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Aliaume Lopez
stage-L3-2016
Commits
4e9dd27b
Commit
4e9dd27b
authored
Dec 28, 2016
by
Aliaume Lopez
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Adding AND and OR gates
parent
7c6417b8
Changes
5
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Showing
5 changed files
with
45 additions
and
11 deletions
+45
-11
circuits.ml
circuits.ml
+3
-0
lines.txt
lines.txt
+6
-10
parser.ml
parser.ml
+2
-0
ptg.ml
ptg.ml
+4
-0
rewriting.ml
rewriting.ml
+30
-1
No files found.
circuits.ml
View file @
4e9dd27b
...
...
@@ -151,6 +151,8 @@ let convert_label = function
|
"PMOS"
->
Gate
Pmos
|
"WAIT"
->
Gate
Wait
|
"DISC"
->
Disconnect
|
"OR"
->
Gate
Or
|
"AND"
->
Gate
And
|
"FORK"
->
Gate
Fork
|
"JOIN"
->
Gate
Join
|
x
->
Gate
(
Box
x
)
...
...
@@ -300,6 +302,7 @@ let rewrite_local rules ptg =
while
not
(
!
inter
==
!
older
)
do
(* test physical equality in constant time *)
older
:=
!
inter
;
inter
:=
apply_local_rules
rules
!
inter
;
report
"LOCAL REWRITE RULE APPLY"
!
inter
;
done
;
!
inter
;;
...
...
lines.txt
View file @
4e9dd27b
let NAND1 = (2 | LOW) . (1 | NMOS) . NMOS in
let NAND2 = (HIGH | 1 | HIGH | 1) . (NMOS | NMOS) . JOIN in
let NAND =
link a0:a1 b0:b1 c1:c0 for
PAR
(a0: | b0:) . :c0
(:a1 | :b1) . NAND1 . c1:
(:a1 | :b1) . NAND2 . c1:
END in
(HIGH | LOW) . NAND
link xO:xI yO:yI for
PAR
xO:
(:xI | :yI) . AND
(:yI | :xI) . OR . yO:
END
parser.ml
View file @
4e9dd27b
...
...
@@ -166,6 +166,8 @@ let circuit_of_name = function
|
"DISC"
->
const
"DISC"
1
0
|
"FORK"
->
const
"FORK"
1
2
|
"JOIN"
->
const
"JOIN"
2
1
|
"AND"
->
const
"AND"
2
1
|
"OR"
->
const
"OR"
2
1
|
x
->
const
x
1
1
;;
(**** THE GRAMMAR
...
...
ptg.ml
View file @
4e9dd27b
...
...
@@ -97,6 +97,8 @@ type gate =
|
Join
|
Nmos
|
Pmos
|
And
|
Or
|
Box
of
string
|
Wait
|
Mux
;;
...
...
@@ -189,6 +191,8 @@ let string_of_gate = function
|
Pmos
->
"P"
|
Box
s
->
"B "
^
s
|
Wait
->
"W"
|
And
->
"AND"
|
Or
->
"OR"
|
Mux
->
"M"
;;
let
rec
string_of_value
=
function
...
...
rewriting.ml
View file @
4e9dd27b
...
...
@@ -220,7 +220,34 @@ let reduce_pmos inputs =
with
Match_failure
_
->
NoOP
;;
(* A small function that gives the lowest common
(* The gate function for the AND gate *)
let
reduce_and
inputs
=
try
let
[
a
;
b
]
=
inputs
in
match
(
a
,
b
)
with
|
Some
(
Value
Low
)
,
_
->
Result
Low
|
_
,
Some
(
Value
Low
)
->
Result
Low
|
Some
(
Value
High
)
,
Some
(
Value
High
)
->
Result
High
|
_
->
NoOP
with
Match_failure
_
->
NoOP
;;
(* The gate function for the OR gate *)
let
reduce_or
inputs
=
try
let
[
a
;
b
]
=
inputs
in
match
(
a
,
b
)
with
|
Some
(
Value
High
)
,
_
->
Result
High
|
_
,
Some
(
Value
High
)
->
Result
High
|
Some
(
Value
Low
)
,
Some
(
Value
Low
)
->
Result
Low
|
_
->
NoOP
with
Match_failure
_
->
NoOP
;;
(*
* A small function that gives the lowest common
* ancestor for two values of the lattice
*)
let
combine_values
v1
v2
=
match
(
v1
,
v2
)
with
...
...
@@ -264,6 +291,8 @@ let fun_of_gate = function
|
Nmos
->
reduce_nmos
|
Pmos
->
reduce_pmos
|
Join
->
reduce_join
|
And
->
reduce_and
|
Or
->
reduce_or
|
_
->
(
fun
_
->
NoOP
);;
(**
...
...
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