From a7edfe40268f2ad435ddeaafafd24453a63c2768 Mon Sep 17 00:00:00 2001
From: blogic <blogic@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Date: Tue, 18 Mar 2014 19:21:56 +0000
Subject: [PATCH] ralink: refresh patches
Signed-off-by: John Crispin <blogic@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39949 3c298f89-4303-0410-b956-a3cf2f4a3e73
---
target/linux/ramips/dts/mt7621.dtsi | 4 +-
.../files/drivers/usb/host/mtk-phy-7621.c | 445 --
.../files/drivers/usb/host/mtk-phy-7621.h | 2871 --------
.../files/drivers/usb/host/mtk-phy-ahb.c | 58 -
.../ramips/files/drivers/usb/host/mtk-phy.c | 102 -
.../ramips/files/drivers/usb/host/mtk-phy.h | 179 -
.../files/drivers/usb/host/xhci-mtk-power.c | 115 -
.../files/drivers/usb/host/xhci-mtk-power.h | 13 -
.../drivers/usb/host/xhci-mtk-scheduler.c | 608 --
.../drivers/usb/host/xhci-mtk-scheduler.h | 77 -
.../ramips/files/drivers/usb/host/xhci-mtk.c | 265 -
.../ramips/files/drivers/usb/host/xhci-mtk.h | 120 -
target/linux/ramips/mt7621/config-3.10 | 33 +
.../ramips/mt7621/profiles/00-default.mk | 2 +-
...e-to-enable-disable-the-cevt-r4k-irq.patch | 31 +-
...01-MIPS-ralink-add-verbose-pmu-info.patch} | 4 +-
...ralink-adds-a-bootrom-dumper-module.patch} | 4 +-
...PS-ralink-add-illegal-access-driver.patch} | 4 +-
...-ralink-workaround-DTB-memory-issue.patch} | 4 +-
...nk-add-missing-clk_set_rate-to-clk.c.patch | 25 +
...MIPS-ralink-add-support-for-MT7620n.patch} | 15 +-
.../ramips/patches-3.10/0106-USB-dwc2.patch | 19 -
...-ralink-allow-manual-memory-override.patch | 45 +
...-MIPS-ralink-add-rt_sysc_m32-helper.patch} | 4 +-
...seudo-pwm-led-trigger-based-on-time.patch} | 6 +-
...a-helper-for-reading-the-ECO-version.patch | 23 +
...11-DMA-ralink-add-rt2880-dma-engine.patch} | 94 +-
...tch => 0112-asoc-add-mt7620-support.patch} | 54 +-
...3-pinctrl-ralink-add-pinctrl-driver.patch} | 2351 +++----
...14-PCI-MIPS-adds-rt2880-pci-support.patch} | 4 +-
...5-PCI-MIPS-adds-mt7620a-pcie-driver.patch} | 24 +-
...patch => 0116-NET-multi-phy-support.patch} | 4 +-
...0117-NET-add-of_get_mac_address_mtd.patch} | 4 +-
...MIPS-add-ralink-SoC-ethernet-driver.patch} | 3383 ++++-----
... 0119-USB-phy-add-ralink-SoC-driver.patch} | 4 +-
...> 0120-USB-add-OHCI-EHCI-OF-binding.patch} | 9 +-
..._otg.patch => 0121-USB-adds-dwc_otg.patch} | 4 +-
...22-serial-ralink-adds-mt7620-serial.patch} | 4 +-
...e-core-has-a-size-of-0x100-and-not-0.patch | 22 +
...w-au1x00-and-rt288x-to-load-from-OF.patch} | 4 +-
...125-i2c-MIPS-adds-ralink-I2C-driver.patch} | 4 +-
...ce-macros-to-set-bits_per_word_mask.patch} | 4 +-
...PS-ralink-add-sdhci-for-mt7620a-SoC.patch} | 4 +-
...-cfi-cmdset-0002-erase-status-check.patch} | 4 +-
...td-cfi-cmdset-0002-force-word-write.patch} | 4 +-
...0-mtd-ralink-add-mt7620-nand-driver.patch} | 7 +-
...1-mtd-add-chunked-read-io-to-m25p80.patch} | 4 +-
...0132-GPIO-add-gpio_export_with_name.patch} | 4 +-
...133-uvc-add-iPassion-iP2970-support.patch} | 15 +-
...ch => 0134-mtd-split-remove-padding.patch} | 0
...e-hazards-for-R2-cores-in-the-TLB-re.patch | 60 +
...-Fix-gic_set_affinity-infinite-loop.patch} | 4 +-
...-calculations-when-using-MT-support.patch} | 4 +-
...ng-to-per-cpu-data-when-flushing-the.patch | 84 +
...rt5350-fix-enable-uartf-kernel-panic.patch | 11 -
...74K-1074K-Correct-erratum-workaround.patch | 60 +
...05-MIPS-GIC-Send-IPIs-using-the-GIC.patch} | 4 +-
...0206-MIPS-ralink-add-MT7621-support.patch} | 232 +-
...207-MIPS-ralink-add-MT7621-defconfig.patch | 211 +
...0208-MIPS-ralink-add-MT7621-dts-file.patch | 300 +
...ink-add-MT7621-early_printk-support.patch} | 16 +-
...-MIPS-ralink-add-MT7621-pcie-driver.patch} | 14 +-
...=> 0211-watchdog-add-MT7621-support.patch} | 48 +-
...O-ralink-add-mt7621-gpio-controller.patch} | 50 +-
...=> 0213-MTD-add-mt7621-nand-support.patch} | 34 +-
.../0214-usb-add-mt7621-xhci-support.patch | 5768 ++++++++++++++++
... 0215-SPI-ralink-add-mt7621-support.patch} | 38 +-
...alink-add-mt7621-SDK-ethernet-driver.patch | 6045 +++++++++++++++++
.../patches-3.10/0217-pinmux-rt2880.patch | 88 +
...B-secion.patch => 0300-MIPS-OWRTDTB.patch} | 12 +-
.../0501-MIPS-increase-GIC_INTR_MAX.patch | 21 -
...-support-needs-to-select-SMP-as-well.patch | 52 -
...0512-USB-add-xhci-support-for-mt7621.patch | 840 ---
.../linux/ramips/patches-3.10/800-eco.patch | 12 -
.../linux/ramips/patches-3.10/999-clk.patch | 17 -
.../patches-3.10/999-memory-detect.patch | 32 -
.../patches-3.10/999-pinctrl_fixes.patch | 33 -
.../ramips/patches-3.10/999-raeth_fixes.patch | 21 -
target/linux/ramips/rt288x/config-3.10 | 4 +
79 files changed, 16104 insertions(+), 9102 deletions(-)
delete mode 100644 target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.c
delete mode 100644 target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.h
delete mode 100644 target/linux/ramips/files/drivers/usb/host/mtk-phy-ahb.c
delete mode 100644 target/linux/ramips/files/drivers/usb/host/mtk-phy.c
delete mode 100644 target/linux/ramips/files/drivers/usb/host/mtk-phy.h
delete mode 100644 target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.c
delete mode 100644 target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.h
delete mode 100644 target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.c
delete mode 100644 target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.h
delete mode 100644 target/linux/ramips/files/drivers/usb/host/xhci-mtk.c
delete mode 100644 target/linux/ramips/files/drivers/usb/host/xhci-mtk.h
rename target/linux/ramips/patches-3.10/{0102-MIPS-ralink-add-verbose-pmu-info.patch => 0101-MIPS-ralink-add-verbose-pmu-info.patch} (92%)
rename target/linux/ramips/patches-3.10/{0103-MIPS-ralink-adds-a-bootrom-dumper-module.patch => 0102-MIPS-ralink-adds-a-bootrom-dumper-module.patch} (93%)
rename target/linux/ramips/patches-3.10/{0104-MIPS-ralink-add-illegal-access-driver.patch => 0103-MIPS-ralink-add-illegal-access-driver.patch} (95%)
rename target/linux/ramips/patches-3.10/{0105-MIPS-ralink-workaround-DTB-memory-issue.patch => 0104-MIPS-ralink-workaround-DTB-memory-issue.patch} (82%)
create mode 100644 target/linux/ramips/patches-3.10/0105-MIPS-ralink-add-missing-clk_set_rate-to-clk.c.patch
rename target/linux/ramips/patches-3.10/{999-mt7620n.patch => 0106-MIPS-ralink-add-support-for-MT7620n.patch} (74%)
delete mode 100644 target/linux/ramips/patches-3.10/0106-USB-dwc2.patch
create mode 100644 target/linux/ramips/patches-3.10/0107-MIPS-ralink-allow-manual-memory-override.patch
rename target/linux/ramips/patches-3.10/{0121-MIPS-ralink-add-rt_sysc_m32-helper.patch => 0108-MIPS-ralink-add-rt_sysc_m32-helper.patch} (85%)
rename target/linux/ramips/patches-3.10/{0201-owrt-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on.patch => 0109-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on-time.patch} (98%)
create mode 100644 target/linux/ramips/patches-3.10/0110-MIPS-ralink-add-a-helper-for-reading-the-ECO-version.patch
rename target/linux/ramips/patches-3.10/{0300-DMA-add-rt2880-dma-engine.patch => 0111-DMA-ralink-add-rt2880-dma-engine.patch} (98%)
rename target/linux/ramips/patches-3.10/{0301-asoc-add-mt7620-support.patch => 0112-asoc-add-mt7620-support.patch} (97%)
rename target/linux/ramips/patches-3.10/{0122-pinmux.patch => 0113-pinctrl-ralink-add-pinctrl-driver.patch} (96%)
rename target/linux/ramips/patches-3.10/{0107-PCI-MIPS-adds-rt2880-pci-support.patch => 0114-PCI-MIPS-adds-rt2880-pci-support.patch} (98%)
rename target/linux/ramips/patches-3.10/{0108-PCI-MIPS-adds-mt7620a-pcie-driver.patch => 0115-PCI-MIPS-adds-mt7620a-pcie-driver.patch} (98%)
rename target/linux/ramips/patches-3.10/{0109-NET-multi-phy-support.patch => 0116-NET-multi-phy-support.patch} (93%)
rename target/linux/ramips/patches-3.10/{0110-NET-add-of_get_mac_address_mtd.patch => 0117-NET-add-of_get_mac_address_mtd.patch} (94%)
rename target/linux/ramips/patches-3.10/{0111-NET-MIPS-add-ralink-SoC-ethernet-driver.patch => 0118-NET-MIPS-add-ralink-SoC-ethernet-driver.patch} (99%)
rename target/linux/ramips/patches-3.10/{0112-USB-phy-add-ralink-SoC-driver.patch => 0119-USB-phy-add-ralink-SoC-driver.patch} (98%)
rename target/linux/ramips/patches-3.10/{0113-USB-add-OHCI-EHCI-OF-binding.patch => 0120-USB-add-OHCI-EHCI-OF-binding.patch} (94%)
rename target/linux/ramips/patches-3.10/{0202-owrt-USB-adds-dwc_otg.patch => 0121-USB-adds-dwc_otg.patch} (99%)
rename target/linux/ramips/patches-3.10/{0114-serial-ralink-adds-mt7620-serial.patch => 0122-serial-ralink-adds-mt7620-serial.patch} (86%)
create mode 100644 target/linux/ramips/patches-3.10/0123-serial-ralink-the-core-has-a-size-of-0x100-and-not-0.patch
rename target/linux/ramips/patches-3.10/{0115-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch => 0124-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch} (84%)
rename target/linux/ramips/patches-3.10/{0116-i2c-MIPS-adds-ralink-I2C-driver.patch => 0125-i2c-MIPS-adds-ralink-I2C-driver.patch} (98%)
rename target/linux/ramips/patches-3.10/{0120-spi-introduce-macros-to-set-bits_per_word_mask.patch => 0126-spi-introduce-macros-to-set-bits_per_word_mask.patch} (87%)
rename target/linux/ramips/patches-3.10/{0117-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch => 0127-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch} (99%)
rename target/linux/ramips/patches-3.10/{0118-mtd-fix-cfi-cmdset-0002-erase-status-check.patch => 0128-mtd-fix-cfi-cmdset-0002-erase-status-check.patch} (84%)
rename target/linux/ramips/patches-3.10/{0119-mtd-cfi-cmdset-0002-force-word-write.patch => 0129-mtd-cfi-cmdset-0002-force-word-write.patch} (94%)
rename target/linux/ramips/patches-3.10/{0250-nand-7620.patch => 0130-mtd-ralink-add-mt7620-nand-driver.patch} (99%)
rename target/linux/ramips/patches-3.10/{0206-MTD-add-chunked-read-io-to-m25p80.patch => 0131-mtd-add-chunked-read-io-to-m25p80.patch} (96%)
rename target/linux/ramips/patches-3.10/{0200-owrt-GPIO-add-gpio_export_with_name.patch => 0132-GPIO-add-gpio_export_with_name.patch} (98%)
rename target/linux/ramips/patches-3.10/{0205-uvc-add-iPassion-iP2970-support.patch => 0133-uvc-add-iPassion-iP2970-support.patch} (93%)
rename target/linux/ramips/patches-3.10/{0204-owrt-mtd-split-remove-padding.patch => 0134-mtd-split-remove-padding.patch} (100%)
create mode 100644 target/linux/ramips/patches-3.10/0200-MIPS-Fix-TLBR-use-hazards-for-R2-cores-in-the-TLB-re.patch
rename target/linux/ramips/patches-3.10/{0508-MIPS-GIC-Fix-gic_set_affinity-infinite-loop.patch => 0201-MIPS-GIC-Fix-gic_set_affinity-infinite-loop.patch} (91%)
rename target/linux/ramips/patches-3.10/{0510-MIPS-Fix-SMP-core-calculations-when-using-MT-support.patch => 0202-MIPS-Fix-SMP-core-calculations-when-using-MT-support.patch} (93%)
create mode 100644 target/linux/ramips/patches-3.10/0203-MIPS-Fix-accessing-to-per-cpu-data-when-flushing-the.patch
delete mode 100644 target/linux/ramips/patches-3.10/0203-serial-rt5350-fix-enable-uartf-kernel-panic.patch
create mode 100644 target/linux/ramips/patches-3.10/0204-MIPS-74K-1074K-Correct-erratum-workaround.patch
rename target/linux/ramips/patches-3.10/{0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch => 0205-MIPS-GIC-Send-IPIs-using-the-GIC.patch} (95%)
rename target/linux/ramips/patches-3.10/{0502-MIPS-ralink-add-MT7621-support.patch => 0206-MIPS-ralink-add-MT7621-support.patch} (77%)
create mode 100644 target/linux/ramips/patches-3.10/0207-MIPS-ralink-add-MT7621-defconfig.patch
create mode 100644 target/linux/ramips/patches-3.10/0208-MIPS-ralink-add-MT7621-dts-file.patch
rename target/linux/ramips/patches-3.10/{0503-MIPS-ralink-add-MT7621-early_printk-support.patch => 0209-MIPS-ralink-add-MT7621-early_printk-support.patch} (68%)
rename target/linux/ramips/patches-3.10/{0504-MIPS-ralink-add-pcie-driver.patch => 0210-MIPS-ralink-add-MT7621-pcie-driver.patch} (99%)
rename target/linux/ramips/patches-3.10/{0505-watchdog-add-MT7621-support.patch => 0211-watchdog-add-MT7621-support.patch} (82%)
rename target/linux/ramips/patches-3.10/{0506-GPIO-ralink-add-mt7621-gpio-controller.patch => 0212-GPIO-ralink-add-mt7621-gpio-controller.patch} (76%)
rename target/linux/ramips/patches-3.10/{0507-MTD-add-mt7621-nand-support.patch => 0213-MTD-add-mt7621-nand-support.patch} (99%)
create mode 100644 target/linux/ramips/patches-3.10/0214-usb-add-mt7621-xhci-support.patch
rename target/linux/ramips/patches-3.10/{0500-spi-mt7621.patch => 0215-SPI-ralink-add-mt7621-support.patch} (87%)
create mode 100644 target/linux/ramips/patches-3.10/0216-NET-ralink-add-mt7621-SDK-ethernet-driver.patch
create mode 100644 target/linux/ramips/patches-3.10/0217-pinmux-rt2880.patch
rename target/linux/ramips/patches-3.10/{0203-owrt-MIPS-add-OWRTDTB-secion.patch => 0300-MIPS-OWRTDTB.patch} (80%)
delete mode 100644 target/linux/ramips/patches-3.10/0501-MIPS-increase-GIC_INTR_MAX.patch
delete mode 100644 target/linux/ramips/patches-3.10/0509-MIPS-Kconfig-CMP-support-needs-to-select-SMP-as-well.patch
delete mode 100644 target/linux/ramips/patches-3.10/0512-USB-add-xhci-support-for-mt7621.patch
delete mode 100644 target/linux/ramips/patches-3.10/800-eco.patch
delete mode 100644 target/linux/ramips/patches-3.10/999-clk.patch
delete mode 100644 target/linux/ramips/patches-3.10/999-memory-detect.patch
delete mode 100644 target/linux/ramips/patches-3.10/999-pinctrl_fixes.patch
delete mode 100644 target/linux/ramips/patches-3.10/999-raeth_fixes.patch
diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
index 9fa9d0a5fa..83df878e9c 100644
--- a/target/linux/ramips/dts/mt7621.dtsi
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -72,8 +72,8 @@
compatible = "ns16550a";
reg = <0xc00 0x100>;
-/* interrupt-parent = <&gic>;
- interrupts = <26>;*/
+ interrupt-parent = <&gic>;
+ interrupts = <26>;
reg-shift = <2>;
reg-io-width = <4>;
diff --git a/target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.c b/target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.c
deleted file mode 100644
index 4e9c0d7a8d..0000000000
--- a/target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.c
+++ /dev/null
@@ -1,445 +0,0 @@
-#include "mtk-phy.h"
-
-#ifdef CONFIG_PROJECT_7621
-#include "mtk-phy-7621.h"
-
-//not used on SoC
-PHY_INT32 phy_init(struct u3phy_info *info){
- return PHY_TRUE;
-}
-
-//not used on SoC
-PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
- return PHY_TRUE;
-}
-
-//--------------------------------------------------------
-// Function : fgEyeScanHelper_CheckPtInRegion()
-// Description : Check if the test point is in a rectangle region.
-// If it is in the rectangle, also check if this point
-// is on the multiple of deltaX and deltaY.
-// Parameter : strucScanRegion * prEye - the region
-// BYTE bX
-// BYTE bY
-// Return : BYTE - TRUE : This point needs to be tested
-// FALSE: This point will be omitted
-// Note : First check within the rectangle.
-// Secondly, use modulous to check if the point will be tested.
-//--------------------------------------------------------
-static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
-{
- PHY_INT8 fgValid = true;
-
-
- /// Be careful, the axis origin is on the TOP-LEFT corner.
- /// Therefore the top-left point has the minimum X and Y
- /// Botton-right point is the maximum X and Y
- if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
- && (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
- {
- // With the region, now check whether or not the input test point is
- // on the multiples of X and Y
- // Do not have to worry about negative value, because we have already
- // check the input bX, and bY is within the region.
- if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
- || ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
- {
- // if the division will have remainder, that means
- // the input test point is on the multiples of X and Y
- fgValid = false;
- }
- else
- {
- }
- }
- else
- {
-
- fgValid = false;
- }
- return fgValid;
-}
-
-//--------------------------------------------------------
-// Function : EyeScanHelper_RunTest()
-// Description : Enable the test, and wait til it is completed
-// Parameter : None
-// Return : None
-// Note : None
-//--------------------------------------------------------
-static void EyeScanHelper_RunTest(struct u3phy_info *info)
-{
- DRV_UDELAY(100);
- // Disable the test
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0); //RG_SSUSB_RX_EYE_CNT_EN = 0
- DRV_UDELAY(100);
- // Run the test
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1); //RG_SSUSB_RX_EYE_CNT_EN = 1
- DRV_UDELAY(100);
- // Wait til it's done
- //RGS_SSUSB_RX_EYE_CNT_RDY
- while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
- , RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
-}
-
-//--------------------------------------------------------
-// Function : fgEyeScanHelper_CalNextPoint()
-// Description : Calcualte the test point for the measurement
-// Parameter : None
-// Return : BOOL - TRUE : the next point is within the
-// boundaryof HW limit
-// FALSE: the next point is out of the HW limit
-// Note : The next point is obtained by calculating
-// from the bottom left of the region rectangle
-// and then scanning up until it reaches the upper
-// limit. At this time, the x will increment, and
-// start scanning downwards until the y hits the
-// zero.
-//--------------------------------------------------------
-static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
-{
- if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
- || ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
- )
- {
- /// Reaches the limit of Y axis
- /// Increment X
- _bXcurr++;
- _fgXChged = true;
- _eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
-
- if (_bXcurr > MAX_X)
- {
- return false;
- }
- }
- else
- {
- _bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
- _fgXChged = false;
- }
- return PHY_TRUE;
-}
-
-PHY_INT32 eyescan_init(struct u3phy_info *info){
- //initial PHY setting
- U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
- , RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
- , RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
- , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
- , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
- return PHY_TRUE;
-}
-
-PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
- , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
- PHY_INT32 cOfst = 0;
- PHY_UINT8 bIdxX = 0;
- PHY_UINT8 bIdxY = 0;
- //PHY_INT8 bCnt = 0;
- PHY_UINT8 bIdxCycCnt = 0;
- PHY_INT8 fgValid;
- PHY_INT8 cX;
- PHY_INT8 cY;
- PHY_UINT8 bExtendCnt;
- PHY_INT8 isContinue;
- //PHY_INT8 isBreak;
- PHY_UINT32 wErr0 = 0, wErr1 = 0;
- //PHY_UINT32 temp;
-
- PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
- PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
-
- _rEye1.bX_tl = x_t1;
- _rEye1.bY_tl = y_t1;
- _rEye1.bX_br = x_br;
- _rEye1.bY_br = y_br;
- _rEye1.bDeltaX = delta_x;
- _rEye1.bDeltaY = delta_y;
-
- _rEye2.bX_tl = x_t1;
- _rEye2.bY_tl = y_t1;
- _rEye2.bX_br = x_br;
- _rEye2.bY_br = y_br;
- _rEye2.bDeltaX = delta_x;
- _rEye2.bDeltaY = delta_y;
-
- _rTestCycle.wEyeCnt = eye_cnt;
- _rTestCycle.bNumOfEyeCnt = num_cnt;
- _rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
- _rTestCycle.bPICalEn = PI_cal_en;
-
- _bXcurr = 0;
- _bYcurr = 0;
- _eScanDir = SCAN_DN;
- _fgXChged = false;
-
- printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
- eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
- x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);
-
- //force SIGDET to OFF
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
- , RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1); //RG_SSUSB_RX_SIGDET_SEL = 1
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
- , RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0); //RG_SSUSB_RX_SIGDET_EN = 0
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
- , RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0); //RG_SSUSB_RX_SIGDET = 0
-
- // RX_TRI_DET_EN to Disable
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
- , RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0); //RG_SSUSB_RX_TRI_DET_EN = 0
-
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0); //RG_SSUSB_RX_EYE_XOFFSET = 0
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0); //RG_SSUSB_RX_EYE0_Y = 0
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0); //RG_SSUSB_RX_EYE1_Y = 0
-
-
- if (PI_cal_en){
- // PI Calibration
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
- , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
- , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
- , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
-
- DRV_UDELAY(20);
-
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
- , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
- _bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
- , RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO); //read RGS_SSUSB_RX_PILPO
-
- printk(KERN_ERR "PI result: %d\n", _bPIResult);
- }
- // Read Initial DAC
- // Set CYCLE
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
- ,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt); //RG_SSUSB_RX_EYE_CNT
-
- // Eye Monitor Feature
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
- , RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff); //RG_SSUSB_RX_EYE_MASK = 0x3ff
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
-
- // Move X,Y to the top-left corner
- for (cOfst = 0; cOfst >= -64; cOfst--)
- {
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- ,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
- }
- for (cOfst = 0; cOfst < 64; cOfst++)
- {
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst); //RG_SSUSB_RX_EYE0_Y
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst); //RG_SSUSB_RX_EYE1_Y
- }
- //ClearErrorResult
- for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
- for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
- {
- for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
- pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
- pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
- }
- }
- }
- isContinue = true;
- while(isContinue){
- //printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
- // The point is within the boundary, then let's check if it is within
- // the testing region.
- // The point is only test-able if one of the eye region
- // includes this point.
- fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
- || fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
- // Translate bX and bY to 2's complement from where the origin was on the
- // top left corner.
- // 0x40 and 0x3F needs a bit of thinking!!!! >"<
- cX = (_bXcurr ^ 0x40);
- cY = (_bYcurr ^ 0x3F);
-
- // Set X if necessary
- if (_fgXChged == true)
- {
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX); //RG_SSUSB_RX_EYE_XOFFSET
- }
- // Set Y
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY); //RG_SSUSB_RX_EYE0_Y
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY); //RG_SSUSB_RX_EYE1_Y
-
- /// Test this point!
- if (fgValid){
- for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
- {
- //run test
- EyeScanHelper_RunTest(info);
- }
- for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
- {
- EyeScanHelper_RunTest(info);
- wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
- , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
- wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
- , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
-
- pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
- pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr] = wErr1;
-
- //EyeScanHelper_GetResult(&_rRes.pwErrCnt0[bCnt], &_rRes.pwErrCnt1[bCnt]);
-// printk(KERN_ERR "cnt[%d] cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n"
-// , bExtendCnt, _bXcurr, _bYcurr, cX, cY, pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr], pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr]);
- }
- //printk(KERN_ERR "cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n", _bXcurr, _bYcurr, cX, cY, pwErrCnt0[0][_bXcurr][_bYcurr], pwErrCnt1[0][_bXcurr][_bYcurr]);
- }
- else{
-
- }
- if (fgEyeScanHelper_CalNextPoint() == false){
-#if 0
- printk(KERN_ERR "Xcurr [0x%x] Ycurr [0x%x]\n", _bXcurr, _bYcurr);
- printk(KERN_ERR "XcurrREG [0x%x] YcurrREG [0x%x]\n", cX, cY);
-#endif
- printk(KERN_ERR "end of eye scan\n");
- isContinue = false;
- }
- }
- printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
- , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
- , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
-
- // Move X,Y to the top-left corner
- for (cOfst = 63; cOfst >= 0; cOfst--)
- {
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
- }
- for (cOfst = 63; cOfst >= 0; cOfst--)
- {
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);
- U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
- , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);
-
- }
- printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
- , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
- , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
-
- printk(KERN_ERR "PI result: %d\n", _bPIResult);
- printk(KERN_ERR "pwErrCnt0 addr: 0x%x\n", (PHY_UINT32)pwErrCnt0);
- printk(KERN_ERR "pwErrCnt1 addr: 0x%x\n", (PHY_UINT32)pwErrCnt1);
-
- return PHY_TRUE;
-}
-
-//not used on SoC
-PHY_INT32 u2_save_cur_en(struct u3phy_info *info){
- return PHY_TRUE;
-}
-
-//not used on SoC
-PHY_INT32 u2_save_cur_re(struct u3phy_info *info){
- return PHY_TRUE;
-}
-
-PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info){
- PHY_INT32 i=0;
- //PHY_INT32 j=0;
- //PHY_INT8 u1SrCalVal = 0;
- //PHY_INT8 u1Reg_addr_HSTX_SRCAL_EN;
- PHY_INT32 fgRet = 0;
- PHY_INT32 u4FmOut = 0;
- PHY_INT32 u4Tmp = 0;
- //PHY_INT32 temp;
-
- // => RG_USB20_HSTX_SRCAL_EN = 1
- // enable HS TX SR calibration
- U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
- , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0x1);
- DRV_MSLEEP(1);
-
- // => RG_FRCK_EN = 1
- // Enable free run clock
- U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
- , RG_FRCK_EN_OFST, RG_FRCK_EN, 1);
-
- // MT6290 HS signal quality patch
- // => RG_CYCLECNT = 400
- // Setting cyclecnt =400
- U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
- , RG_CYCLECNT_OFST, RG_CYCLECNT, 0x400);
-
- // => RG_FREQDET_EN = 1
- // Enable frequency meter
- U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
- , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0x1);
-
- // wait for FM detection done, set 10ms timeout
- for(i=0; i<10; i++){
- // => u4FmOut = USB_FM_OUT
- // read FM_OUT
- u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr0));
- printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
-
- // check if FM detection done
- if (u4FmOut != 0)
- {
- fgRet = 0;
- printk("FM detection done! loop = %d\n", i);
-
- break;
- }
-
- fgRet = 1;
- DRV_MSLEEP(1);
- }
- // => RG_FREQDET_EN = 0
- // disable frequency meter
- U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
- , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0);
-
- // => RG_FRCK_EN = 0
- // disable free run clock
- U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
- , RG_FRCK_EN_OFST, RG_FRCK_EN, 0);
-
- // => RG_USB20_HSTX_SRCAL_EN = 0
- // disable HS TX SR calibration
- U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
- , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0);
- DRV_MSLEEP(1);
-
- if(u4FmOut == 0){
- U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
- , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, 0x4);
-
- fgRet = 1;
- }
- else{
- // set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
- u4Tmp = (((1024 * 25 * U2_SR_COEF_7621) / u4FmOut) + 500) / 1000;
- printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
- U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
- , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, u4Tmp);
- }
- return fgRet;
-}
-
-#endif
diff --git a/target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.h b/target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.h
deleted file mode 100644
index 41b0c7744b..0000000000
--- a/target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.h
+++ /dev/null
@@ -1,2871 +0,0 @@
-#ifdef CONFIG_PROJECT_7621
-#ifndef __MTK_PHY_7621_H
-#define __MTK_PHY_7621_H
-
-#define U2_SR_COEF_7621 28
-
-///////////////////////////////////////////////////////////////////////////////
-
-struct u2phy_reg {
- //0x0
- PHY_LE32 u2phyac0;
- PHY_LE32 u2phyac1;
- PHY_LE32 u2phyac2;
- PHY_LE32 reserve0;
- //0x10
- PHY_LE32 u2phyacr0;
- PHY_LE32 u2phyacr1;
- PHY_LE32 u2phyacr2;
- PHY_LE32 u2phyacr3;
- //0x20
- PHY_LE32 u2phyacr4;
- PHY_LE32 u2phyamon0;
- PHY_LE32 reserve1[2];
- //0x30~0x50
- PHY_LE32 reserve2[12];
- //0x60
- PHY_LE32 u2phydcr0;
- PHY_LE32 u2phydcr1;
- PHY_LE32 u2phydtm0;
- PHY_LE32 u2phydtm1;
- //0x70
- PHY_LE32 u2phydmon0;
- PHY_LE32 u2phydmon1;
- PHY_LE32 u2phydmon2;
- PHY_LE32 u2phydmon3;
- //0x80
- PHY_LE32 u2phybc12c;
- PHY_LE32 u2phybc12c1;
- PHY_LE32 reserve3[2];
- //0x90~0xe0
- PHY_LE32 reserve4[24];
- //0xf0
- PHY_LE32 reserve6[3];
- PHY_LE32 regfcom;
-};
-
-//U3D_U2PHYAC0
-#define RG_USB20_USBPLL_DIVEN (0x7<<28) //30:28
-#define RG_USB20_USBPLL_CKCTRL (0x3<<26) //27:26
-#define RG_USB20_USBPLL_PREDIV (0x3<<24) //25:24
-#define RG_USB20_USBPLL_FORCE_ON (0x1<<23) //23:23
-#define RG_USB20_USBPLL_FBDIV (0x7f<<16) //22:16
-#define RG_USB20_REF_EN (0x1<<15) //15:15
-#define RG_USB20_INTR_EN (0x1<<14) //14:14
-#define RG_USB20_BG_TRIM (0xf<<8) //11:8
-#define RG_USB20_BG_RBSEL (0x3<<6) //7:6
-#define RG_USB20_BG_RASEL (0x3<<4) //5:4
-#define RG_USB20_BGR_DIV (0x3<<2) //3:2
-#define RG_SIFSLV_CHP_EN (0x1<<1) //1:1
-#define RG_SIFSLV_BGR_EN (0x1<<0) //0:0
-
-//U3D_U2PHYAC1
-#define RG_USB20_VRT_VREF_SEL (0x7<<28) //30:28
-#define RG_USB20_TERM_VREF_SEL (0x7<<24) //26:24
-#define RG_USB20_MPX_SEL (0xff<<16) //23:16
-#define RG_USB20_MPX_OUT_SEL (0x3<<12) //13:12
-#define RG_USB20_TX_PH_ROT_SEL (0x7<<8) //10:8
-#define RG_USB20_USBPLL_ACCEN (0x1<<3) //3:3
-#define RG_USB20_USBPLL_LF (0x1<<2) //2:2
-#define RG_USB20_USBPLL_BR (0x1<<1) //1:1
-#define RG_USB20_USBPLL_BP (0x1<<0) //0:0
-
-//U3D_U2PHYAC2
-#define RG_SIFSLV_MAC_BANDGAP_EN (0x1<<17) //17:17
-#define RG_SIFSLV_MAC_CHOPPER_EN (0x1<<16) //16:16
-#define RG_USB20_CLKREF_REV (0xff<<0) //7:0
-
-//U3D_U2PHYACR0
-#define RG_USB20_ICUSB_EN (0x1<<24) //24:24
-#define RG_USB20_HSTX_SRCAL_EN (0x1<<23) //23:23
-#define RG_USB20_HSTX_SRCTRL (0x7<<16) //18:16
-#define RG_USB20_LS_CR (0x7<<12) //14:12
-#define RG_USB20_FS_CR (0x7<<8) //10:8
-#define RG_USB20_LS_SR (0x7<<4) //6:4
-#define RG_USB20_FS_SR (0x7<<0) //2:0
-
-//U3D_U2PHYACR1
-#define RG_USB20_INIT_SQ_EN_DG (0x3<<28) //29:28
-#define RG_USB20_SQD (0x3<<24) //25:24
-#define RG_USB20_HSTX_TMODE_SEL (0x3<<20) //21:20
-#define RG_USB20_HSTX_TMODE_EN (0x1<<19) //19:19
-#define RG_USB20_PHYD_MONEN (0x1<<18) //18:18
-#define RG_USB20_INLPBK_EN (0x1<<17) //17:17
-#define RG_USB20_CHIRP_EN (0x1<<16) //16:16
-#define RG_USB20_DM_ABIST_SOURCE_EN (0x1<<15) //15:15
-#define RG_USB20_DM_ABIST_SELE (0xf<<8) //11:8
-#define RG_USB20_DP_ABIST_SOURCE_EN (0x1<<7) //7:7
-#define RG_USB20_DP_ABIST_SELE (0xf<<0) //3:0
-
-//U3D_U2PHYACR2
-#define RG_USB20_OTG_ABIST_SELE (0x7<<29) //31:29
-#define RG_USB20_OTG_ABIST_EN (0x1<<28) //28:28
-#define RG_USB20_OTG_VBUSCMP_EN (0x1<<27) //27:27
-#define RG_USB20_OTG_VBUSTH (0x7<<24) //26:24
-#define RG_USB20_DISC_FIT_EN (0x1<<22) //22:22
-#define RG_USB20_DISCD (0x3<<20) //21:20
-#define RG_USB20_DISCTH (0xf<<16) //19:16
-#define RG_USB20_SQCAL_EN (0x1<<15) //15:15
-#define RG_USB20_SQCAL (0xf<<8) //11:8
-#define RG_USB20_SQTH (0xf<<0) //3:0
-
-//U3D_U2PHYACR3
-#define RG_USB20_HSTX_DBIST (0xf<<28) //31:28
-#define RG_USB20_HSTX_BIST_EN (0x1<<26) //26:26
-#define RG_USB20_HSTX_I_EN_MODE (0x3<<24) //25:24
-#define RG_USB20_HSRX_TMODE_EN (0x1<<23) //23:23
-#define RG_USB20_HSRX_BIAS_EN_SEL (0x3<<20) //21:20
-#define RG_USB20_USB11_TMODE_EN (0x1<<19) //19:19
-#define RG_USB20_TMODE_FS_LS_TX_EN (0x1<<18) //18:18
-#define RG_USB20_TMODE_FS_LS_RCV_EN (0x1<<17) //17:17
-#define RG_USB20_TMODE_FS_LS_MODE (0x1<<16) //16:16
-#define RG_USB20_HS_TERM_EN_MODE (0x3<<13) //14:13
-#define RG_USB20_PUPD_BIST_EN (0x1<<12) //12:12
-#define RG_USB20_EN_PU_DM (0x1<<11) //11:11
-#define RG_USB20_EN_PD_DM (0x1<<10) //10:10
-#define RG_USB20_EN_PU_DP (0x1<<9) //9:9
-#define RG_USB20_EN_PD_DP (0x1<<8) //8:8
-#define RG_USB20_PHY_REV (0xff<<0) //7:0
-
-//U3D_U2PHYACR4
-#define RG_USB20_DP_100K_MODE (0x1<<18) //18:18
-#define RG_USB20_DM_100K_EN (0x1<<17) //17:17
-#define USB20_DP_100K_EN (0x1<<16) //16:16
-#define USB20_GPIO_DM_I (0x1<<15) //15:15
-#define USB20_GPIO_DP_I (0x1<<14) //14:14
-#define USB20_GPIO_DM_OE (0x1<<13) //13:13
-#define USB20_GPIO_DP_OE (0x1<<12) //12:12
-#define RG_USB20_GPIO_CTL (0x1<<9) //9:9
-#define USB20_GPIO_MODE (0x1<<8) //8:8
-#define RG_USB20_TX_BIAS_EN (0x1<<5) //5:5
-#define RG_USB20_TX_VCMPDN_EN (0x1<<4) //4:4
-#define RG_USB20_HS_SQ_EN_MODE (0x3<<2) //3:2
-#define RG_USB20_HS_RCV_EN_MODE (0x3<<0) //1:0
-
-//U3D_U2PHYAMON0
-#define RGO_USB20_GPIO_DM_O (0x1<<1) //1:1
-#define RGO_USB20_GPIO_DP_O (0x1<<0) //0:0
-
-//U3D_U2PHYDCR0
-#define RG_USB20_CDR_TST (0x3<<30) //31:30
-#define RG_USB20_GATED_ENB (0x1<<29) //29:29
-#define RG_USB20_TESTMODE (0x3<<26) //27:26
-#define RG_USB20_PLL_STABLE (0x1<<25) //25:25
-#define RG_USB20_PLL_FORCE_ON (0x1<<24) //24:24
-#define RG_USB20_PHYD_RESERVE (0xffff<<8) //23:8
-#define RG_USB20_EBTHRLD (0x1<<7) //7:7
-#define RG_USB20_EARLY_HSTX_I (0x1<<6) //6:6
-#define RG_USB20_TX_TST (0x1<<5) //5:5
-#define RG_USB20_NEGEDGE_ENB (0x1<<4) //4:4
-#define RG_USB20_CDR_FILT (0xf<<0) //3:0
-
-//U3D_U2PHYDCR1
-#define RG_USB20_PROBE_SEL (0xff<<24) //31:24
-#define RG_USB20_DRVVBUS (0x1<<23) //23:23
-#define RG_DEBUG_EN (0x1<<22) //22:22
-#define RG_USB20_OTG_PROBE (0x3<<20) //21:20
-#define RG_USB20_SW_PLLMODE (0x3<<18) //19:18
-#define RG_USB20_BERTH (0x3<<16) //17:16
-#define RG_USB20_LBMODE (0x3<<13) //14:13
-#define RG_USB20_FORCE_TAP (0x1<<12) //12:12
-#define RG_USB20_TAPSEL (0xfff<<0) //11:0
-
-//U3D_U2PHYDTM0
-#define RG_UART_MODE (0x3<<30) //31:30
-#define FORCE_UART_I (0x1<<29) //29:29
-#define FORCE_UART_BIAS_EN (0x1<<28) //28:28
-#define FORCE_UART_TX_OE (0x1<<27) //27:27
-#define FORCE_UART_EN (0x1<<26) //26:26
-#define FORCE_USB_CLKEN (0x1<<25) //25:25
-#define FORCE_DRVVBUS (0x1<<24) //24:24
-#define FORCE_DATAIN (0x1<<23) //23:23
-#define FORCE_TXVALID (0x1<<22) //22:22
-#define FORCE_DM_PULLDOWN (0x1<<21) //21:21
-#define FORCE_DP_PULLDOWN (0x1<<20) //20:20
-#define FORCE_XCVRSEL (0x1<<19) //19:19
-#define FORCE_SUSPENDM (0x1<<18) //18:18
-#define FORCE_TERMSEL (0x1<<17) //17:17
-#define FORCE_OPMODE (0x1<<16) //16:16
-#define UTMI_MUXSEL (0x1<<15) //15:15
-#define RG_RESET (0x1<<14) //14:14
-#define RG_DATAIN (0xf<<10) //13:10
-#define RG_TXVALIDH (0x1<<9) //9:9
-#define RG_TXVALID (0x1<<8) //8:8
-#define RG_DMPULLDOWN (0x1<<7) //7:7
-#define RG_DPPULLDOWN (0x1<<6) //6:6
-#define RG_XCVRSEL (0x3<<4) //5:4
-#define RG_SUSPENDM (0x1<<3) //3:3
-#define RG_TERMSEL (0x1<<2) //2:2
-#define RG_OPMODE (0x3<<0) //1:0
-
-//U3D_U2PHYDTM1
-#define RG_USB20_PRBS7_EN (0x1<<31) //31:31
-#define RG_USB20_PRBS7_BITCNT (0x3f<<24) //29:24
-#define RG_USB20_CLK48M_EN (0x1<<23) //23:23
-#define RG_USB20_CLK60M_EN (0x1<<22) //22:22
-#define RG_UART_I (0x1<<19) //19:19
-#define RG_UART_BIAS_EN (0x1<<18) //18:18
-#define RG_UART_TX_OE (0x1<<17) //17:17
-#define RG_UART_EN (0x1<<16) //16:16
-#define FORCE_VBUSVALID (0x1<<13) //13:13
-#define FORCE_SESSEND (0x1<<12) //12:12
-#define FORCE_BVALID (0x1<<11) //11:11
-#define FORCE_AVALID (0x1<<10) //10:10
-#define FORCE_IDDIG (0x1<<9) //9:9
-#define FORCE_IDPULLUP (0x1<<8) //8:8
-#define RG_VBUSVALID (0x1<<5) //5:5
-#define RG_SESSEND (0x1<<4) //4:4
-#define RG_BVALID (0x1<<3) //3:3
-#define RG_AVALID (0x1<<2) //2:2
-#define RG_IDDIG (0x1<<1) //1:1
-#define RG_IDPULLUP (0x1<<0) //0:0
-
-//U3D_U2PHYDMON0
-#define RG_USB20_PRBS7_BERTH (0xff<<0) //7:0
-
-//U3D_U2PHYDMON1
-#define USB20_UART_O (0x1<<31) //31:31
-#define RGO_USB20_LB_PASS (0x1<<30) //30:30
-#define RGO_USB20_LB_DONE (0x1<<29) //29:29
-#define AD_USB20_BVALID (0x1<<28) //28:28
-#define USB20_IDDIG (0x1<<27) //27:27
-#define AD_USB20_VBUSVALID (0x1<<26) //26:26
-#define AD_USB20_SESSEND (0x1<<25) //25:25
-#define AD_USB20_AVALID (0x1<<24) //24:24
-#define USB20_LINE_STATE (0x3<<22) //23:22
-#define USB20_HST_DISCON (0x1<<21) //21:21
-#define USB20_TX_READY (0x1<<20) //20:20
-#define USB20_RX_ERROR (0x1<<19) //19:19
-#define USB20_RX_ACTIVE (0x1<<18) //18:18
-#define USB20_RX_VALIDH (0x1<<17) //17:17
-#define USB20_RX_VALID (0x1<<16) //16:16
-#define USB20_DATA_OUT (0xffff<<0) //15:0
-
-//U3D_U2PHYDMON2
-#define RGO_TXVALID_CNT (0xff<<24) //31:24
-#define RGO_RXACTIVE_CNT (0xff<<16) //23:16
-#define RGO_USB20_LB_BERCNT (0xff<<8) //15:8
-#define USB20_PROBE_OUT (0xff<<0) //7:0
-
-//U3D_U2PHYDMON3
-#define RGO_USB20_PRBS7_ERRCNT (0xffff<<16) //31:16
-#define RGO_USB20_PRBS7_DONE (0x1<<3) //3:3
-#define RGO_USB20_PRBS7_LOCK (0x1<<2) //2:2
-#define RGO_USB20_PRBS7_PASS (0x1<<1) //1:1
-#define RGO_USB20_PRBS7_PASSTH (0x1<<0) //0:0
-
-//U3D_U2PHYBC12C
-#define RG_SIFSLV_CHGDT_DEGLCH_CNT (0xf<<28) //31:28
-#define RG_SIFSLV_CHGDT_CTRL_CNT (0xf<<24) //27:24
-#define RG_SIFSLV_CHGDT_FORCE_MODE (0x1<<16) //16:16
-#define RG_CHGDT_ISRC_LEV (0x3<<14) //15:14
-#define RG_CHGDT_VDATSRC (0x1<<13) //13:13
-#define RG_CHGDT_BGVREF_SEL (0x7<<10) //12:10
-#define RG_CHGDT_RDVREF_SEL (0x3<<8) //9:8
-#define RG_CHGDT_ISRC_DP (0x1<<7) //7:7
-#define RG_SIFSLV_CHGDT_OPOUT_DM (0x1<<6) //6:6
-#define RG_CHGDT_VDAT_DM (0x1<<5) //5:5
-#define RG_CHGDT_OPOUT_DP (0x1<<4) //4:4
-#define RG_SIFSLV_CHGDT_VDAT_DP (0x1<<3) //3:3
-#define RG_SIFSLV_CHGDT_COMP_EN (0x1<<2) //2:2
-#define RG_SIFSLV_CHGDT_OPDRV_EN (0x1<<1) //1:1
-#define RG_CHGDT_EN (0x1<<0) //0:0
-
-//U3D_U2PHYBC12C1
-#define RG_CHGDT_REV (0xff<<0) //7:0
-
-//U3D_REGFCOM
-#define RG_PAGE (0xff<<24) //31:24
-#define I2C_MODE (0x1<<16) //16:16
-
-
-/* OFFSET */
-
-//U3D_U2PHYAC0
-#define RG_USB20_USBPLL_DIVEN_OFST (28)
-#define RG_USB20_USBPLL_CKCTRL_OFST (26)
-#define RG_USB20_USBPLL_PREDIV_OFST (24)
-#define RG_USB20_USBPLL_FORCE_ON_OFST (23)
-#define RG_USB20_USBPLL_FBDIV_OFST (16)
-#define RG_USB20_REF_EN_OFST (15)
-#define RG_USB20_INTR_EN_OFST (14)
-#define RG_USB20_BG_TRIM_OFST (8)
-#define RG_USB20_BG_RBSEL_OFST (6)
-#define RG_USB20_BG_RASEL_OFST (4)
-#define RG_USB20_BGR_DIV_OFST (2)
-#define RG_SIFSLV_CHP_EN_OFST (1)
-#define RG_SIFSLV_BGR_EN_OFST (0)
-
-//U3D_U2PHYAC1
-#define RG_USB20_VRT_VREF_SEL_OFST (28)
-#define RG_USB20_TERM_VREF_SEL_OFST (24)
-#define RG_USB20_MPX_SEL_OFST (16)
-#define RG_USB20_MPX_OUT_SEL_OFST (12)
-#define RG_USB20_TX_PH_ROT_SEL_OFST (8)
-#define RG_USB20_USBPLL_ACCEN_OFST (3)
-#define RG_USB20_USBPLL_LF_OFST (2)
-#define RG_USB20_USBPLL_BR_OFST (1)
-#define RG_USB20_USBPLL_BP_OFST (0)
-
-//U3D_U2PHYAC2
-#define RG_SIFSLV_MAC_BANDGAP_EN_OFST (17)
-#define RG_SIFSLV_MAC_CHOPPER_EN_OFST (16)
-#define RG_USB20_CLKREF_REV_OFST (0)
-
-//U3D_U2PHYACR0
-#define RG_USB20_ICUSB_EN_OFST (24)
-#define RG_USB20_HSTX_SRCAL_EN_OFST (23)
-#define RG_USB20_HSTX_SRCTRL_OFST (16)
-#define RG_USB20_LS_CR_OFST (12)
-#define RG_USB20_FS_CR_OFST (8)
-#define RG_USB20_LS_SR_OFST (4)
-#define RG_USB20_FS_SR_OFST (0)
-
-//U3D_U2PHYACR1
-#define RG_USB20_INIT_SQ_EN_DG_OFST (28)
-#define RG_USB20_SQD_OFST (24)
-#define RG_USB20_HSTX_TMODE_SEL_OFST (20)
-#define RG_USB20_HSTX_TMODE_EN_OFST (19)
-#define RG_USB20_PHYD_MONEN_OFST (18)
-#define RG_USB20_INLPBK_EN_OFST (17)
-#define RG_USB20_CHIRP_EN_OFST (16)
-#define RG_USB20_DM_ABIST_SOURCE_EN_OFST (15)
-#define RG_USB20_DM_ABIST_SELE_OFST (8)
-#define RG_USB20_DP_ABIST_SOURCE_EN_OFST (7)
-#define RG_USB20_DP_ABIST_SELE_OFST (0)
-
-//U3D_U2PHYACR2
-#define RG_USB20_OTG_ABIST_SELE_OFST (29)
-#define RG_USB20_OTG_ABIST_EN_OFST (28)
-#define RG_USB20_OTG_VBUSCMP_EN_OFST (27)
-#define RG_USB20_OTG_VBUSTH_OFST (24)
-#define RG_USB20_DISC_FIT_EN_OFST (22)
-#define RG_USB20_DISCD_OFST (20)
-#define RG_USB20_DISCTH_OFST (16)
-#define RG_USB20_SQCAL_EN_OFST (15)
-#define RG_USB20_SQCAL_OFST (8)
-#define RG_USB20_SQTH_OFST (0)
-
-//U3D_U2PHYACR3
-#define RG_USB20_HSTX_DBIST_OFST (28)
-#define RG_USB20_HSTX_BIST_EN_OFST (26)
-#define RG_USB20_HSTX_I_EN_MODE_OFST (24)
-#define RG_USB20_HSRX_TMODE_EN_OFST (23)
-#define RG_USB20_HSRX_BIAS_EN_SEL_OFST (20)
-#define RG_USB20_USB11_TMODE_EN_OFST (19)
-#define RG_USB20_TMODE_FS_LS_TX_EN_OFST (18)
-#define RG_USB20_TMODE_FS_LS_RCV_EN_OFST (17)
-#define RG_USB20_TMODE_FS_LS_MODE_OFST (16)
-#define RG_USB20_HS_TERM_EN_MODE_OFST (13)
-#define RG_USB20_PUPD_BIST_EN_OFST (12)
-#define RG_USB20_EN_PU_DM_OFST (11)
-#define RG_USB20_EN_PD_DM_OFST (10)
-#define RG_USB20_EN_PU_DP_OFST (9)
-#define RG_USB20_EN_PD_DP_OFST (8)
-#define RG_USB20_PHY_REV_OFST (0)
-
-//U3D_U2PHYACR4
-#define RG_USB20_DP_100K_MODE_OFST (18)
-#define RG_USB20_DM_100K_EN_OFST (17)
-#define USB20_DP_100K_EN_OFST (16)
-#define USB20_GPIO_DM_I_OFST (15)
-#define USB20_GPIO_DP_I_OFST (14)
-#define USB20_GPIO_DM_OE_OFST (13)
-#define USB20_GPIO_DP_OE_OFST (12)
-#define RG_USB20_GPIO_CTL_OFST (9)
-#define USB20_GPIO_MODE_OFST (8)
-#define RG_USB20_TX_BIAS_EN_OFST (5)
-#define RG_USB20_TX_VCMPDN_EN_OFST (4)
-#define RG_USB20_HS_SQ_EN_MODE_OFST (2)
-#define RG_USB20_HS_RCV_EN_MODE_OFST (0)
-
-//U3D_U2PHYAMON0
-#define RGO_USB20_GPIO_DM_O_OFST (1)
-#define RGO_USB20_GPIO_DP_O_OFST (0)
-
-//U3D_U2PHYDCR0
-#define RG_USB20_CDR_TST_OFST (30)
-#define RG_USB20_GATED_ENB_OFST (29)
-#define RG_USB20_TESTMODE_OFST (26)
-#define RG_USB20_PLL_STABLE_OFST (25)
-#define RG_USB20_PLL_FORCE_ON_OFST (24)
-#define RG_USB20_PHYD_RESERVE_OFST (8)
-#define RG_USB20_EBTHRLD_OFST (7)
-#define RG_USB20_EARLY_HSTX_I_OFST (6)
-#define RG_USB20_TX_TST_OFST (5)
-#define RG_USB20_NEGEDGE_ENB_OFST (4)
-#define RG_USB20_CDR_FILT_OFST (0)
-
-//U3D_U2PHYDCR1
-#define RG_USB20_PROBE_SEL_OFST (24)
-#define RG_USB20_DRVVBUS_OFST (23)
-#define RG_DEBUG_EN_OFST (22)
-#define RG_USB20_OTG_PROBE_OFST (20)
-#define RG_USB20_SW_PLLMODE_OFST (18)
-#define RG_USB20_BERTH_OFST (16)
-#define RG_USB20_LBMODE_OFST (13)
-#define RG_USB20_FORCE_TAP_OFST (12)
-#define RG_USB20_TAPSEL_OFST (0)
-
-//U3D_U2PHYDTM0
-#define RG_UART_MODE_OFST (30)
-#define FORCE_UART_I_OFST (29)
-#define FORCE_UART_BIAS_EN_OFST (28)
-#define FORCE_UART_TX_OE_OFST (27)
-#define FORCE_UART_EN_OFST (26)
-#define FORCE_USB_CLKEN_OFST (25)
-#define FORCE_DRVVBUS_OFST (24)
-#define FORCE_DATAIN_OFST (23)
-#define FORCE_TXVALID_OFST (22)
-#define FORCE_DM_PULLDOWN_OFST (21)
-#define FORCE_DP_PULLDOWN_OFST (20)
-#define FORCE_XCVRSEL_OFST (19)
-#define FORCE_SUSPENDM_OFST (18)
-#define FORCE_TERMSEL_OFST (17)
-#define FORCE_OPMODE_OFST (16)
-#define UTMI_MUXSEL_OFST (15)
-#define RG_RESET_OFST (14)
-#define RG_DATAIN_OFST (10)
-#define RG_TXVALIDH_OFST (9)
-#define RG_TXVALID_OFST (8)
-#define RG_DMPULLDOWN_OFST (7)
-#define RG_DPPULLDOWN_OFST (6)
-#define RG_XCVRSEL_OFST (4)
-#define RG_SUSPENDM_OFST (3)
-#define RG_TERMSEL_OFST (2)
-#define RG_OPMODE_OFST (0)
-
-//U3D_U2PHYDTM1
-#define RG_USB20_PRBS7_EN_OFST (31)
-#define RG_USB20_PRBS7_BITCNT_OFST (24)
-#define RG_USB20_CLK48M_EN_OFST (23)
-#define RG_USB20_CLK60M_EN_OFST (22)
-#define RG_UART_I_OFST (19)
-#define RG_UART_BIAS_EN_OFST (18)
-#define RG_UART_TX_OE_OFST (17)
-#define RG_UART_EN_OFST (16)
-#define FORCE_VBUSVALID_OFST (13)
-#define FORCE_SESSEND_OFST (12)
-#define FORCE_BVALID_OFST (11)
-#define FORCE_AVALID_OFST (10)
-#define FORCE_IDDIG_OFST (9)
-#define FORCE_IDPULLUP_OFST (8)
-#define RG_VBUSVALID_OFST (5)
-#define RG_SESSEND_OFST (4)
-#define RG_BVALID_OFST (3)
-#define RG_AVALID_OFST (2)
-#define RG_IDDIG_OFST (1)
-#define RG_IDPULLUP_OFST (0)
-
-//U3D_U2PHYDMON0
-#define RG_USB20_PRBS7_BERTH_OFST (0)
-
-//U3D_U2PHYDMON1
-#define USB20_UART_O_OFST (31)
-#define RGO_USB20_LB_PASS_OFST (30)
-#define RGO_USB20_LB_DONE_OFST (29)
-#define AD_USB20_BVALID_OFST (28)
-#define USB20_IDDIG_OFST (27)
-#define AD_USB20_VBUSVALID_OFST (26)
-#define AD_USB20_SESSEND_OFST (25)
-#define AD_USB20_AVALID_OFST (24)
-#define USB20_LINE_STATE_OFST (22)
-#define USB20_HST_DISCON_OFST (21)
-#define USB20_TX_READY_OFST (20)
-#define USB20_RX_ERROR_OFST (19)
-#define USB20_RX_ACTIVE_OFST (18)
-#define USB20_RX_VALIDH_OFST (17)
-#define USB20_RX_VALID_OFST (16)
-#define USB20_DATA_OUT_OFST (0)
-
-//U3D_U2PHYDMON2
-#define RGO_TXVALID_CNT_OFST (24)
-#define RGO_RXACTIVE_CNT_OFST (16)
-#define RGO_USB20_LB_BERCNT_OFST (8)
-#define USB20_PROBE_OUT_OFST (0)
-
-//U3D_U2PHYDMON3
-#define RGO_USB20_PRBS7_ERRCNT_OFST (16)
-#define RGO_USB20_PRBS7_DONE_OFST (3)
-#define RGO_USB20_PRBS7_LOCK_OFST (2)
-#define RGO_USB20_PRBS7_PASS_OFST (1)
-#define RGO_USB20_PRBS7_PASSTH_OFST (0)
-
-//U3D_U2PHYBC12C
-#define RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST (28)
-#define RG_SIFSLV_CHGDT_CTRL_CNT_OFST (24)
-#define RG_SIFSLV_CHGDT_FORCE_MODE_OFST (16)
-#define RG_CHGDT_ISRC_LEV_OFST (14)
-#define RG_CHGDT_VDATSRC_OFST (13)
-#define RG_CHGDT_BGVREF_SEL_OFST (10)
-#define RG_CHGDT_RDVREF_SEL_OFST (8)
-#define RG_CHGDT_ISRC_DP_OFST (7)
-#define RG_SIFSLV_CHGDT_OPOUT_DM_OFST (6)
-#define RG_CHGDT_VDAT_DM_OFST (5)
-#define RG_CHGDT_OPOUT_DP_OFST (4)
-#define RG_SIFSLV_CHGDT_VDAT_DP_OFST (3)
-#define RG_SIFSLV_CHGDT_COMP_EN_OFST (2)
-#define RG_SIFSLV_CHGDT_OPDRV_EN_OFST (1)
-#define RG_CHGDT_EN_OFST (0)
-
-//U3D_U2PHYBC12C1
-#define RG_CHGDT_REV_OFST (0)
-
-//U3D_REGFCOM
-#define RG_PAGE_OFST (24)
-#define I2C_MODE_OFST (16)
-
-
-///////////////////////////////////////////////////////////////////////////////
-
-struct u3phya_reg {
- //0x0
- PHY_LE32 reg0;
- PHY_LE32 reg1;
- PHY_LE32 reg2;
- PHY_LE32 reg3;
- //0x10
- PHY_LE32 reg4;
- PHY_LE32 reg5;
- PHY_LE32 reg6;
- PHY_LE32 reg7;
- //0x20
- PHY_LE32 reg8;
- PHY_LE32 reg9;
- PHY_LE32 rega;
- PHY_LE32 regb;
- //0x30
- PHY_LE32 regc;
- PHY_LE32 regd;
- PHY_LE32 rege;
-};
-
-//U3D_reg0
-#define RG_SSUSB_BGR_EN (0x1<<31) //31:31
-#define RG_SSUSB_CHPEN (0x1<<30) //30:30
-#define RG_SSUSB_BG_DIV (0x3<<28) //29:28
-#define RG_SSUSB_INTR_EN (0x1<<26) //26:26
-#define RG_SSUSB_MPX_OUT_SEL (0x3<<24) //25:24
-#define RG_SSUSB_MPX_SEL (0xff<<16) //23:16
-#define RG_SSUSB_REF_EN (0x1<<15) //15:15
-#define RG_SSUSB_VRT_VREF_SEL (0xf<<11) //14:11
-#define RG_SSUSB_BG_RASEL (0x3<<9) //10:9
-#define RG_SSUSB_BG_RBSEL (0x3<<7) //8:7
-#define RG_SSUSB_BG_MONEN (0x1<<6) //6:6
-#define RG_PCIE_CLKDRV_OFFSET (0x3<<0) //1:0
-
-//U3D_reg1
-#define RG_PCIE_CLKDRV_SLEW (0x3<<30) //31:30
-#define RG_PCIE_CLKDRV_AMP (0x7<<27) //29:27
-#define RG_SSUSB_XTAL_TST_A2DCK_EN (0x1<<26) //26:26
-#define RG_SSUSB_XTAL_MON_EN (0x1<<25) //25:25
-#define RG_SSUSB_XTAL_HYS (0x1<<24) //24:24
-#define RG_SSUSB_XTAL_TOP_RESERVE (0xffff<<8) //23:8
-#define RG_SSUSB_SYSPLL_RESERVE (0xf<<4) //7:4
-#define RG_SSUSB_SYSPLL_FBSEL (0x3<<2) //3:2
-#define RG_SSUSB_SYSPLL_PREDIV (0x3<<0) //1:0
-
-//U3D_reg2
-#define RG_SSUSB_SYSPLL_LF (0x1<<31) //31:31
-#define RG_SSUSB_SYSPLL_FBDIV (0x7f<<24) //30:24
-#define RG_SSUSB_SYSPLL_POSDIV (0x3<<22) //23:22
-#define RG_SSUSB_SYSPLL_VCO_DIV_SEL (0x1<<21) //21:21
-#define RG_SSUSB_SYSPLL_BLP (0x1<<20) //20:20
-#define RG_SSUSB_SYSPLL_BP (0x1<<19) //19:19
-#define RG_SSUSB_SYSPLL_BR (0x1<<18) //18:18
-#define RG_SSUSB_SYSPLL_BC (0x1<<17) //17:17
-#define RG_SSUSB_SYSPLL_DIVEN (0x7<<14) //16:14
-#define RG_SSUSB_SYSPLL_FPEN (0x1<<13) //13:13
-#define RG_SSUSB_SYSPLL_MONCK_EN (0x1<<12) //12:12
-#define RG_SSUSB_SYSPLL_MONVC_EN (0x1<<11) //11:11
-#define RG_SSUSB_SYSPLL_MONREF_EN (0x1<<10) //10:10
-#define RG_SSUSB_SYSPLL_VOD_EN (0x1<<9) //9:9
-#define RG_SSUSB_SYSPLL_CK_SEL (0x1<<8) //8:8
-
-//U3D_reg3
-#define RG_SSUSB_SYSPLL_TOP_RESERVE (0xffff<<16) //31:16
-
-//U3D_reg4
-#define RG_SSUSB_SYSPLL_PCW_NCPO (0x7fffffff<<1) //31:1
-
-//U3D_reg5
-#define RG_SSUSB_SYSPLL_DDS_PI_C (0x7<<29) //31:29
-#define RG_SSUSB_SYSPLL_DDS_HF_EN (0x1<<28) //28:28
-#define RG_SSUSB_SYSPLL_DDS_PREDIV2 (0x1<<27) //27:27
-#define RG_SSUSB_SYSPLL_DDS_POSTDIV2 (0x1<<26) //26:26
-#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN (0x1<<25) //25:25
-#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL (0x1<<24) //24:24
-#define RG_SSUSB_SYSPLL_DDS_MONEN (0x1<<23) //23:23
-#define RG_SSUSB_SYSPLL_DDS_LPF_EN (0x1<<22) //22:22
-#define RG_SSUSB_SYSPLL_CLK_PH_INV (0x1<<21) //21:21
-#define RG_SSUSB_SYSPLL_DDS_SEL_EXT (0x1<<20) //20:20
-#define RG_SSUSB_SYSPLL_DDS_DMY (0xffff<<0) //15:0
-
-//U3D_reg6
-#define RG_SSUSB_TX250MCK_INVB (0x1<<31) //31:31
-#define RG_SSUSB_IDRV_ITAILOP_EN (0x1<<30) //30:30
-#define RG_SSUSB_IDRV_CALIB (0x3f<<24) //29:24
-#define RG_SSUSB_TX_R50_FON (0x1<<23) //23:23
-#define RG_SSUSB_TX_SR (0x7<<20) //22:20
-#define RG_SSUSB_TX_EIDLE_CM (0xf<<16) //19:16
-#define RG_SSUSB_RXDET_RSEL (0x3<<14) //15:14
-#define RG_SSUSB_RXDET_VTHSEL (0x3<<12) //13:12
-#define RG_SSUSB_CKMON_EN (0x1<<11) //11:11
-#define RG_SSUSB_CKMON_SEL (0x7<<8) //10:8
-#define RG_SSUSB_TX_VLMON_EN (0x1<<7) //7:7
-#define RG_SSUSB_TX_VLMON_SEL (0x1<<6) //6:6
-#define RG_SSUSB_RXLBTX_EN (0x1<<5) //5:5
-#define RG_SSUSB_TXLBRX_EN (0x1<<4) //4:4
-
-//U3D_reg7
-#define RG_SSUSB_RESERVE (0xfffff<<12) //31:12
-#define RG_SSUSB_PLL_CKCTRL (0x3<<10) //11:10
-#define RG_SSUSB_PLL_POSDIV (0x3<<8) //9:8
-#define RG_SSUSB_PLL_AUTOK_LOAD (0x1<<7) //7:7
-#define RG_SSUSB_PLL_LOAD_RSTB (0x1<<6) //6:6
-#define RG_SSUSB_PLL_EP_EN (0x1<<5) //5:5
-#define RG_SSUSB_PLL_VOD_EN (0x1<<4) //4:4
-#define RG_SSUSB_PLL_V11_EN (0x1<<3) //3:3
-#define RG_SSUSB_PLL_MONREF_EN (0x1<<2) //2:2
-#define RG_SSUSB_PLL_MONCK_EN (0x1<<1) //1:1
-#define RG_SSUSB_PLL_MONVC_EN (0x1<<0) //0:0
-
-//U3D_reg8
-#define RG_SSUSB_PLL_RESERVE (0xffff<<0) //15:0
-
-//U3D_reg9
-#define RG_SSUSB_PLL_DDS_DMY (0xffff<<16) //31:16
-#define RG_SSUSB_PLL_SSC_PRD (0xffff<<0) //15:0
-
-//U3D_regA
-#define RG_SSUSB_PLL_SSC_PHASE_INI (0x1<<31) //31:31
-#define RG_SSUSB_PLL_SSC_TRI_EN (0x1<<30) //30:30
-#define RG_SSUSB_PLL_CLK_PH_INV (0x1<<29) //29:29
-#define RG_SSUSB_PLL_DDS_LPF_EN (0x1<<28) //28:28
-#define RG_SSUSB_PLL_DDS_VADJ (0x7<<21) //23:21
-#define RG_SSUSB_PLL_DDS_MONEN (0x1<<20) //20:20
-#define RG_SSUSB_PLL_DDS_PS_VADJ (0x7<<17) //19:17
-#define RG_SSUSB_PLL_DDS_SEL_EXT (0x1<<16) //16:16
-#define RG_SSUSB_CDR_PD_DIV_BYPASS (0x1<<15) //15:15
-#define RG_SSUSB_CDR_PD_DIV_SEL (0x1<<14) //14:14
-#define RG_SSUSB_CDR_CPBIAS_SEL (0x1<<13) //13:13
-#define RG_SSUSB_CDR_OSCDET_EN (0x1<<12) //12:12
-#define RG_SSUSB_CDR_MONMUX (0x1<<11) //11:11
-#define RG_SSUSB_CDR_CKCTRL (0x3<<9) //10:9
-#define RG_SSUSB_CDR_ACCEN (0x1<<8) //8:8
-#define RG_SSUSB_CDR_BYPASS (0x3<<6) //7:6
-#define RG_SSUSB_CDR_PI_SLEW (0x3<<4) //5:4
-#define RG_SSUSB_CDR_EPEN (0x1<<3) //3:3
-#define RG_SSUSB_CDR_AUTOK_LOAD (0x1<<2) //2:2
-#define RG_SSUSB_CDR_LOAD_RSTB (0x1<<1) //1:1
-#define RG_SSUSB_CDR_MONEN (0x1<<0) //0:0
-
-//U3D_regB
-#define RG_SSUSB_CDR_MONEN_DIG (0x1<<31) //31:31
-#define RG_SSUSB_CDR_REGOD (0x3<<29) //30:29
-#define RG_SSUSB_RX_DAC_EN (0x1<<26) //26:26
-#define RG_SSUSB_RX_DAC_PWD (0x1<<25) //25:25
-#define RG_SSUSB_EQ_CURSEL (0x1<<24) //24:24
-#define RG_SSUSB_RX_DAC_MUX (0x1f<<19) //23:19
-#define RG_SSUSB_RX_R2T_EN (0x1<<18) //18:18
-#define RG_SSUSB_RX_T2R_EN (0x1<<17) //17:17
-#define RG_SSUSB_RX_50_LOWER (0x7<<14) //16:14
-#define RG_SSUSB_RX_50_TAR (0x3<<12) //13:12
-#define RG_SSUSB_RX_SW_CTRL (0xf<<7) //10:7
-#define RG_PCIE_SIGDET_VTH (0x3<<5) //6:5
-#define RG_PCIE_SIGDET_LPF (0x3<<3) //4:3
-#define RG_SSUSB_LFPS_MON_EN (0x1<<2) //2:2
-
-//U3D_regC
-#define RG_SSUSB_RXAFE_DCMON_SEL (0xf<<28) //31:28
-#define RG_SSUSB_CDR_RESERVE (0xff<<16) //23:16
-#define RG_SSUSB_RXAFE_RESERVE (0xff<<8) //15:8
-#define RG_PCIE_RX_RESERVE (0xff<<0) //7:0
-
-//U3D_redD
-#define RGS_SSUSB_CDR_NO_OSC (0x1<<8) //8:8
-#define RGS_SSUSB_RX_DEBUG_RESERVE (0xff<<0) //7:0
-
-//U3D_regE
-#define RG_SSUSB_INT_BIAS_SEL (0x1<<4) //4:4
-#define RG_SSUSB_EXT_BIAS_SEL (0x1<<3) //3:3
-#define RG_SSUSB_RX_P1_ENTRY_PASS (0x1<<2) //2:2
-#define RG_SSUSB_RX_PD_RST (0x1<<1) //1:1
-#define RG_SSUSB_RX_PD_RST_PASS (0x1<<0) //0:0
-
-
-/* OFFSET */
-
-//U3D_reg0
-#define RG_SSUSB_BGR_EN_OFST (31)
-#define RG_SSUSB_CHPEN_OFST (30)
-#define RG_SSUSB_BG_DIV_OFST (28)
-#define RG_SSUSB_INTR_EN_OFST (26)
-#define RG_SSUSB_MPX_OUT_SEL_OFST (24)
-#define RG_SSUSB_MPX_SEL_OFST (16)
-#define RG_SSUSB_REF_EN_OFST (15)
-#define RG_SSUSB_VRT_VREF_SEL_OFST (11)
-#define RG_SSUSB_BG_RASEL_OFST (9)
-#define RG_SSUSB_BG_RBSEL_OFST (7)
-#define RG_SSUSB_BG_MONEN_OFST (6)
-#define RG_PCIE_CLKDRV_OFFSET_OFST (0)
-
-//U3D_reg1
-#define RG_PCIE_CLKDRV_SLEW_OFST (30)
-#define RG_PCIE_CLKDRV_AMP_OFST (27)
-#define RG_SSUSB_XTAL_TST_A2DCK_EN_OFST (26)
-#define RG_SSUSB_XTAL_MON_EN_OFST (25)
-#define RG_SSUSB_XTAL_HYS_OFST (24)
-#define RG_SSUSB_XTAL_TOP_RESERVE_OFST (8)
-#define RG_SSUSB_SYSPLL_RESERVE_OFST (4)
-#define RG_SSUSB_SYSPLL_FBSEL_OFST (2)
-#define RG_SSUSB_SYSPLL_PREDIV_OFST (0)
-
-//U3D_reg2
-#define RG_SSUSB_SYSPLL_LF_OFST (31)
-#define RG_SSUSB_SYSPLL_FBDIV_OFST (24)
-#define RG_SSUSB_SYSPLL_POSDIV_OFST (22)
-#define RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST (21)
-#define RG_SSUSB_SYSPLL_BLP_OFST (20)
-#define RG_SSUSB_SYSPLL_BP_OFST (19)
-#define RG_SSUSB_SYSPLL_BR_OFST (18)
-#define RG_SSUSB_SYSPLL_BC_OFST (17)
-#define RG_SSUSB_SYSPLL_DIVEN_OFST (14)
-#define RG_SSUSB_SYSPLL_FPEN_OFST (13)
-#define RG_SSUSB_SYSPLL_MONCK_EN_OFST (12)
-#define RG_SSUSB_SYSPLL_MONVC_EN_OFST (11)
-#define RG_SSUSB_SYSPLL_MONREF_EN_OFST (10)
-#define RG_SSUSB_SYSPLL_VOD_EN_OFST (9)
-#define RG_SSUSB_SYSPLL_CK_SEL_OFST (8)
-
-//U3D_reg3
-#define RG_SSUSB_SYSPLL_TOP_RESERVE_OFST (16)
-
-//U3D_reg4
-#define RG_SSUSB_SYSPLL_PCW_NCPO_OFST (1)
-
-//U3D_reg5
-#define RG_SSUSB_SYSPLL_DDS_PI_C_OFST (29)
-#define RG_SSUSB_SYSPLL_DDS_HF_EN_OFST (28)
-#define RG_SSUSB_SYSPLL_DDS_PREDIV2_OFST (27)
-#define RG_SSUSB_SYSPLL_DDS_POSTDIV2_OFST (26)
-#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN_OFST (25)
-#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL_OFST (24)
-#define RG_SSUSB_SYSPLL_DDS_MONEN_OFST (23)
-#define RG_SSUSB_SYSPLL_DDS_LPF_EN_OFST (22)
-#define RG_SSUSB_SYSPLL_CLK_PH_INV_OFST (21)
-#define RG_SSUSB_SYSPLL_DDS_SEL_EXT_OFST (20)
-#define RG_SSUSB_SYSPLL_DDS_DMY_OFST (0)
-
-//U3D_reg6
-#define RG_SSUSB_TX250MCK_INVB_OFST (31)
-#define RG_SSUSB_IDRV_ITAILOP_EN_OFST (30)
-#define RG_SSUSB_IDRV_CALIB_OFST (24)
-#define RG_SSUSB_TX_R50_FON_OFST (23)
-#define RG_SSUSB_TX_SR_OFST (20)
-#define RG_SSUSB_TX_EIDLE_CM_OFST (16)
-#define RG_SSUSB_RXDET_RSEL_OFST (14)
-#define RG_SSUSB_RXDET_VTHSEL_OFST (12)
-#define RG_SSUSB_CKMON_EN_OFST (11)
-#define RG_SSUSB_CKMON_SEL_OFST (8)
-#define RG_SSUSB_TX_VLMON_EN_OFST (7)
-#define RG_SSUSB_TX_VLMON_SEL_OFST (6)
-#define RG_SSUSB_RXLBTX_EN_OFST (5)
-#define RG_SSUSB_TXLBRX_EN_OFST (4)
-
-//U3D_reg7
-#define RG_SSUSB_RESERVE_OFST (12)
-#define RG_SSUSB_PLL_CKCTRL_OFST (10)
-#define RG_SSUSB_PLL_POSDIV_OFST (8)
-#define RG_SSUSB_PLL_AUTOK_LOAD_OFST (7)
-#define RG_SSUSB_PLL_LOAD_RSTB_OFST (6)
-#define RG_SSUSB_PLL_EP_EN_OFST (5)
-#define RG_SSUSB_PLL_VOD_EN_OFST (4)
-#define RG_SSUSB_PLL_V11_EN_OFST (3)
-#define RG_SSUSB_PLL_MONREF_EN_OFST (2)
-#define RG_SSUSB_PLL_MONCK_EN_OFST (1)
-#define RG_SSUSB_PLL_MONVC_EN_OFST (0)
-
-//U3D_reg8
-#define RG_SSUSB_PLL_RESERVE_OFST (0)
-
-//U3D_reg9
-#define RG_SSUSB_PLL_DDS_DMY_OFST (16)
-#define RG_SSUSB_PLL_SSC_PRD_OFST (0)
-
-//U3D_regA
-#define RG_SSUSB_PLL_SSC_PHASE_INI_OFST (31)
-#define RG_SSUSB_PLL_SSC_TRI_EN_OFST (30)
-#define RG_SSUSB_PLL_CLK_PH_INV_OFST (29)
-#define RG_SSUSB_PLL_DDS_LPF_EN_OFST (28)
-#define RG_SSUSB_PLL_DDS_VADJ_OFST (21)
-#define RG_SSUSB_PLL_DDS_MONEN_OFST (20)
-#define RG_SSUSB_PLL_DDS_PS_VADJ_OFST (17)
-#define RG_SSUSB_PLL_DDS_SEL_EXT_OFST (16)
-#define RG_SSUSB_CDR_PD_DIV_BYPASS_OFST (15)
-#define RG_SSUSB_CDR_PD_DIV_SEL_OFST (14)
-#define RG_SSUSB_CDR_CPBIAS_SEL_OFST (13)
-#define RG_SSUSB_CDR_OSCDET_EN_OFST (12)
-#define RG_SSUSB_CDR_MONMUX_OFST (11)
-#define RG_SSUSB_CDR_CKCTRL_OFST (9)
-#define RG_SSUSB_CDR_ACCEN_OFST (8)
-#define RG_SSUSB_CDR_BYPASS_OFST (6)
-#define RG_SSUSB_CDR_PI_SLEW_OFST (4)
-#define RG_SSUSB_CDR_EPEN_OFST (3)
-#define RG_SSUSB_CDR_AUTOK_LOAD_OFST (2)
-#define RG_SSUSB_CDR_LOAD_RSTB_OFST (1)
-#define RG_SSUSB_CDR_MONEN_OFST (0)
-
-//U3D_regB
-#define RG_SSUSB_CDR_MONEN_DIG_OFST (31)
-#define RG_SSUSB_CDR_REGOD_OFST (29)
-#define RG_SSUSB_RX_DAC_EN_OFST (26)
-#define RG_SSUSB_RX_DAC_PWD_OFST (25)
-#define RG_SSUSB_EQ_CURSEL_OFST (24)
-#define RG_SSUSB_RX_DAC_MUX_OFST (19)
-#define RG_SSUSB_RX_R2T_EN_OFST (18)
-#define RG_SSUSB_RX_T2R_EN_OFST (17)
-#define RG_SSUSB_RX_50_LOWER_OFST (14)
-#define RG_SSUSB_RX_50_TAR_OFST (12)
-#define RG_SSUSB_RX_SW_CTRL_OFST (7)
-#define RG_PCIE_SIGDET_VTH_OFST (5)
-#define RG_PCIE_SIGDET_LPF_OFST (3)
-#define RG_SSUSB_LFPS_MON_EN_OFST (2)
-
-//U3D_regC
-#define RG_SSUSB_RXAFE_DCMON_SEL_OFST (28)
-#define RG_SSUSB_CDR_RESERVE_OFST (16)
-#define RG_SSUSB_RXAFE_RESERVE_OFST (8)
-#define RG_PCIE_RX_RESERVE_OFST (0)
-
-//U3D_redD
-#define RGS_SSUSB_CDR_NO_OSC_OFST (8)
-#define RGS_SSUSB_RX_DEBUG_RESERVE_OFST (0)
-
-//U3D_regE
-#define RG_SSUSB_INT_BIAS_SEL_OFST (4)
-#define RG_SSUSB_EXT_BIAS_SEL_OFST (3)
-#define RG_SSUSB_RX_P1_ENTRY_PASS_OFST (2)
-#define RG_SSUSB_RX_PD_RST_OFST (1)
-#define RG_SSUSB_RX_PD_RST_PASS_OFST (0)
-
-///////////////////////////////////////////////////////////////////////////////
-
-struct u3phya_da_reg {
- //0x0
- PHY_LE32 reg0;
- PHY_LE32 reg1;
- PHY_LE32 reg4;
- PHY_LE32 reg5;
- //0x10
- PHY_LE32 reg6;
- PHY_LE32 reg7;
- PHY_LE32 reg8;
- PHY_LE32 reg9;
- //0x20
- PHY_LE32 reg10;
- PHY_LE32 reg12;
- PHY_LE32 reg13;
- PHY_LE32 reg14;
- //0x30
- PHY_LE32 reg15;
- PHY_LE32 reg16;
- PHY_LE32 reg19;
- PHY_LE32 reg20;
- //0x40
- PHY_LE32 reg21;
- PHY_LE32 reg23;
- PHY_LE32 reg25;
- PHY_LE32 reg26;
- //0x50
- PHY_LE32 reg28;
- PHY_LE32 reg29;
- PHY_LE32 reg30;
- PHY_LE32 reg31;
- //0x60
- PHY_LE32 reg32;
- PHY_LE32 reg33;
-};
-
-//U3D_reg0
-#define RG_PCIE_SPEED_PE2D (0x1<<24) //24:24
-#define RG_PCIE_SPEED_PE2H (0x1<<23) //23:23
-#define RG_PCIE_SPEED_PE1D (0x1<<22) //22:22
-#define RG_PCIE_SPEED_PE1H (0x1<<21) //21:21
-#define RG_PCIE_SPEED_U3 (0x1<<20) //20:20
-#define RG_SSUSB_XTAL_EXT_EN_PE2D (0x3<<18) //19:18
-#define RG_SSUSB_XTAL_EXT_EN_PE2H (0x3<<16) //17:16
-#define RG_SSUSB_XTAL_EXT_EN_PE1D (0x3<<14) //15:14
-#define RG_SSUSB_XTAL_EXT_EN_PE1H (0x3<<12) //13:12
-#define RG_SSUSB_XTAL_EXT_EN_U3 (0x3<<10) //11:10
-#define RG_SSUSB_CDR_REFCK_SEL_PE2D (0x3<<8) //9:8
-#define RG_SSUSB_CDR_REFCK_SEL_PE2H (0x3<<6) //7:6
-#define RG_SSUSB_CDR_REFCK_SEL_PE1D (0x3<<4) //5:4
-#define RG_SSUSB_CDR_REFCK_SEL_PE1H (0x3<<2) //3:2
-#define RG_SSUSB_CDR_REFCK_SEL_U3 (0x3<<0) //1:0
-
-//U3D_reg1
-#define RG_USB20_REFCK_SEL_PE2D (0x1<<30) //30:30
-#define RG_USB20_REFCK_SEL_PE2H (0x1<<29) //29:29
-#define RG_USB20_REFCK_SEL_PE1D (0x1<<28) //28:28
-#define RG_USB20_REFCK_SEL_PE1H (0x1<<27) //27:27
-#define RG_USB20_REFCK_SEL_U3 (0x1<<26) //26:26
-#define RG_PCIE_REFCK_DIV4_PE2D (0x1<<25) //25:25
-#define RG_PCIE_REFCK_DIV4_PE2H (0x1<<24) //24:24
-#define RG_PCIE_REFCK_DIV4_PE1D (0x1<<18) //18:18
-#define RG_PCIE_REFCK_DIV4_PE1H (0x1<<17) //17:17
-#define RG_PCIE_REFCK_DIV4_U3 (0x1<<16) //16:16
-#define RG_PCIE_MODE_PE2D (0x1<<8) //8:8
-#define RG_PCIE_MODE_PE2H (0x1<<3) //3:3
-#define RG_PCIE_MODE_PE1D (0x1<<2) //2:2
-#define RG_PCIE_MODE_PE1H (0x1<<1) //1:1
-#define RG_PCIE_MODE_U3 (0x1<<0) //0:0
-
-//U3D_reg4
-#define RG_SSUSB_PLL_DIVEN_PE2D (0x7<<22) //24:22
-#define RG_SSUSB_PLL_DIVEN_PE2H (0x7<<19) //21:19
-#define RG_SSUSB_PLL_DIVEN_PE1D (0x7<<16) //18:16
-#define RG_SSUSB_PLL_DIVEN_PE1H (0x7<<13) //15:13
-#define RG_SSUSB_PLL_DIVEN_U3 (0x7<<10) //12:10
-#define RG_SSUSB_PLL_BC_PE2D (0x3<<8) //9:8
-#define RG_SSUSB_PLL_BC_PE2H (0x3<<6) //7:6
-#define RG_SSUSB_PLL_BC_PE1D (0x3<<4) //5:4
-#define RG_SSUSB_PLL_BC_PE1H (0x3<<2) //3:2
-#define RG_SSUSB_PLL_BC_U3 (0x3<<0) //1:0
-
-//U3D_reg5
-#define RG_SSUSB_PLL_BR_PE2D (0x7<<27) //29:27
-#define RG_SSUSB_PLL_BR_PE2H (0x7<<24) //26:24
-#define RG_SSUSB_PLL_BR_PE1D (0x7<<21) //23:21
-#define RG_SSUSB_PLL_BR_PE1H (0x7<<18) //20:18
-#define RG_SSUSB_PLL_BR_U3 (0x7<<15) //17:15
-#define RG_SSUSB_PLL_IC_PE2D (0x7<<12) //14:12
-#define RG_SSUSB_PLL_IC_PE2H (0x7<<9) //11:9
-#define RG_SSUSB_PLL_IC_PE1D (0x7<<6) //8:6
-#define RG_SSUSB_PLL_IC_PE1H (0x7<<3) //5:3
-#define RG_SSUSB_PLL_IC_U3 (0x7<<0) //2:0
-
-//U3D_reg6
-#define RG_SSUSB_PLL_IR_PE2D (0xf<<24) //27:24
-#define RG_SSUSB_PLL_IR_PE2H (0xf<<16) //19:16
-#define RG_SSUSB_PLL_IR_PE1D (0xf<<8) //11:8
-#define RG_SSUSB_PLL_IR_PE1H (0xf<<4) //7:4
-#define RG_SSUSB_PLL_IR_U3 (0xf<<0) //3:0
-
-//U3D_reg7
-#define RG_SSUSB_PLL_BP_PE2D (0xf<<24) //27:24
-#define RG_SSUSB_PLL_BP_PE2H (0xf<<16) //19:16
-#define RG_SSUSB_PLL_BP_PE1D (0xf<<8) //11:8
-#define RG_SSUSB_PLL_BP_PE1H (0xf<<4) //7:4
-#define RG_SSUSB_PLL_BP_U3 (0xf<<0) //3:0
-
-//U3D_reg8
-#define RG_SSUSB_PLL_FBKSEL_PE2D (0x3<<24) //25:24
-#define RG_SSUSB_PLL_FBKSEL_PE2H (0x3<<16) //17:16
-#define RG_SSUSB_PLL_FBKSEL_PE1D (0x3<<8) //9:8
-#define RG_SSUSB_PLL_FBKSEL_PE1H (0x3<<2) //3:2
-#define RG_SSUSB_PLL_FBKSEL_U3 (0x3<<0) //1:0
-
-//U3D_reg9
-#define RG_SSUSB_PLL_FBKDIV_PE2H (0x7f<<24) //30:24
-#define RG_SSUSB_PLL_FBKDIV_PE1D (0x7f<<16) //22:16
-#define RG_SSUSB_PLL_FBKDIV_PE1H (0x7f<<8) //14:8
-#define RG_SSUSB_PLL_FBKDIV_U3 (0x7f<<0) //6:0
-
-//U3D_reg10
-#define RG_SSUSB_PLL_PREDIV_PE2D (0x3<<26) //27:26
-#define RG_SSUSB_PLL_PREDIV_PE2H (0x3<<24) //25:24
-#define RG_SSUSB_PLL_PREDIV_PE1D (0x3<<18) //19:18
-#define RG_SSUSB_PLL_PREDIV_PE1H (0x3<<16) //17:16
-#define RG_SSUSB_PLL_PREDIV_U3 (0x3<<8) //9:8
-#define RG_SSUSB_PLL_FBKDIV_PE2D (0x7f<<0) //6:0
-
-//U3D_reg12
-#define RG_SSUSB_PLL_PCW_NCPO_U3 (0x7fffffff<<0) //30:0
-
-//U3D_reg13
-#define RG_SSUSB_PLL_PCW_NCPO_PE1H (0x7fffffff<<0) //30:0
-
-//U3D_reg14
-#define RG_SSUSB_PLL_PCW_NCPO_PE1D (0x7fffffff<<0) //30:0
-
-//U3D_reg15
-#define RG_SSUSB_PLL_PCW_NCPO_PE2H (0x7fffffff<<0) //30:0
-
-//U3D_reg16
-#define RG_SSUSB_PLL_PCW_NCPO_PE2D (0x7fffffff<<0) //30:0
-
-//U3D_reg19
-#define RG_SSUSB_PLL_SSC_DELTA1_PE1H (0xffff<<16) //31:16
-#define RG_SSUSB_PLL_SSC_DELTA1_U3 (0xffff<<0) //15:0
-
-//U3D_reg20
-#define RG_SSUSB_PLL_SSC_DELTA1_PE2H (0xffff<<16) //31:16
-#define RG_SSUSB_PLL_SSC_DELTA1_PE1D (0xffff<<0) //15:0
-
-//U3D_reg21
-#define RG_SSUSB_PLL_SSC_DELTA_U3 (0xffff<<16) //31:16
-#define RG_SSUSB_PLL_SSC_DELTA1_PE2D (0xffff<<0) //15:0
-
-//U3D_reg23
-#define RG_SSUSB_PLL_SSC_DELTA_PE1D (0xffff<<16) //31:16
-#define RG_SSUSB_PLL_SSC_DELTA_PE1H (0xffff<<0) //15:0
-
-//U3D_reg25
-#define RG_SSUSB_PLL_SSC_DELTA_PE2D (0xffff<<16) //31:16
-#define RG_SSUSB_PLL_SSC_DELTA_PE2H (0xffff<<0) //15:0
-
-//U3D_reg26
-#define RG_SSUSB_PLL_REFCKDIV_PE2D (0x1<<25) //25:25
-#define RG_SSUSB_PLL_REFCKDIV_PE2H (0x1<<24) //24:24
-#define RG_SSUSB_PLL_REFCKDIV_PE1D (0x1<<16) //16:16
-#define RG_SSUSB_PLL_REFCKDIV_PE1H (0x1<<8) //8:8
-#define RG_SSUSB_PLL_REFCKDIV_U3 (0x1<<0) //0:0
-
-//U3D_reg28
-#define RG_SSUSB_CDR_BPA_PE2D (0x3<<24) //25:24
-#define RG_SSUSB_CDR_BPA_PE2H (0x3<<16) //17:16
-#define RG_SSUSB_CDR_BPA_PE1D (0x3<<10) //11:10
-#define RG_SSUSB_CDR_BPA_PE1H (0x3<<8) //9:8
-#define RG_SSUSB_CDR_BPA_U3 (0x3<<0) //1:0
-
-//U3D_reg29
-#define RG_SSUSB_CDR_BPB_PE2D (0x7<<24) //26:24
-#define RG_SSUSB_CDR_BPB_PE2H (0x7<<16) //18:16
-#define RG_SSUSB_CDR_BPB_PE1D (0x7<<6) //8:6
-#define RG_SSUSB_CDR_BPB_PE1H (0x7<<3) //5:3
-#define RG_SSUSB_CDR_BPB_U3 (0x7<<0) //2:0
-
-//U3D_reg30
-#define RG_SSUSB_CDR_BR_PE2D (0x7<<24) //26:24
-#define RG_SSUSB_CDR_BR_PE2H (0x7<<16) //18:16
-#define RG_SSUSB_CDR_BR_PE1D (0x7<<6) //8:6
-#define RG_SSUSB_CDR_BR_PE1H (0x7<<3) //5:3
-#define RG_SSUSB_CDR_BR_U3 (0x7<<0) //2:0
-
-//U3D_reg31
-#define RG_SSUSB_CDR_FBDIV_PE2H (0x7f<<24) //30:24
-#define RG_SSUSB_CDR_FBDIV_PE1D (0x7f<<16) //22:16
-#define RG_SSUSB_CDR_FBDIV_PE1H (0x7f<<8) //14:8
-#define RG_SSUSB_CDR_FBDIV_U3 (0x7f<<0) //6:0
-
-//U3D_reg32
-#define RG_SSUSB_EQ_RSTEP1_PE2D (0x3<<30) //31:30
-#define RG_SSUSB_EQ_RSTEP1_PE2H (0x3<<28) //29:28
-#define RG_SSUSB_EQ_RSTEP1_PE1D (0x3<<26) //27:26
-#define RG_SSUSB_EQ_RSTEP1_PE1H (0x3<<24) //25:24
-#define RG_SSUSB_EQ_RSTEP1_U3 (0x3<<22) //23:22
-#define RG_SSUSB_LFPS_DEGLITCH_PE2D (0x3<<20) //21:20
-#define RG_SSUSB_LFPS_DEGLITCH_PE2H (0x3<<18) //19:18
-#define RG_SSUSB_LFPS_DEGLITCH_PE1D (0x3<<16) //17:16
-#define RG_SSUSB_LFPS_DEGLITCH_PE1H (0x3<<14) //15:14
-#define RG_SSUSB_LFPS_DEGLITCH_U3 (0x3<<12) //13:12
-#define RG_SSUSB_CDR_KVSEL_PE2D (0x1<<11) //11:11
-#define RG_SSUSB_CDR_KVSEL_PE2H (0x1<<10) //10:10
-#define RG_SSUSB_CDR_KVSEL_PE1D (0x1<<9) //9:9
-#define RG_SSUSB_CDR_KVSEL_PE1H (0x1<<8) //8:8
-#define RG_SSUSB_CDR_KVSEL_U3 (0x1<<7) //7:7
-#define RG_SSUSB_CDR_FBDIV_PE2D (0x7f<<0) //6:0
-
-//U3D_reg33
-#define RG_SSUSB_RX_CMPWD_PE2D (0x1<<26) //26:26
-#define RG_SSUSB_RX_CMPWD_PE2H (0x1<<25) //25:25
-#define RG_SSUSB_RX_CMPWD_PE1D (0x1<<24) //24:24
-#define RG_SSUSB_RX_CMPWD_PE1H (0x1<<23) //23:23
-#define RG_SSUSB_RX_CMPWD_U3 (0x1<<16) //16:16
-#define RG_SSUSB_EQ_RSTEP2_PE2D (0x3<<8) //9:8
-#define RG_SSUSB_EQ_RSTEP2_PE2H (0x3<<6) //7:6
-#define RG_SSUSB_EQ_RSTEP2_PE1D (0x3<<4) //5:4
-#define RG_SSUSB_EQ_RSTEP2_PE1H (0x3<<2) //3:2
-#define RG_SSUSB_EQ_RSTEP2_U3 (0x3<<0) //1:0
-
-
-/* OFFSET */
-
-//U3D_reg0
-#define RG_PCIE_SPEED_PE2D_OFST (24)
-#define RG_PCIE_SPEED_PE2H_OFST (23)
-#define RG_PCIE_SPEED_PE1D_OFST (22)
-#define RG_PCIE_SPEED_PE1H_OFST (21)
-#define RG_PCIE_SPEED_U3_OFST (20)
-#define RG_SSUSB_XTAL_EXT_EN_PE2D_OFST (18)
-#define RG_SSUSB_XTAL_EXT_EN_PE2H_OFST (16)
-#define RG_SSUSB_XTAL_EXT_EN_PE1D_OFST (14)
-#define RG_SSUSB_XTAL_EXT_EN_PE1H_OFST (12)
-#define RG_SSUSB_XTAL_EXT_EN_U3_OFST (10)
-#define RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST (8)
-#define RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST (6)
-#define RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST (4)
-#define RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST (2)
-#define RG_SSUSB_CDR_REFCK_SEL_U3_OFST (0)
-
-//U3D_reg1
-#define RG_USB20_REFCK_SEL_PE2D_OFST (30)
-#define RG_USB20_REFCK_SEL_PE2H_OFST (29)
-#define RG_USB20_REFCK_SEL_PE1D_OFST (28)
-#define RG_USB20_REFCK_SEL_PE1H_OFST (27)
-#define RG_USB20_REFCK_SEL_U3_OFST (26)
-#define RG_PCIE_REFCK_DIV4_PE2D_OFST (25)
-#define RG_PCIE_REFCK_DIV4_PE2H_OFST (24)
-#define RG_PCIE_REFCK_DIV4_PE1D_OFST (18)
-#define RG_PCIE_REFCK_DIV4_PE1H_OFST (17)
-#define RG_PCIE_REFCK_DIV4_U3_OFST (16)
-#define RG_PCIE_MODE_PE2D_OFST (8)
-#define RG_PCIE_MODE_PE2H_OFST (3)
-#define RG_PCIE_MODE_PE1D_OFST (2)
-#define RG_PCIE_MODE_PE1H_OFST (1)
-#define RG_PCIE_MODE_U3_OFST (0)
-
-//U3D_reg4
-#define RG_SSUSB_PLL_DIVEN_PE2D_OFST (22)
-#define RG_SSUSB_PLL_DIVEN_PE2H_OFST (19)
-#define RG_SSUSB_PLL_DIVEN_PE1D_OFST (16)
-#define RG_SSUSB_PLL_DIVEN_PE1H_OFST (13)
-#define RG_SSUSB_PLL_DIVEN_U3_OFST (10)
-#define RG_SSUSB_PLL_BC_PE2D_OFST (8)
-#define RG_SSUSB_PLL_BC_PE2H_OFST (6)
-#define RG_SSUSB_PLL_BC_PE1D_OFST (4)
-#define RG_SSUSB_PLL_BC_PE1H_OFST (2)
-#define RG_SSUSB_PLL_BC_U3_OFST (0)
-
-//U3D_reg5
-#define RG_SSUSB_PLL_BR_PE2D_OFST (27)
-#define RG_SSUSB_PLL_BR_PE2H_OFST (24)
-#define RG_SSUSB_PLL_BR_PE1D_OFST (21)
-#define RG_SSUSB_PLL_BR_PE1H_OFST (18)
-#define RG_SSUSB_PLL_BR_U3_OFST (15)
-#define RG_SSUSB_PLL_IC_PE2D_OFST (12)
-#define RG_SSUSB_PLL_IC_PE2H_OFST (9)
-#define RG_SSUSB_PLL_IC_PE1D_OFST (6)
-#define RG_SSUSB_PLL_IC_PE1H_OFST (3)
-#define RG_SSUSB_PLL_IC_U3_OFST (0)
-
-//U3D_reg6
-#define RG_SSUSB_PLL_IR_PE2D_OFST (24)
-#define RG_SSUSB_PLL_IR_PE2H_OFST (16)
-#define RG_SSUSB_PLL_IR_PE1D_OFST (8)
-#define RG_SSUSB_PLL_IR_PE1H_OFST (4)
-#define RG_SSUSB_PLL_IR_U3_OFST (0)
-
-//U3D_reg7
-#define RG_SSUSB_PLL_BP_PE2D_OFST (24)
-#define RG_SSUSB_PLL_BP_PE2H_OFST (16)
-#define RG_SSUSB_PLL_BP_PE1D_OFST (8)
-#define RG_SSUSB_PLL_BP_PE1H_OFST (4)
-#define RG_SSUSB_PLL_BP_U3_OFST (0)
-
-//U3D_reg8
-#define RG_SSUSB_PLL_FBKSEL_PE2D_OFST (24)
-#define RG_SSUSB_PLL_FBKSEL_PE2H_OFST (16)
-#define RG_SSUSB_PLL_FBKSEL_PE1D_OFST (8)
-#define RG_SSUSB_PLL_FBKSEL_PE1H_OFST (2)
-#define RG_SSUSB_PLL_FBKSEL_U3_OFST (0)
-
-//U3D_reg9
-#define RG_SSUSB_PLL_FBKDIV_PE2H_OFST (24)
-#define RG_SSUSB_PLL_FBKDIV_PE1D_OFST (16)
-#define RG_SSUSB_PLL_FBKDIV_PE1H_OFST (8)
-#define RG_SSUSB_PLL_FBKDIV_U3_OFST (0)
-
-//U3D_reg10
-#define RG_SSUSB_PLL_PREDIV_PE2D_OFST (26)
-#define RG_SSUSB_PLL_PREDIV_PE2H_OFST (24)
-#define RG_SSUSB_PLL_PREDIV_PE1D_OFST (18)
-#define RG_SSUSB_PLL_PREDIV_PE1H_OFST (16)
-#define RG_SSUSB_PLL_PREDIV_U3_OFST (8)
-#define RG_SSUSB_PLL_FBKDIV_PE2D_OFST (0)
-
-//U3D_reg12
-#define RG_SSUSB_PLL_PCW_NCPO_U3_OFST (0)
-
-//U3D_reg13
-#define RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST (0)
-
-//U3D_reg14
-#define RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST (0)
-
-//U3D_reg15
-#define RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST (0)
-
-//U3D_reg16
-#define RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST (0)
-
-//U3D_reg19
-#define RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST (16)
-#define RG_SSUSB_PLL_SSC_DELTA1_U3_OFST (0)
-
-//U3D_reg20
-#define RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST (16)
-#define RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST (0)
-
-//U3D_reg21
-#define RG_SSUSB_PLL_SSC_DELTA_U3_OFST (16)
-#define RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST (0)
-
-//U3D_reg23
-#define RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST (16)
-#define RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST (0)
-
-//U3D_reg25
-#define RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST (16)
-#define RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST (0)
-
-//U3D_reg26
-#define RG_SSUSB_PLL_REFCKDIV_PE2D_OFST (25)
-#define RG_SSUSB_PLL_REFCKDIV_PE2H_OFST (24)
-#define RG_SSUSB_PLL_REFCKDIV_PE1D_OFST (16)
-#define RG_SSUSB_PLL_REFCKDIV_PE1H_OFST (8)
-#define RG_SSUSB_PLL_REFCKDIV_U3_OFST (0)
-
-//U3D_reg28
-#define RG_SSUSB_CDR_BPA_PE2D_OFST (24)
-#define RG_SSUSB_CDR_BPA_PE2H_OFST (16)
-#define RG_SSUSB_CDR_BPA_PE1D_OFST (10)
-#define RG_SSUSB_CDR_BPA_PE1H_OFST (8)
-#define RG_SSUSB_CDR_BPA_U3_OFST (0)
-
-//U3D_reg29
-#define RG_SSUSB_CDR_BPB_PE2D_OFST (24)
-#define RG_SSUSB_CDR_BPB_PE2H_OFST (16)
-#define RG_SSUSB_CDR_BPB_PE1D_OFST (6)
-#define RG_SSUSB_CDR_BPB_PE1H_OFST (3)
-#define RG_SSUSB_CDR_BPB_U3_OFST (0)
-
-//U3D_reg30
-#define RG_SSUSB_CDR_BR_PE2D_OFST (24)
-#define RG_SSUSB_CDR_BR_PE2H_OFST (16)
-#define RG_SSUSB_CDR_BR_PE1D_OFST (6)
-#define RG_SSUSB_CDR_BR_PE1H_OFST (3)
-#define RG_SSUSB_CDR_BR_U3_OFST (0)
-
-//U3D_reg31
-#define RG_SSUSB_CDR_FBDIV_PE2H_OFST (24)
-#define RG_SSUSB_CDR_FBDIV_PE1D_OFST (16)
-#define RG_SSUSB_CDR_FBDIV_PE1H_OFST (8)
-#define RG_SSUSB_CDR_FBDIV_U3_OFST (0)
-
-//U3D_reg32
-#define RG_SSUSB_EQ_RSTEP1_PE2D_OFST (30)
-#define RG_SSUSB_EQ_RSTEP1_PE2H_OFST (28)
-#define RG_SSUSB_EQ_RSTEP1_PE1D_OFST (26)
-#define RG_SSUSB_EQ_RSTEP1_PE1H_OFST (24)
-#define RG_SSUSB_EQ_RSTEP1_U3_OFST (22)
-#define RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST (20)
-#define RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST (18)
-#define RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST (16)
-#define RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST (14)
-#define RG_SSUSB_LFPS_DEGLITCH_U3_OFST (12)
-#define RG_SSUSB_CDR_KVSEL_PE2D_OFST (11)
-#define RG_SSUSB_CDR_KVSEL_PE2H_OFST (10)
-#define RG_SSUSB_CDR_KVSEL_PE1D_OFST (9)
-#define RG_SSUSB_CDR_KVSEL_PE1H_OFST (8)
-#define RG_SSUSB_CDR_KVSEL_U3_OFST (7)
-#define RG_SSUSB_CDR_FBDIV_PE2D_OFST (0)
-
-//U3D_reg33
-#define RG_SSUSB_RX_CMPWD_PE2D_OFST (26)
-#define RG_SSUSB_RX_CMPWD_PE2H_OFST (25)
-#define RG_SSUSB_RX_CMPWD_PE1D_OFST (24)
-#define RG_SSUSB_RX_CMPWD_PE1H_OFST (23)
-#define RG_SSUSB_RX_CMPWD_U3_OFST (16)
-#define RG_SSUSB_EQ_RSTEP2_PE2D_OFST (8)
-#define RG_SSUSB_EQ_RSTEP2_PE2H_OFST (6)
-#define RG_SSUSB_EQ_RSTEP2_PE1D_OFST (4)
-#define RG_SSUSB_EQ_RSTEP2_PE1H_OFST (2)
-#define RG_SSUSB_EQ_RSTEP2_U3_OFST (0)
-
-
-///////////////////////////////////////////////////////////////////////////////
-
-struct u3phyd_reg {
- //0x0
- PHY_LE32 phyd_mix0;
- PHY_LE32 phyd_mix1;
- PHY_LE32 phyd_lfps0;
- PHY_LE32 phyd_lfps1;
- //0x10
- PHY_LE32 phyd_impcal0;
- PHY_LE32 phyd_impcal1;
- PHY_LE32 phyd_txpll0;
- PHY_LE32 phyd_txpll1;
- //0x20
- PHY_LE32 phyd_txpll2;
- PHY_LE32 phyd_fl0;
- PHY_LE32 phyd_mix2;
- PHY_LE32 phyd_rx0;
- //0x30
- PHY_LE32 phyd_t2rlb;
- PHY_LE32 phyd_cppat;
- PHY_LE32 phyd_mix3;
- PHY_LE32 phyd_ebufctl;
- //0x40
- PHY_LE32 phyd_pipe0;
- PHY_LE32 phyd_pipe1;
- PHY_LE32 phyd_mix4;
- PHY_LE32 phyd_ckgen0;
- //0x50
- PHY_LE32 phyd_mix5;
- PHY_LE32 phyd_reserved;
- PHY_LE32 phyd_cdr0;
- PHY_LE32 phyd_cdr1;
- //0x60
- PHY_LE32 phyd_pll_0;
- PHY_LE32 phyd_pll_1;
- PHY_LE32 phyd_bcn_det_1;
- PHY_LE32 phyd_bcn_det_2;
- //0x70
- PHY_LE32 eq0;
- PHY_LE32 eq1;
- PHY_LE32 eq2;
- PHY_LE32 eq3;
- //0x80
- PHY_LE32 eq_eye0;
- PHY_LE32 eq_eye1;
- PHY_LE32 eq_eye2;
- PHY_LE32 eq_dfe0;
- //0x90
- PHY_LE32 eq_dfe1;
- PHY_LE32 eq_dfe2;
- PHY_LE32 eq_dfe3;
- PHY_LE32 reserve0;
- //0xa0
- PHY_LE32 phyd_mon0;
- PHY_LE32 phyd_mon1;
- PHY_LE32 phyd_mon2;
- PHY_LE32 phyd_mon3;
- //0xb0
- PHY_LE32 phyd_mon4;
- PHY_LE32 phyd_mon5;
- PHY_LE32 phyd_mon6;
- PHY_LE32 phyd_mon7;
- //0xc0
- PHY_LE32 phya_rx_mon0;
- PHY_LE32 phya_rx_mon1;
- PHY_LE32 phya_rx_mon2;
- PHY_LE32 phya_rx_mon3;
- //0xd0
- PHY_LE32 phya_rx_mon4;
- PHY_LE32 phya_rx_mon5;
- PHY_LE32 phyd_cppat2;
- PHY_LE32 eq_eye3;
- //0xe0
- PHY_LE32 kband_out;
- PHY_LE32 kband_out1;
-};
-
-//U3D_PHYD_MIX0
-#define RG_SSUSB_P_P3_TX_NG (0x1<<31) //31:31
-#define RG_SSUSB_TSEQ_EN (0x1<<30) //30:30
-#define RG_SSUSB_TSEQ_POLEN (0x1<<29) //29:29
-#define RG_SSUSB_TSEQ_POL (0x1<<28) //28:28
-#define RG_SSUSB_P_P3_PCLK_NG (0x1<<27) //27:27
-#define RG_SSUSB_TSEQ_TH (0x7<<24) //26:24
-#define RG_SSUSB_PRBS_BERTH (0xff<<16) //23:16
-#define RG_SSUSB_DISABLE_PHY_U2_ON (0x1<<15) //15:15
-#define RG_SSUSB_DISABLE_PHY_U2_OFF (0x1<<14) //14:14
-#define RG_SSUSB_PRBS_EN (0x1<<13) //13:13
-#define RG_SSUSB_BPSLOCK (0x1<<12) //12:12
-#define RG_SSUSB_RTCOMCNT (0xf<<8) //11:8
-#define RG_SSUSB_COMCNT (0xf<<4) //7:4
-#define RG_SSUSB_PRBSEL_CALIB (0xf<<0) //3:0
-
-//U3D_PHYD_MIX1
-#define RG_SSUSB_SLEEP_EN (0x1<<31) //31:31
-#define RG_SSUSB_PRBSEL_PCS (0x7<<28) //30:28
-#define RG_SSUSB_TXLFPS_PRD (0xf<<24) //27:24
-#define RG_SSUSB_P_RX_P0S_CK (0x1<<23) //23:23
-#define RG_SSUSB_P_TX_P0S_CK (0x1<<22) //22:22
-#define RG_SSUSB_PDNCTL (0x3f<<16) //21:16
-#define RG_SSUSB_TX_DRV_EN (0x1<<15) //15:15
-#define RG_SSUSB_TX_DRV_SEL (0x1<<14) //14:14
-#define RG_SSUSB_TX_DRV_DLY (0x3f<<8) //13:8
-#define RG_SSUSB_BERT_EN (0x1<<7) //7:7
-#define RG_SSUSB_SCP_TH (0x7<<4) //6:4
-#define RG_SSUSB_SCP_EN (0x1<<3) //3:3
-#define RG_SSUSB_RXANSIDEC_TEST (0x7<<0) //2:0
-
-//U3D_PHYD_LFPS0
-#define RG_SSUSB_LFPS_PWD (0x1<<30) //30:30
-#define RG_SSUSB_FORCE_LFPS_PWD (0x1<<29) //29:29
-#define RG_SSUSB_RXLFPS_OVF (0x1f<<24) //28:24
-#define RG_SSUSB_P3_ENTRY_SEL (0x1<<23) //23:23
-#define RG_SSUSB_P3_ENTRY (0x1<<22) //22:22
-#define RG_SSUSB_RXLFPS_CDRSEL (0x3<<20) //21:20
-#define RG_SSUSB_RXLFPS_CDRTH (0xf<<16) //19:16
-#define RG_SSUSB_LOCK5G_BLOCK (0x1<<15) //15:15
-#define RG_SSUSB_TFIFO_EXT_D_SEL (0x1<<14) //14:14
-#define RG_SSUSB_TFIFO_NO_EXTEND (0x1<<13) //13:13
-#define RG_SSUSB_RXLFPS_LOB (0x1f<<8) //12:8
-#define RG_SSUSB_TXLFPS_EN (0x1<<7) //7:7
-#define RG_SSUSB_TXLFPS_SEL (0x1<<6) //6:6
-#define RG_SSUSB_RXLFPS_CDRLOCK (0x1<<5) //5:5
-#define RG_SSUSB_RXLFPS_UPB (0x1f<<0) //4:0
-
-//U3D_PHYD_LFPS1
-#define RG_SSUSB_RX_IMP_BIAS (0xf<<28) //31:28
-#define RG_SSUSB_TX_IMP_BIAS (0xf<<24) //27:24
-#define RG_SSUSB_FWAKE_TH (0x3f<<16) //21:16
-#define RG_SSUSB_RXLFPS_UDF (0x1f<<8) //12:8
-#define RG_SSUSB_RXLFPS_P0IDLETH (0xff<<0) //7:0
-
-//U3D_PHYD_IMPCAL0
-#define RG_SSUSB_FORCE_TX_IMPSEL (0x1<<31) //31:31
-#define RG_SSUSB_TX_IMPCAL_EN (0x1<<30) //30:30
-#define RG_SSUSB_FORCE_TX_IMPCAL_EN (0x1<<29) //29:29
-#define RG_SSUSB_TX_IMPSEL (0x1f<<24) //28:24
-#define RG_SSUSB_TX_IMPCAL_CALCYC (0x3f<<16) //21:16
-#define RG_SSUSB_TX_IMPCAL_STBCYC (0x1f<<10) //14:10
-#define RG_SSUSB_TX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
-
-//U3D_PHYD_IMPCAL1
-#define RG_SSUSB_FORCE_RX_IMPSEL (0x1<<31) //31:31
-#define RG_SSUSB_RX_IMPCAL_EN (0x1<<30) //30:30
-#define RG_SSUSB_FORCE_RX_IMPCAL_EN (0x1<<29) //29:29
-#define RG_SSUSB_RX_IMPSEL (0x1f<<24) //28:24
-#define RG_SSUSB_RX_IMPCAL_CALCYC (0x3f<<16) //21:16
-#define RG_SSUSB_RX_IMPCAL_STBCYC (0x1f<<10) //14:10
-#define RG_SSUSB_RX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
-
-//U3D_PHYD_TXPLL0
-#define RG_SSUSB_TXPLL_DDSEN_CYC (0x1f<<27) //31:27
-#define RG_SSUSB_TXPLL_ON (0x1<<26) //26:26
-#define RG_SSUSB_FORCE_TXPLLON (0x1<<25) //25:25
-#define RG_SSUSB_TXPLL_STBCYC (0x1ff<<16) //24:16
-#define RG_SSUSB_TXPLL_NCPOCHG_CYC (0xf<<12) //15:12
-#define RG_SSUSB_TXPLL_NCPOEN_CYC (0x3<<10) //11:10
-#define RG_SSUSB_TXPLL_DDSRSTB_CYC (0x7<<0) //2:0
-
-//U3D_PHYD_TXPLL1
-#define RG_SSUSB_PLL_NCPO_EN (0x1<<31) //31:31
-#define RG_SSUSB_PLL_FIFO_START_MAN (0x1<<30) //30:30
-#define RG_SSUSB_PLL_NCPO_CHG (0x1<<28) //28:28
-#define RG_SSUSB_PLL_DDS_RSTB (0x1<<27) //27:27
-#define RG_SSUSB_PLL_DDS_PWDB (0x1<<26) //26:26
-#define RG_SSUSB_PLL_DDSEN (0x1<<25) //25:25
-#define RG_SSUSB_PLL_AUTOK_VCO (0x1<<24) //24:24
-#define RG_SSUSB_PLL_PWD (0x1<<23) //23:23
-#define RG_SSUSB_RX_AFE_PWD (0x1<<22) //22:22
-#define RG_SSUSB_PLL_TCADJ (0x3f<<16) //21:16
-#define RG_SSUSB_FORCE_CDR_TCADJ (0x1<<15) //15:15
-#define RG_SSUSB_FORCE_CDR_AUTOK_VCO (0x1<<14) //14:14
-#define RG_SSUSB_FORCE_CDR_PWD (0x1<<13) //13:13
-#define RG_SSUSB_FORCE_PLL_NCPO_EN (0x1<<12) //12:12
-#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN (0x1<<11) //11:11
-#define RG_SSUSB_FORCE_PLL_NCPO_CHG (0x1<<9) //9:9
-#define RG_SSUSB_FORCE_PLL_DDS_RSTB (0x1<<8) //8:8
-#define RG_SSUSB_FORCE_PLL_DDS_PWDB (0x1<<7) //7:7
-#define RG_SSUSB_FORCE_PLL_DDSEN (0x1<<6) //6:6
-#define RG_SSUSB_FORCE_PLL_TCADJ (0x1<<5) //5:5
-#define RG_SSUSB_FORCE_PLL_AUTOK_VCO (0x1<<4) //4:4
-#define RG_SSUSB_FORCE_PLL_PWD (0x1<<3) //3:3
-#define RG_SSUSB_FLT_1_DISPERR_B (0x1<<2) //2:2
-
-//U3D_PHYD_TXPLL2
-#define RG_SSUSB_TX_LFPS_EN (0x1<<31) //31:31
-#define RG_SSUSB_FORCE_TX_LFPS_EN (0x1<<30) //30:30
-#define RG_SSUSB_TX_LFPS (0x1<<29) //29:29
-#define RG_SSUSB_FORCE_TX_LFPS (0x1<<28) //28:28
-#define RG_SSUSB_RXPLL_STB (0x1<<27) //27:27
-#define RG_SSUSB_TXPLL_STB (0x1<<26) //26:26
-#define RG_SSUSB_FORCE_RXPLL_STB (0x1<<25) //25:25
-#define RG_SSUSB_FORCE_TXPLL_STB (0x1<<24) //24:24
-#define RG_SSUSB_RXPLL_REFCKSEL (0x1<<16) //16:16
-#define RG_SSUSB_RXPLL_STBMODE (0x1<<11) //11:11
-#define RG_SSUSB_RXPLL_ON (0x1<<10) //10:10
-#define RG_SSUSB_FORCE_RXPLLON (0x1<<9) //9:9
-#define RG_SSUSB_FORCE_RX_AFE_PWD (0x1<<8) //8:8
-#define RG_SSUSB_CDR_AUTOK_VCO (0x1<<7) //7:7
-#define RG_SSUSB_CDR_PWD (0x1<<6) //6:6
-#define RG_SSUSB_CDR_TCADJ (0x3f<<0) //5:0
-
-//U3D_PHYD_FL0
-#define RG_SSUSB_RX_FL_TARGET (0xffff<<16) //31:16
-#define RG_SSUSB_RX_FL_CYCLECNT (0xffff<<0) //15:0
-
-//U3D_PHYD_MIX2
-#define RG_SSUSB_RX_EQ_RST (0x1<<31) //31:31
-#define RG_SSUSB_RX_EQ_RST_SEL (0x1<<30) //30:30
-#define RG_SSUSB_RXVAL_RST (0x1<<29) //29:29
-#define RG_SSUSB_RXVAL_CNT (0x1f<<24) //28:24
-#define RG_SSUSB_CDROS_EN (0x1<<18) //18:18
-#define RG_SSUSB_CDR_LCKOP (0x3<<16) //17:16
-#define RG_SSUSB_RX_FL_LOCKTH (0xf<<8) //11:8
-#define RG_SSUSB_RX_FL_OFFSET (0xff<<0) //7:0
-
-//U3D_PHYD_RX0
-#define RG_SSUSB_T2RLB_BERTH (0xff<<24) //31:24
-#define RG_SSUSB_T2RLB_PAT (0xff<<16) //23:16
-#define RG_SSUSB_T2RLB_EN (0x1<<15) //15:15
-#define RG_SSUSB_T2RLB_BPSCRAMB (0x1<<14) //14:14
-#define RG_SSUSB_T2RLB_SERIAL (0x1<<13) //13:13
-#define RG_SSUSB_T2RLB_MODE (0x3<<11) //12:11
-#define RG_SSUSB_RX_SAOSC_EN (0x1<<10) //10:10
-#define RG_SSUSB_RX_SAOSC_EN_SEL (0x1<<9) //9:9
-#define RG_SSUSB_RX_DFE_OPTION (0x1<<8) //8:8
-#define RG_SSUSB_RX_DFE_EN (0x1<<7) //7:7
-#define RG_SSUSB_RX_DFE_EN_SEL (0x1<<6) //6:6
-#define RG_SSUSB_RX_EQ_EN (0x1<<5) //5:5
-#define RG_SSUSB_RX_EQ_EN_SEL (0x1<<4) //4:4
-#define RG_SSUSB_RX_SAOSC_RST (0x1<<3) //3:3
-#define RG_SSUSB_RX_SAOSC_RST_SEL (0x1<<2) //2:2
-#define RG_SSUSB_RX_DFE_RST (0x1<<1) //1:1
-#define RG_SSUSB_RX_DFE_RST_SEL (0x1<<0) //0:0
-
-//U3D_PHYD_T2RLB
-#define RG_SSUSB_EQTRAIN_CH_MODE (0x1<<28) //28:28
-#define RG_SSUSB_PRB_OUT_CPPAT (0x1<<27) //27:27
-#define RG_SSUSB_BPANSIENC (0x1<<26) //26:26
-#define RG_SSUSB_VALID_EN (0x1<<25) //25:25
-#define RG_SSUSB_EBUF_SRST (0x1<<24) //24:24
-#define RG_SSUSB_K_EMP (0xf<<20) //23:20
-#define RG_SSUSB_K_FUL (0xf<<16) //19:16
-#define RG_SSUSB_T2RLB_BDATRST (0xf<<12) //15:12
-#define RG_SSUSB_P_T2RLB_SKP_EN (0x1<<10) //10:10
-#define RG_SSUSB_T2RLB_PATMODE (0x3<<8) //9:8
-#define RG_SSUSB_T2RLB_TSEQCNT (0xff<<0) //7:0
-
-//U3D_PHYD_CPPAT
-#define RG_SSUSB_CPPAT_PROGRAM_EN (0x1<<24) //24:24
-#define RG_SSUSB_CPPAT_TOZ (0x3<<21) //22:21
-#define RG_SSUSB_CPPAT_PRBS_EN (0x1<<20) //20:20
-#define RG_SSUSB_CPPAT_OUT_TMP2 (0xf<<16) //19:16
-#define RG_SSUSB_CPPAT_OUT_TMP1 (0xff<<8) //15:8
-#define RG_SSUSB_CPPAT_OUT_TMP0 (0xff<<0) //7:0
-
-//U3D_PHYD_MIX3
-#define RG_SSUSB_CDR_TCADJ_MINUS (0x1<<31) //31:31
-#define RG_SSUSB_P_CDROS_EN (0x1<<30) //30:30
-#define RG_SSUSB_P_P2_TX_DRV_DIS (0x1<<28) //28:28
-#define RG_SSUSB_CDR_TCADJ_OFFSET (0x7<<24) //26:24
-#define RG_SSUSB_PLL_TCADJ_MINUS (0x1<<23) //23:23
-#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN (0x1<<20) //20:20
-#define RG_SSUSB_PLL_BIAS_LPF_EN (0x1<<19) //19:19
-#define RG_SSUSB_PLL_TCADJ_OFFSET (0x7<<16) //18:16
-#define RG_SSUSB_FORCE_PLL_SSCEN (0x1<<15) //15:15
-#define RG_SSUSB_PLL_SSCEN (0x1<<14) //14:14
-#define RG_SSUSB_FORCE_CDR_PI_PWD (0x1<<13) //13:13
-#define RG_SSUSB_CDR_PI_PWD (0x1<<12) //12:12
-#define RG_SSUSB_CDR_PI_MODE (0x1<<11) //11:11
-#define RG_SSUSB_TXPLL_SSCEN_CYC (0x3ff<<0) //9:0
-
-//U3D_PHYD_EBUFCTL
-#define RG_SSUSB_EBUFCTL (0xffffffff<<0) //31:0
-
-//U3D_PHYD_PIPE0
-#define RG_SSUSB_RXTERMINATION (0x1<<30) //30:30
-#define RG_SSUSB_RXEQTRAINING (0x1<<29) //29:29
-#define RG_SSUSB_RXPOLARITY (0x1<<28) //28:28
-#define RG_SSUSB_TXDEEMPH (0x3<<26) //27:26
-#define RG_SSUSB_POWERDOWN (0x3<<24) //25:24
-#define RG_SSUSB_TXONESZEROS (0x1<<23) //23:23
-#define RG_SSUSB_TXELECIDLE (0x1<<22) //22:22
-#define RG_SSUSB_TXDETECTRX (0x1<<21) //21:21
-#define RG_SSUSB_PIPE_SEL (0x1<<20) //20:20
-#define RG_SSUSB_TXDATAK (0xf<<16) //19:16
-#define RG_SSUSB_CDR_STABLE_SEL (0x1<<15) //15:15
-#define RG_SSUSB_CDR_STABLE (0x1<<14) //14:14
-#define RG_SSUSB_CDR_RSTB_SEL (0x1<<13) //13:13
-#define RG_SSUSB_CDR_RSTB (0x1<<12) //12:12
-#define RG_SSUSB_P_ERROR_SEL (0x3<<4) //5:4
-#define RG_SSUSB_TXMARGIN (0x7<<1) //3:1
-#define RG_SSUSB_TXCOMPLIANCE (0x1<<0) //0:0
-
-//U3D_PHYD_PIPE1
-#define RG_SSUSB_TXDATA (0xffffffff<<0) //31:0
-
-//U3D_PHYD_MIX4
-#define RG_SSUSB_CDROS_CNT (0x3f<<24) //29:24
-#define RG_SSUSB_T2RLB_BER_EN (0x1<<16) //16:16
-#define RG_SSUSB_T2RLB_BER_RATE (0xffff<<0) //15:0
-
-//U3D_PHYD_CKGEN0
-#define RG_SSUSB_RFIFO_IMPLAT (0x1<<27) //27:27
-#define RG_SSUSB_TFIFO_PSEL (0x7<<24) //26:24
-#define RG_SSUSB_CKGEN_PSEL (0x3<<8) //9:8
-#define RG_SSUSB_RXCK_INV (0x1<<0) //0:0
-
-//U3D_PHYD_MIX5
-#define RG_SSUSB_PRB_SEL (0xffff<<16) //31:16
-#define RG_SSUSB_RXPLL_STBCYC (0x7ff<<0) //10:0
-
-//U3D_PHYD_RESERVED
-#define RG_SSUSB_PHYD_RESERVE (0xffffffff<<0) //31:0
-//#define RG_SSUSB_RX_SIGDET_SEL (0x1<<11)
-//#define RG_SSUSB_RX_SIGDET_EN (0x1<<12)
-//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL (0x1<<9)
-//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN (0x1<<10)
-
-//U3D_PHYD_CDR0
-#define RG_SSUSB_CDR_BIC_LTR (0xf<<28) //31:28
-#define RG_SSUSB_CDR_BIC_LTD0 (0xf<<24) //27:24
-#define RG_SSUSB_CDR_BC_LTD1 (0x1f<<16) //20:16
-#define RG_SSUSB_CDR_BC_LTR (0x1f<<8) //12:8
-#define RG_SSUSB_CDR_BC_LTD0 (0x1f<<0) //4:0
-
-//U3D_PHYD_CDR1
-#define RG_SSUSB_CDR_BIR_LTD1 (0x1f<<24) //28:24
-#define RG_SSUSB_CDR_BIR_LTR (0x1f<<16) //20:16
-#define RG_SSUSB_CDR_BIR_LTD0 (0x1f<<8) //12:8
-#define RG_SSUSB_CDR_BW_SEL (0x3<<6) //7:6
-#define RG_SSUSB_CDR_BIC_LTD1 (0xf<<0) //3:0
-
-//U3D_PHYD_PLL_0
-#define RG_SSUSB_FORCE_CDR_BAND_5G (0x1<<28) //28:28
-#define RG_SSUSB_FORCE_CDR_BAND_2P5G (0x1<<27) //27:27
-#define RG_SSUSB_FORCE_PLL_BAND_5G (0x1<<26) //26:26
-#define RG_SSUSB_FORCE_PLL_BAND_2P5G (0x1<<25) //25:25
-#define RG_SSUSB_P_EQ_T_SEL (0x3ff<<15) //24:15
-#define RG_SSUSB_PLL_ISO_EN_CYC (0x3ff<<5) //14:5
-#define RG_SSUSB_PLLBAND_RECAL (0x1<<4) //4:4
-#define RG_SSUSB_PLL_DDS_ISO_EN (0x1<<3) //3:3
-#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN (0x1<<2) //2:2
-#define RG_SSUSB_PLL_DDS_PWR_ON (0x1<<1) //1:1
-#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON (0x1<<0) //0:0
-
-//U3D_PHYD_PLL_1
-#define RG_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
-#define RG_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
-#define RG_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
-#define RG_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
-
-//U3D_PHYD_BCN_DET_1
-#define RG_SSUSB_P_BCN_OBS_PRD (0xffff<<16) //31:16
-#define RG_SSUSB_U_BCN_OBS_PRD (0xffff<<0) //15:0
-
-//U3D_PHYD_BCN_DET_2
-#define RG_SSUSB_P_BCN_OBS_SEL (0xfff<<16) //27:16
-#define RG_SSUSB_BCN_DET_DIS (0x1<<12) //12:12
-#define RG_SSUSB_U_BCN_OBS_SEL (0xfff<<0) //11:0
-
-//U3D_EQ0
-#define RG_SSUSB_EQ_DLHL_LFI (0x7f<<24) //30:24
-#define RG_SSUSB_EQ_DHHL_LFI (0x7f<<16) //22:16
-#define RG_SSUSB_EQ_DD0HOS_LFI (0x7f<<8) //14:8
-#define RG_SSUSB_EQ_DD0LOS_LFI (0x7f<<0) //6:0
-
-//U3D_EQ1
-#define RG_SSUSB_EQ_DD1HOS_LFI (0x7f<<24) //30:24
-#define RG_SSUSB_EQ_DD1LOS_LFI (0x7f<<16) //22:16
-#define RG_SSUSB_EQ_DE0OS_LFI (0x7f<<8) //14:8
-#define RG_SSUSB_EQ_DE1OS_LFI (0x7f<<0) //6:0
-
-//U3D_EQ2
-#define RG_SSUSB_EQ_DLHLOS_LFI (0x7f<<24) //30:24
-#define RG_SSUSB_EQ_DHHLOS_LFI (0x7f<<16) //22:16
-#define RG_SSUSB_EQ_STOPTIME (0x1<<14) //14:14
-#define RG_SSUSB_EQ_DHHL_LF_SEL (0x7<<11) //13:11
-#define RG_SSUSB_EQ_DSAOS_LF_SEL (0x7<<8) //10:8
-#define RG_SSUSB_EQ_STARTTIME (0x3<<6) //7:6
-#define RG_SSUSB_EQ_DLEQ_LF_SEL (0x7<<3) //5:3
-#define RG_SSUSB_EQ_DLHL_LF_SEL (0x7<<0) //2:0
-
-//U3D_EQ3
-#define RG_SSUSB_EQ_DLEQ_LFI_GEN2 (0xf<<28) //31:28
-#define RG_SSUSB_EQ_DLEQ_LFI_GEN1 (0xf<<24) //27:24
-#define RG_SSUSB_EQ_DEYE0OS_LFI (0x7f<<16) //22:16
-#define RG_SSUSB_EQ_DEYE1OS_LFI (0x7f<<8) //14:8
-#define RG_SSUSB_EQ_TRI_DET_EN (0x1<<7) //7:7
-#define RG_SSUSB_EQ_TRI_DET_TH (0x7f<<0) //6:0
-
-//U3D_EQ_EYE0
-#define RG_SSUSB_EQ_EYE_XOFFSET (0x7f<<25) //31:25
-#define RG_SSUSB_EQ_EYE_MON_EN (0x1<<24) //24:24
-#define RG_SSUSB_EQ_EYE0_Y (0x7f<<16) //22:16
-#define RG_SSUSB_EQ_EYE1_Y (0x7f<<8) //14:8
-#define RG_SSUSB_EQ_PILPO_ROUT (0x1<<7) //7:7
-#define RG_SSUSB_EQ_PI_KPGAIN (0x7<<4) //6:4
-#define RG_SSUSB_EQ_EYE_CNT_EN (0x1<<3) //3:3
-
-//U3D_EQ_EYE1
-#define RG_SSUSB_EQ_SIGDET (0x7f<<24) //30:24
-#define RG_SSUSB_EQ_EYE_MASK (0x3ff<<7) //16:7
-
-//U3D_EQ_EYE2
-#define RG_SSUSB_EQ_RX500M_CK_SEL (0x1<<31) //31:31
-#define RG_SSUSB_EQ_SD_CNT1 (0x3f<<24) //29:24
-#define RG_SSUSB_EQ_ISIFLAG_SEL (0x3<<22) //23:22
-#define RG_SSUSB_EQ_SD_CNT0 (0x3f<<16) //21:16
-
-//U3D_EQ_DFE0
-#define RG_SSUSB_EQ_LEQMAX (0xf<<28) //31:28
-#define RG_SSUSB_EQ_DFEX_EN (0x1<<27) //27:27
-#define RG_SSUSB_EQ_DFEX_LF_SEL (0x7<<24) //26:24
-#define RG_SSUSB_EQ_CHK_EYE_H (0x1<<23) //23:23
-#define RG_SSUSB_EQ_PIEYE_INI (0x7f<<16) //22:16
-#define RG_SSUSB_EQ_PI90_INI (0x7f<<8) //14:8
-#define RG_SSUSB_EQ_PI0_INI (0x7f<<0) //6:0
-
-//U3D_EQ_DFE1
-#define RG_SSUSB_EQ_REV (0xffff<<16) //31:16
-#define RG_SSUSB_EQ_DFEYEN_DUR (0x7<<12) //14:12
-#define RG_SSUSB_EQ_DFEXEN_DUR (0x7<<8) //10:8
-#define RG_SSUSB_EQ_DFEX_RST (0x1<<7) //7:7
-#define RG_SSUSB_EQ_GATED_RXD_B (0x1<<6) //6:6
-#define RG_SSUSB_EQ_PI90CK_SEL (0x3<<4) //5:4
-#define RG_SSUSB_EQ_DFEX_DIS (0x1<<2) //2:2
-#define RG_SSUSB_EQ_DFEYEN_STOP_DIS (0x1<<1) //1:1
-#define RG_SSUSB_EQ_DFEXEN_SEL (0x1<<0) //0:0
-
-//U3D_EQ_DFE2
-#define RG_SSUSB_EQ_MON_SEL (0x1f<<24) //28:24
-#define RG_SSUSB_EQ_LEQOSC_DLYCNT (0x7<<16) //18:16
-#define RG_SSUSB_EQ_DLEQOS_LFI (0x1f<<8) //12:8
-#define RG_SSUSB_EQ_LEQ_STOP_TO (0x3<<0) //1:0
-
-//U3D_EQ_DFE3
-#define RG_SSUSB_EQ_RESERVED (0xffffffff<<0) //31:0
-
-//U3D_PHYD_MON0
-#define RGS_SSUSB_BERT_BERC (0xffff<<16) //31:16
-#define RGS_SSUSB_LFPS (0xf<<12) //15:12
-#define RGS_SSUSB_TRAINDEC (0x7<<8) //10:8
-#define RGS_SSUSB_SCP_PAT (0xff<<0) //7:0
-
-//U3D_PHYD_MON1
-#define RGS_SSUSB_RX_FL_OUT (0xffff<<0) //15:0
-
-//U3D_PHYD_MON2
-#define RGS_SSUSB_T2RLB_ERRCNT (0xffff<<16) //31:16
-#define RGS_SSUSB_RETRACK (0xf<<12) //15:12
-#define RGS_SSUSB_RXPLL_LOCK (0x1<<10) //10:10
-#define RGS_SSUSB_CDR_VCOCAL_CPLT_D (0x1<<9) //9:9
-#define RGS_SSUSB_PLL_VCOCAL_CPLT_D (0x1<<8) //8:8
-#define RGS_SSUSB_PDNCTL (0xff<<0) //7:0
-
-//U3D_PHYD_MON3
-#define RGS_SSUSB_TSEQ_ERRCNT (0xffff<<16) //31:16
-#define RGS_SSUSB_PRBS_ERRCNT (0xffff<<0) //15:0
-
-//U3D_PHYD_MON4
-#define RGS_SSUSB_RX_LSLOCK_CNT (0xf<<24) //27:24
-#define RGS_SSUSB_SCP_DETCNT (0xff<<16) //23:16
-#define RGS_SSUSB_TSEQ_DETCNT (0xffff<<0) //15:0
-
-//U3D_PHYD_MON5
-#define RGS_SSUSB_EBUFMSG (0xffff<<16) //31:16
-#define RGS_SSUSB_BERT_LOCK (0x1<<15) //15:15
-#define RGS_SSUSB_SCP_DET (0x1<<14) //14:14
-#define RGS_SSUSB_TSEQ_DET (0x1<<13) //13:13
-#define RGS_SSUSB_EBUF_UDF (0x1<<12) //12:12
-#define RGS_SSUSB_EBUF_OVF (0x1<<11) //11:11
-#define RGS_SSUSB_PRBS_PASSTH (0x1<<10) //10:10
-#define RGS_SSUSB_PRBS_PASS (0x1<<9) //9:9
-#define RGS_SSUSB_PRBS_LOCK (0x1<<8) //8:8
-#define RGS_SSUSB_T2RLB_ERR (0x1<<6) //6:6
-#define RGS_SSUSB_T2RLB_PASSTH (0x1<<5) //5:5
-#define RGS_SSUSB_T2RLB_PASS (0x1<<4) //4:4
-#define RGS_SSUSB_T2RLB_LOCK (0x1<<3) //3:3
-#define RGS_SSUSB_RX_IMPCAL_DONE (0x1<<2) //2:2
-#define RGS_SSUSB_TX_IMPCAL_DONE (0x1<<1) //1:1
-#define RGS_SSUSB_RXDETECTED (0x1<<0) //0:0
-
-//U3D_PHYD_MON6
-#define RGS_SSUSB_SIGCAL_DONE (0x1<<30) //30:30
-#define RGS_SSUSB_SIGCAL_CAL_OUT (0x1<<29) //29:29
-#define RGS_SSUSB_SIGCAL_OFFSET (0x1f<<24) //28:24
-#define RGS_SSUSB_RX_IMP_SEL (0x1f<<16) //20:16
-#define RGS_SSUSB_TX_IMP_SEL (0x1f<<8) //12:8
-#define RGS_SSUSB_TFIFO_MSG (0xf<<4) //7:4
-#define RGS_SSUSB_RFIFO_MSG (0xf<<0) //3:0
-
-//U3D_PHYD_MON7
-#define RGS_SSUSB_FT_OUT (0xff<<8) //15:8
-#define RGS_SSUSB_PRB_OUT (0xff<<0) //7:0
-
-//U3D_PHYA_RX_MON0
-#define RGS_SSUSB_EQ_DCLEQ (0xf<<24) //27:24
-#define RGS_SSUSB_EQ_DCD0H (0x7f<<16) //22:16
-#define RGS_SSUSB_EQ_DCD0L (0x7f<<8) //14:8
-#define RGS_SSUSB_EQ_DCD1H (0x7f<<0) //6:0
-
-//U3D_PHYA_RX_MON1
-#define RGS_SSUSB_EQ_DCD1L (0x7f<<24) //30:24
-#define RGS_SSUSB_EQ_DCE0 (0x7f<<16) //22:16
-#define RGS_SSUSB_EQ_DCE1 (0x7f<<8) //14:8
-#define RGS_SSUSB_EQ_DCHHL (0x7f<<0) //6:0
-
-//U3D_PHYA_RX_MON2
-#define RGS_SSUSB_EQ_LEQ_STOP (0x1<<31) //31:31
-#define RGS_SSUSB_EQ_DCLHL (0x7f<<24) //30:24
-#define RGS_SSUSB_EQ_STATUS (0xff<<16) //23:16
-#define RGS_SSUSB_EQ_DCEYE0 (0x7f<<8) //14:8
-#define RGS_SSUSB_EQ_DCEYE1 (0x7f<<0) //6:0
-
-//U3D_PHYA_RX_MON3
-#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0 (0xfffff<<0) //19:0
-
-//U3D_PHYA_RX_MON4
-#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1 (0xfffff<<0) //19:0
-
-//U3D_PHYA_RX_MON5
-#define RGS_SSUSB_EQ_DCLEQOS (0x1f<<8) //12:8
-#define RGS_SSUSB_EQ_EYE_CNT_RDY (0x1<<7) //7:7
-#define RGS_SSUSB_EQ_PILPO (0x7f<<0) //6:0
-
-//U3D_PHYD_CPPAT2
-#define RG_SSUSB_CPPAT_OUT_H_TMP2 (0xf<<16) //19:16
-#define RG_SSUSB_CPPAT_OUT_H_TMP1 (0xff<<8) //15:8
-#define RG_SSUSB_CPPAT_OUT_H_TMP0 (0xff<<0) //7:0
-
-//U3D_EQ_EYE3
-#define RG_SSUSB_EQ_LEQ_SHIFT (0x7<<24) //26:24
-#define RG_SSUSB_EQ_EYE_CNT (0xfffff<<0) //19:0
-
-//U3D_KBAND_OUT
-#define RGS_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
-#define RGS_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
-#define RGS_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
-#define RGS_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
-
-//U3D_KBAND_OUT1
-#define RGS_SSUSB_CDR_VCOCAL_FAIL (0x1<<24) //24:24
-#define RGS_SSUSB_CDR_VCOCAL_STATE (0xff<<16) //23:16
-#define RGS_SSUSB_PLL_VCOCAL_FAIL (0x1<<8) //8:8
-#define RGS_SSUSB_PLL_VCOCAL_STATE (0xff<<0) //7:0
-
-
-/* OFFSET */
-
-//U3D_PHYD_MIX0
-#define RG_SSUSB_P_P3_TX_NG_OFST (31)
-#define RG_SSUSB_TSEQ_EN_OFST (30)
-#define RG_SSUSB_TSEQ_POLEN_OFST (29)
-#define RG_SSUSB_TSEQ_POL_OFST (28)
-#define RG_SSUSB_P_P3_PCLK_NG_OFST (27)
-#define RG_SSUSB_TSEQ_TH_OFST (24)
-#define RG_SSUSB_PRBS_BERTH_OFST (16)
-#define RG_SSUSB_DISABLE_PHY_U2_ON_OFST (15)
-#define RG_SSUSB_DISABLE_PHY_U2_OFF_OFST (14)
-#define RG_SSUSB_PRBS_EN_OFST (13)
-#define RG_SSUSB_BPSLOCK_OFST (12)
-#define RG_SSUSB_RTCOMCNT_OFST (8)
-#define RG_SSUSB_COMCNT_OFST (4)
-#define RG_SSUSB_PRBSEL_CALIB_OFST (0)
-
-//U3D_PHYD_MIX1
-#define RG_SSUSB_SLEEP_EN_OFST (31)
-#define RG_SSUSB_PRBSEL_PCS_OFST (28)
-#define RG_SSUSB_TXLFPS_PRD_OFST (24)
-#define RG_SSUSB_P_RX_P0S_CK_OFST (23)
-#define RG_SSUSB_P_TX_P0S_CK_OFST (22)
-#define RG_SSUSB_PDNCTL_OFST (16)
-#define RG_SSUSB_TX_DRV_EN_OFST (15)
-#define RG_SSUSB_TX_DRV_SEL_OFST (14)
-#define RG_SSUSB_TX_DRV_DLY_OFST (8)
-#define RG_SSUSB_BERT_EN_OFST (7)
-#define RG_SSUSB_SCP_TH_OFST (4)
-#define RG_SSUSB_SCP_EN_OFST (3)
-#define RG_SSUSB_RXANSIDEC_TEST_OFST (0)
-
-//U3D_PHYD_LFPS0
-#define RG_SSUSB_LFPS_PWD_OFST (30)
-#define RG_SSUSB_FORCE_LFPS_PWD_OFST (29)
-#define RG_SSUSB_RXLFPS_OVF_OFST (24)
-#define RG_SSUSB_P3_ENTRY_SEL_OFST (23)
-#define RG_SSUSB_P3_ENTRY_OFST (22)
-#define RG_SSUSB_RXLFPS_CDRSEL_OFST (20)
-#define RG_SSUSB_RXLFPS_CDRTH_OFST (16)
-#define RG_SSUSB_LOCK5G_BLOCK_OFST (15)
-#define RG_SSUSB_TFIFO_EXT_D_SEL_OFST (14)
-#define RG_SSUSB_TFIFO_NO_EXTEND_OFST (13)
-#define RG_SSUSB_RXLFPS_LOB_OFST (8)
-#define RG_SSUSB_TXLFPS_EN_OFST (7)
-#define RG_SSUSB_TXLFPS_SEL_OFST (6)
-#define RG_SSUSB_RXLFPS_CDRLOCK_OFST (5)
-#define RG_SSUSB_RXLFPS_UPB_OFST (0)
-
-//U3D_PHYD_LFPS1
-#define RG_SSUSB_RX_IMP_BIAS_OFST (28)
-#define RG_SSUSB_TX_IMP_BIAS_OFST (24)
-#define RG_SSUSB_FWAKE_TH_OFST (16)
-#define RG_SSUSB_RXLFPS_UDF_OFST (8)
-#define RG_SSUSB_RXLFPS_P0IDLETH_OFST (0)
-
-//U3D_PHYD_IMPCAL0
-#define RG_SSUSB_FORCE_TX_IMPSEL_OFST (31)
-#define RG_SSUSB_TX_IMPCAL_EN_OFST (30)
-#define RG_SSUSB_FORCE_TX_IMPCAL_EN_OFST (29)
-#define RG_SSUSB_TX_IMPSEL_OFST (24)
-#define RG_SSUSB_TX_IMPCAL_CALCYC_OFST (16)
-#define RG_SSUSB_TX_IMPCAL_STBCYC_OFST (10)
-#define RG_SSUSB_TX_IMPCAL_CYCCNT_OFST (0)
-
-//U3D_PHYD_IMPCAL1
-#define RG_SSUSB_FORCE_RX_IMPSEL_OFST (31)
-#define RG_SSUSB_RX_IMPCAL_EN_OFST (30)
-#define RG_SSUSB_FORCE_RX_IMPCAL_EN_OFST (29)
-#define RG_SSUSB_RX_IMPSEL_OFST (24)
-#define RG_SSUSB_RX_IMPCAL_CALCYC_OFST (16)
-#define RG_SSUSB_RX_IMPCAL_STBCYC_OFST (10)
-#define RG_SSUSB_RX_IMPCAL_CYCCNT_OFST (0)
-
-//U3D_PHYD_TXPLL0
-#define RG_SSUSB_TXPLL_DDSEN_CYC_OFST (27)
-#define RG_SSUSB_TXPLL_ON_OFST (26)
-#define RG_SSUSB_FORCE_TXPLLON_OFST (25)
-#define RG_SSUSB_TXPLL_STBCYC_OFST (16)
-#define RG_SSUSB_TXPLL_NCPOCHG_CYC_OFST (12)
-#define RG_SSUSB_TXPLL_NCPOEN_CYC_OFST (10)
-#define RG_SSUSB_TXPLL_DDSRSTB_CYC_OFST (0)
-
-//U3D_PHYD_TXPLL1
-#define RG_SSUSB_PLL_NCPO_EN_OFST (31)
-#define RG_SSUSB_PLL_FIFO_START_MAN_OFST (30)
-#define RG_SSUSB_PLL_NCPO_CHG_OFST (28)
-#define RG_SSUSB_PLL_DDS_RSTB_OFST (27)
-#define RG_SSUSB_PLL_DDS_PWDB_OFST (26)
-#define RG_SSUSB_PLL_DDSEN_OFST (25)
-#define RG_SSUSB_PLL_AUTOK_VCO_OFST (24)
-#define RG_SSUSB_PLL_PWD_OFST (23)
-#define RG_SSUSB_RX_AFE_PWD_OFST (22)
-#define RG_SSUSB_PLL_TCADJ_OFST (16)
-#define RG_SSUSB_FORCE_CDR_TCADJ_OFST (15)
-#define RG_SSUSB_FORCE_CDR_AUTOK_VCO_OFST (14)
-#define RG_SSUSB_FORCE_CDR_PWD_OFST (13)
-#define RG_SSUSB_FORCE_PLL_NCPO_EN_OFST (12)
-#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN_OFST (11)
-#define RG_SSUSB_FORCE_PLL_NCPO_CHG_OFST (9)
-#define RG_SSUSB_FORCE_PLL_DDS_RSTB_OFST (8)
-#define RG_SSUSB_FORCE_PLL_DDS_PWDB_OFST (7)
-#define RG_SSUSB_FORCE_PLL_DDSEN_OFST (6)
-#define RG_SSUSB_FORCE_PLL_TCADJ_OFST (5)
-#define RG_SSUSB_FORCE_PLL_AUTOK_VCO_OFST (4)
-#define RG_SSUSB_FORCE_PLL_PWD_OFST (3)
-#define RG_SSUSB_FLT_1_DISPERR_B_OFST (2)
-
-//U3D_PHYD_TXPLL2
-#define RG_SSUSB_TX_LFPS_EN_OFST (31)
-#define RG_SSUSB_FORCE_TX_LFPS_EN_OFST (30)
-#define RG_SSUSB_TX_LFPS_OFST (29)
-#define RG_SSUSB_FORCE_TX_LFPS_OFST (28)
-#define RG_SSUSB_RXPLL_STB_OFST (27)
-#define RG_SSUSB_TXPLL_STB_OFST (26)
-#define RG_SSUSB_FORCE_RXPLL_STB_OFST (25)
-#define RG_SSUSB_FORCE_TXPLL_STB_OFST (24)
-#define RG_SSUSB_RXPLL_REFCKSEL_OFST (16)
-#define RG_SSUSB_RXPLL_STBMODE_OFST (11)
-#define RG_SSUSB_RXPLL_ON_OFST (10)
-#define RG_SSUSB_FORCE_RXPLLON_OFST (9)
-#define RG_SSUSB_FORCE_RX_AFE_PWD_OFST (8)
-#define RG_SSUSB_CDR_AUTOK_VCO_OFST (7)
-#define RG_SSUSB_CDR_PWD_OFST (6)
-#define RG_SSUSB_CDR_TCADJ_OFST (0)
-
-//U3D_PHYD_FL0
-#define RG_SSUSB_RX_FL_TARGET_OFST (16)
-#define RG_SSUSB_RX_FL_CYCLECNT_OFST (0)
-
-//U3D_PHYD_MIX2
-#define RG_SSUSB_RX_EQ_RST_OFST (31)
-#define RG_SSUSB_RX_EQ_RST_SEL_OFST (30)
-#define RG_SSUSB_RXVAL_RST_OFST (29)
-#define RG_SSUSB_RXVAL_CNT_OFST (24)
-#define RG_SSUSB_CDROS_EN_OFST (18)
-#define RG_SSUSB_CDR_LCKOP_OFST (16)
-#define RG_SSUSB_RX_FL_LOCKTH_OFST (8)
-#define RG_SSUSB_RX_FL_OFFSET_OFST (0)
-
-//U3D_PHYD_RX0
-#define RG_SSUSB_T2RLB_BERTH_OFST (24)
-#define RG_SSUSB_T2RLB_PAT_OFST (16)
-#define RG_SSUSB_T2RLB_EN_OFST (15)
-#define RG_SSUSB_T2RLB_BPSCRAMB_OFST (14)
-#define RG_SSUSB_T2RLB_SERIAL_OFST (13)
-#define RG_SSUSB_T2RLB_MODE_OFST (11)
-#define RG_SSUSB_RX_SAOSC_EN_OFST (10)
-#define RG_SSUSB_RX_SAOSC_EN_SEL_OFST (9)
-#define RG_SSUSB_RX_DFE_OPTION_OFST (8)
-#define RG_SSUSB_RX_DFE_EN_OFST (7)
-#define RG_SSUSB_RX_DFE_EN_SEL_OFST (6)
-#define RG_SSUSB_RX_EQ_EN_OFST (5)
-#define RG_SSUSB_RX_EQ_EN_SEL_OFST (4)
-#define RG_SSUSB_RX_SAOSC_RST_OFST (3)
-#define RG_SSUSB_RX_SAOSC_RST_SEL_OFST (2)
-#define RG_SSUSB_RX_DFE_RST_OFST (1)
-#define RG_SSUSB_RX_DFE_RST_SEL_OFST (0)
-
-//U3D_PHYD_T2RLB
-#define RG_SSUSB_EQTRAIN_CH_MODE_OFST (28)
-#define RG_SSUSB_PRB_OUT_CPPAT_OFST (27)
-#define RG_SSUSB_BPANSIENC_OFST (26)
-#define RG_SSUSB_VALID_EN_OFST (25)
-#define RG_SSUSB_EBUF_SRST_OFST (24)
-#define RG_SSUSB_K_EMP_OFST (20)
-#define RG_SSUSB_K_FUL_OFST (16)
-#define RG_SSUSB_T2RLB_BDATRST_OFST (12)
-#define RG_SSUSB_P_T2RLB_SKP_EN_OFST (10)
-#define RG_SSUSB_T2RLB_PATMODE_OFST (8)
-#define RG_SSUSB_T2RLB_TSEQCNT_OFST (0)
-
-//U3D_PHYD_CPPAT
-#define RG_SSUSB_CPPAT_PROGRAM_EN_OFST (24)
-#define RG_SSUSB_CPPAT_TOZ_OFST (21)
-#define RG_SSUSB_CPPAT_PRBS_EN_OFST (20)
-#define RG_SSUSB_CPPAT_OUT_TMP2_OFST (16)
-#define RG_SSUSB_CPPAT_OUT_TMP1_OFST (8)
-#define RG_SSUSB_CPPAT_OUT_TMP0_OFST (0)
-
-//U3D_PHYD_MIX3
-#define RG_SSUSB_CDR_TCADJ_MINUS_OFST (31)
-#define RG_SSUSB_P_CDROS_EN_OFST (30)
-#define RG_SSUSB_P_P2_TX_DRV_DIS_OFST (28)
-#define RG_SSUSB_CDR_TCADJ_OFFSET_OFST (24)
-#define RG_SSUSB_PLL_TCADJ_MINUS_OFST (23)
-#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN_OFST (20)
-#define RG_SSUSB_PLL_BIAS_LPF_EN_OFST (19)
-#define RG_SSUSB_PLL_TCADJ_OFFSET_OFST (16)
-#define RG_SSUSB_FORCE_PLL_SSCEN_OFST (15)
-#define RG_SSUSB_PLL_SSCEN_OFST (14)
-#define RG_SSUSB_FORCE_CDR_PI_PWD_OFST (13)
-#define RG_SSUSB_CDR_PI_PWD_OFST (12)
-#define RG_SSUSB_CDR_PI_MODE_OFST (11)
-#define RG_SSUSB_TXPLL_SSCEN_CYC_OFST (0)
-
-//U3D_PHYD_EBUFCTL
-#define RG_SSUSB_EBUFCTL_OFST (0)
-
-//U3D_PHYD_PIPE0
-#define RG_SSUSB_RXTERMINATION_OFST (30)
-#define RG_SSUSB_RXEQTRAINING_OFST (29)
-#define RG_SSUSB_RXPOLARITY_OFST (28)
-#define RG_SSUSB_TXDEEMPH_OFST (26)
-#define RG_SSUSB_POWERDOWN_OFST (24)
-#define RG_SSUSB_TXONESZEROS_OFST (23)
-#define RG_SSUSB_TXELECIDLE_OFST (22)
-#define RG_SSUSB_TXDETECTRX_OFST (21)
-#define RG_SSUSB_PIPE_SEL_OFST (20)
-#define RG_SSUSB_TXDATAK_OFST (16)
-#define RG_SSUSB_CDR_STABLE_SEL_OFST (15)
-#define RG_SSUSB_CDR_STABLE_OFST (14)
-#define RG_SSUSB_CDR_RSTB_SEL_OFST (13)
-#define RG_SSUSB_CDR_RSTB_OFST (12)
-#define RG_SSUSB_P_ERROR_SEL_OFST (4)
-#define RG_SSUSB_TXMARGIN_OFST (1)
-#define RG_SSUSB_TXCOMPLIANCE_OFST (0)
-
-//U3D_PHYD_PIPE1
-#define RG_SSUSB_TXDATA_OFST (0)
-
-//U3D_PHYD_MIX4
-#define RG_SSUSB_CDROS_CNT_OFST (24)
-#define RG_SSUSB_T2RLB_BER_EN_OFST (16)
-#define RG_SSUSB_T2RLB_BER_RATE_OFST (0)
-
-//U3D_PHYD_CKGEN0
-#define RG_SSUSB_RFIFO_IMPLAT_OFST (27)
-#define RG_SSUSB_TFIFO_PSEL_OFST (24)
-#define RG_SSUSB_CKGEN_PSEL_OFST (8)
-#define RG_SSUSB_RXCK_INV_OFST (0)
-
-//U3D_PHYD_MIX5
-#define RG_SSUSB_PRB_SEL_OFST (16)
-#define RG_SSUSB_RXPLL_STBCYC_OFST (0)
-
-//U3D_PHYD_RESERVED
-#define RG_SSUSB_PHYD_RESERVE_OFST (0)
-//#define RG_SSUSB_RX_SIGDET_SEL_OFST (11)
-//#define RG_SSUSB_RX_SIGDET_EN_OFST (12)
-//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL_OFST (9)
-//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN_OFST (10)
-
-//U3D_PHYD_CDR0
-#define RG_SSUSB_CDR_BIC_LTR_OFST (28)
-#define RG_SSUSB_CDR_BIC_LTD0_OFST (24)
-#define RG_SSUSB_CDR_BC_LTD1_OFST (16)
-#define RG_SSUSB_CDR_BC_LTR_OFST (8)
-#define RG_SSUSB_CDR_BC_LTD0_OFST (0)
-
-//U3D_PHYD_CDR1
-#define RG_SSUSB_CDR_BIR_LTD1_OFST (24)
-#define RG_SSUSB_CDR_BIR_LTR_OFST (16)
-#define RG_SSUSB_CDR_BIR_LTD0_OFST (8)
-#define RG_SSUSB_CDR_BW_SEL_OFST (6)
-#define RG_SSUSB_CDR_BIC_LTD1_OFST (0)
-
-//U3D_PHYD_PLL_0
-#define RG_SSUSB_FORCE_CDR_BAND_5G_OFST (28)
-#define RG_SSUSB_FORCE_CDR_BAND_2P5G_OFST (27)
-#define RG_SSUSB_FORCE_PLL_BAND_5G_OFST (26)
-#define RG_SSUSB_FORCE_PLL_BAND_2P5G_OFST (25)
-#define RG_SSUSB_P_EQ_T_SEL_OFST (15)
-#define RG_SSUSB_PLL_ISO_EN_CYC_OFST (5)
-#define RG_SSUSB_PLLBAND_RECAL_OFST (4)
-#define RG_SSUSB_PLL_DDS_ISO_EN_OFST (3)
-#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN_OFST (2)
-#define RG_SSUSB_PLL_DDS_PWR_ON_OFST (1)
-#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON_OFST (0)
-
-//U3D_PHYD_PLL_1
-#define RG_SSUSB_CDR_BAND_5G_OFST (24)
-#define RG_SSUSB_CDR_BAND_2P5G_OFST (16)
-#define RG_SSUSB_PLL_BAND_5G_OFST (8)
-#define RG_SSUSB_PLL_BAND_2P5G_OFST (0)
-
-//U3D_PHYD_BCN_DET_1
-#define RG_SSUSB_P_BCN_OBS_PRD_OFST (16)
-#define RG_SSUSB_U_BCN_OBS_PRD_OFST (0)
-
-//U3D_PHYD_BCN_DET_2
-#define RG_SSUSB_P_BCN_OBS_SEL_OFST (16)
-#define RG_SSUSB_BCN_DET_DIS_OFST (12)
-#define RG_SSUSB_U_BCN_OBS_SEL_OFST (0)
-
-//U3D_EQ0
-#define RG_SSUSB_EQ_DLHL_LFI_OFST (24)
-#define RG_SSUSB_EQ_DHHL_LFI_OFST (16)
-#define RG_SSUSB_EQ_DD0HOS_LFI_OFST (8)
-#define RG_SSUSB_EQ_DD0LOS_LFI_OFST (0)
-
-//U3D_EQ1
-#define RG_SSUSB_EQ_DD1HOS_LFI_OFST (24)
-#define RG_SSUSB_EQ_DD1LOS_LFI_OFST (16)
-#define RG_SSUSB_EQ_DE0OS_LFI_OFST (8)
-#define RG_SSUSB_EQ_DE1OS_LFI_OFST (0)
-
-//U3D_EQ2
-#define RG_SSUSB_EQ_DLHLOS_LFI_OFST (24)
-#define RG_SSUSB_EQ_DHHLOS_LFI_OFST (16)
-#define RG_SSUSB_EQ_STOPTIME_OFST (14)
-#define RG_SSUSB_EQ_DHHL_LF_SEL_OFST (11)
-#define RG_SSUSB_EQ_DSAOS_LF_SEL_OFST (8)
-#define RG_SSUSB_EQ_STARTTIME_OFST (6)
-#define RG_SSUSB_EQ_DLEQ_LF_SEL_OFST (3)
-#define RG_SSUSB_EQ_DLHL_LF_SEL_OFST (0)
-
-//U3D_EQ3
-#define RG_SSUSB_EQ_DLEQ_LFI_GEN2_OFST (28)
-#define RG_SSUSB_EQ_DLEQ_LFI_GEN1_OFST (24)
-#define RG_SSUSB_EQ_DEYE0OS_LFI_OFST (16)
-#define RG_SSUSB_EQ_DEYE1OS_LFI_OFST (8)
-#define RG_SSUSB_EQ_TRI_DET_EN_OFST (7)
-#define RG_SSUSB_EQ_TRI_DET_TH_OFST (0)
-
-//U3D_EQ_EYE0
-#define RG_SSUSB_EQ_EYE_XOFFSET_OFST (25)
-#define RG_SSUSB_EQ_EYE_MON_EN_OFST (24)
-#define RG_SSUSB_EQ_EYE0_Y_OFST (16)
-#define RG_SSUSB_EQ_EYE1_Y_OFST (8)
-#define RG_SSUSB_EQ_PILPO_ROUT_OFST (7)
-#define RG_SSUSB_EQ_PI_KPGAIN_OFST (4)
-#define RG_SSUSB_EQ_EYE_CNT_EN_OFST (3)
-
-//U3D_EQ_EYE1
-#define RG_SSUSB_EQ_SIGDET_OFST (24)
-#define RG_SSUSB_EQ_EYE_MASK_OFST (7)
-
-//U3D_EQ_EYE2
-#define RG_SSUSB_EQ_RX500M_CK_SEL_OFST (31)
-#define RG_SSUSB_EQ_SD_CNT1_OFST (24)
-#define RG_SSUSB_EQ_ISIFLAG_SEL_OFST (22)
-#define RG_SSUSB_EQ_SD_CNT0_OFST (16)
-
-//U3D_EQ_DFE0
-#define RG_SSUSB_EQ_LEQMAX_OFST (28)
-#define RG_SSUSB_EQ_DFEX_EN_OFST (27)
-#define RG_SSUSB_EQ_DFEX_LF_SEL_OFST (24)
-#define RG_SSUSB_EQ_CHK_EYE_H_OFST (23)
-#define RG_SSUSB_EQ_PIEYE_INI_OFST (16)
-#define RG_SSUSB_EQ_PI90_INI_OFST (8)
-#define RG_SSUSB_EQ_PI0_INI_OFST (0)
-
-//U3D_EQ_DFE1
-#define RG_SSUSB_EQ_REV_OFST (16)
-#define RG_SSUSB_EQ_DFEYEN_DUR_OFST (12)
-#define RG_SSUSB_EQ_DFEXEN_DUR_OFST (8)
-#define RG_SSUSB_EQ_DFEX_RST_OFST (7)
-#define RG_SSUSB_EQ_GATED_RXD_B_OFST (6)
-#define RG_SSUSB_EQ_PI90CK_SEL_OFST (4)
-#define RG_SSUSB_EQ_DFEX_DIS_OFST (2)
-#define RG_SSUSB_EQ_DFEYEN_STOP_DIS_OFST (1)
-#define RG_SSUSB_EQ_DFEXEN_SEL_OFST (0)
-
-//U3D_EQ_DFE2
-#define RG_SSUSB_EQ_MON_SEL_OFST (24)
-#define RG_SSUSB_EQ_LEQOSC_DLYCNT_OFST (16)
-#define RG_SSUSB_EQ_DLEQOS_LFI_OFST (8)
-#define RG_SSUSB_EQ_LEQ_STOP_TO_OFST (0)
-
-//U3D_EQ_DFE3
-#define RG_SSUSB_EQ_RESERVED_OFST (0)
-
-//U3D_PHYD_MON0
-#define RGS_SSUSB_BERT_BERC_OFST (16)
-#define RGS_SSUSB_LFPS_OFST (12)
-#define RGS_SSUSB_TRAINDEC_OFST (8)
-#define RGS_SSUSB_SCP_PAT_OFST (0)
-
-//U3D_PHYD_MON1
-#define RGS_SSUSB_RX_FL_OUT_OFST (0)
-
-//U3D_PHYD_MON2
-#define RGS_SSUSB_T2RLB_ERRCNT_OFST (16)
-#define RGS_SSUSB_RETRACK_OFST (12)
-#define RGS_SSUSB_RXPLL_LOCK_OFST (10)
-#define RGS_SSUSB_CDR_VCOCAL_CPLT_D_OFST (9)
-#define RGS_SSUSB_PLL_VCOCAL_CPLT_D_OFST (8)
-#define RGS_SSUSB_PDNCTL_OFST (0)
-
-//U3D_PHYD_MON3
-#define RGS_SSUSB_TSEQ_ERRCNT_OFST (16)
-#define RGS_SSUSB_PRBS_ERRCNT_OFST (0)
-
-//U3D_PHYD_MON4
-#define RGS_SSUSB_RX_LSLOCK_CNT_OFST (24)
-#define RGS_SSUSB_SCP_DETCNT_OFST (16)
-#define RGS_SSUSB_TSEQ_DETCNT_OFST (0)
-
-//U3D_PHYD_MON5
-#define RGS_SSUSB_EBUFMSG_OFST (16)
-#define RGS_SSUSB_BERT_LOCK_OFST (15)
-#define RGS_SSUSB_SCP_DET_OFST (14)
-#define RGS_SSUSB_TSEQ_DET_OFST (13)
-#define RGS_SSUSB_EBUF_UDF_OFST (12)
-#define RGS_SSUSB_EBUF_OVF_OFST (11)
-#define RGS_SSUSB_PRBS_PASSTH_OFST (10)
-#define RGS_SSUSB_PRBS_PASS_OFST (9)
-#define RGS_SSUSB_PRBS_LOCK_OFST (8)
-#define RGS_SSUSB_T2RLB_ERR_OFST (6)
-#define RGS_SSUSB_T2RLB_PASSTH_OFST (5)
-#define RGS_SSUSB_T2RLB_PASS_OFST (4)
-#define RGS_SSUSB_T2RLB_LOCK_OFST (3)
-#define RGS_SSUSB_RX_IMPCAL_DONE_OFST (2)
-#define RGS_SSUSB_TX_IMPCAL_DONE_OFST (1)
-#define RGS_SSUSB_RXDETECTED_OFST (0)
-
-//U3D_PHYD_MON6
-#define RGS_SSUSB_SIGCAL_DONE_OFST (30)
-#define RGS_SSUSB_SIGCAL_CAL_OUT_OFST (29)
-#define RGS_SSUSB_SIGCAL_OFFSET_OFST (24)
-#define RGS_SSUSB_RX_IMP_SEL_OFST (16)
-#define RGS_SSUSB_TX_IMP_SEL_OFST (8)
-#define RGS_SSUSB_TFIFO_MSG_OFST (4)
-#define RGS_SSUSB_RFIFO_MSG_OFST (0)
-
-//U3D_PHYD_MON7
-#define RGS_SSUSB_FT_OUT_OFST (8)
-#define RGS_SSUSB_PRB_OUT_OFST (0)
-
-//U3D_PHYA_RX_MON0
-#define RGS_SSUSB_EQ_DCLEQ_OFST (24)
-#define RGS_SSUSB_EQ_DCD0H_OFST (16)
-#define RGS_SSUSB_EQ_DCD0L_OFST (8)
-#define RGS_SSUSB_EQ_DCD1H_OFST (0)
-
-//U3D_PHYA_RX_MON1
-#define RGS_SSUSB_EQ_DCD1L_OFST (24)
-#define RGS_SSUSB_EQ_DCE0_OFST (16)
-#define RGS_SSUSB_EQ_DCE1_OFST (8)
-#define RGS_SSUSB_EQ_DCHHL_OFST (0)
-
-//U3D_PHYA_RX_MON2
-#define RGS_SSUSB_EQ_LEQ_STOP_OFST (31)
-#define RGS_SSUSB_EQ_DCLHL_OFST (24)
-#define RGS_SSUSB_EQ_STATUS_OFST (16)
-#define RGS_SSUSB_EQ_DCEYE0_OFST (8)
-#define RGS_SSUSB_EQ_DCEYE1_OFST (0)
-
-//U3D_PHYA_RX_MON3
-#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST (0)
-
-//U3D_PHYA_RX_MON4
-#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST (0)
-
-//U3D_PHYA_RX_MON5
-#define RGS_SSUSB_EQ_DCLEQOS_OFST (8)
-#define RGS_SSUSB_EQ_EYE_CNT_RDY_OFST (7)
-#define RGS_SSUSB_EQ_PILPO_OFST (0)
-
-//U3D_PHYD_CPPAT2
-#define RG_SSUSB_CPPAT_OUT_H_TMP2_OFST (16)
-#define RG_SSUSB_CPPAT_OUT_H_TMP1_OFST (8)
-#define RG_SSUSB_CPPAT_OUT_H_TMP0_OFST (0)
-
-//U3D_EQ_EYE3
-#define RG_SSUSB_EQ_LEQ_SHIFT_OFST (24)
-#define RG_SSUSB_EQ_EYE_CNT_OFST (0)
-
-//U3D_KBAND_OUT
-#define RGS_SSUSB_CDR_BAND_5G_OFST (24)
-#define RGS_SSUSB_CDR_BAND_2P5G_OFST (16)
-#define RGS_SSUSB_PLL_BAND_5G_OFST (8)
-#define RGS_SSUSB_PLL_BAND_2P5G_OFST (0)
-
-//U3D_KBAND_OUT1
-#define RGS_SSUSB_CDR_VCOCAL_FAIL_OFST (24)
-#define RGS_SSUSB_CDR_VCOCAL_STATE_OFST (16)
-#define RGS_SSUSB_PLL_VCOCAL_FAIL_OFST (8)
-#define RGS_SSUSB_PLL_VCOCAL_STATE_OFST (0)
-
-
-///////////////////////////////////////////////////////////////////////////////
-
-struct u3phyd_bank2_reg {
- //0x0
- PHY_LE32 b2_phyd_top1;
- PHY_LE32 b2_phyd_top2;
- PHY_LE32 b2_phyd_top3;
- PHY_LE32 b2_phyd_top4;
- //0x10
- PHY_LE32 b2_phyd_top5;
- PHY_LE32 b2_phyd_top6;
- PHY_LE32 b2_phyd_top7;
- PHY_LE32 b2_phyd_p_sigdet1;
- //0x20
- PHY_LE32 b2_phyd_p_sigdet2;
- PHY_LE32 b2_phyd_p_sigdet_cal1;
- PHY_LE32 b2_phyd_rxdet1;
- PHY_LE32 b2_phyd_rxdet2;
- //0x30
- PHY_LE32 b2_phyd_misc0;
- PHY_LE32 b2_phyd_misc2;
- PHY_LE32 b2_phyd_misc3;
- PHY_LE32 reserve0;
- //0x40
- PHY_LE32 b2_rosc_0;
- PHY_LE32 b2_rosc_1;
- PHY_LE32 b2_rosc_2;
- PHY_LE32 b2_rosc_3;
- //0x50
- PHY_LE32 b2_rosc_4;
- PHY_LE32 b2_rosc_5;
- PHY_LE32 b2_rosc_6;
- PHY_LE32 b2_rosc_7;
- //0x60
- PHY_LE32 b2_rosc_8;
- PHY_LE32 b2_rosc_9;
- PHY_LE32 b2_rosc_a;
- PHY_LE32 reserve1;
- //0x70~0xd0
- PHY_LE32 reserve2[28];
- //0xe0
- PHY_LE32 phyd_version;
- PHY_LE32 phyd_model;
-};
-
-//U3D_B2_PHYD_TOP1
-#define RG_SSUSB_PCIE2_K_EMP (0xf<<28) //31:28
-#define RG_SSUSB_PCIE2_K_FUL (0xf<<24) //27:24
-#define RG_SSUSB_TX_EIDLE_LP_EN (0x1<<17) //17:17
-#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN (0x1<<16) //16:16
-#define RG_SSUSB_SIGDET_EN (0x1<<15) //15:15
-#define RG_SSUSB_FORCE_SIGDET_EN (0x1<<14) //14:14
-#define RG_SSUSB_CLKRX_EN (0x1<<13) //13:13
-#define RG_SSUSB_FORCE_CLKRX_EN (0x1<<12) //12:12
-#define RG_SSUSB_CLKTX_EN (0x1<<11) //11:11
-#define RG_SSUSB_FORCE_CLKTX_EN (0x1<<10) //10:10
-#define RG_SSUSB_CLK_REQ_N_I (0x1<<9) //9:9
-#define RG_SSUSB_FORCE_CLK_REQ_N_I (0x1<<8) //8:8
-#define RG_SSUSB_RATE (0x1<<6) //6:6
-#define RG_SSUSB_FORCE_RATE (0x1<<5) //5:5
-#define RG_SSUSB_PCIE_MODE_SEL (0x1<<4) //4:4
-#define RG_SSUSB_FORCE_PCIE_MODE_SEL (0x1<<3) //3:3
-#define RG_SSUSB_PHY_MODE (0x3<<1) //2:1
-#define RG_SSUSB_FORCE_PHY_MODE (0x1<<0) //0:0
-
-//U3D_B2_PHYD_TOP2
-#define RG_SSUSB_FORCE_IDRV_6DB (0x1<<30) //30:30
-#define RG_SSUSB_IDRV_6DB (0x3f<<24) //29:24
-#define RG_SSUSB_FORCE_IDEM_3P5DB (0x1<<22) //22:22
-#define RG_SSUSB_IDEM_3P5DB (0x3f<<16) //21:16
-#define RG_SSUSB_FORCE_IDRV_3P5DB (0x1<<14) //14:14
-#define RG_SSUSB_IDRV_3P5DB (0x3f<<8) //13:8
-#define RG_SSUSB_FORCE_IDRV_0DB (0x1<<6) //6:6
-#define RG_SSUSB_IDRV_0DB (0x3f<<0) //5:0
-
-//U3D_B2_PHYD_TOP3
-#define RG_SSUSB_TX_BIASI (0x7<<25) //27:25
-#define RG_SSUSB_FORCE_TX_BIASI_EN (0x1<<24) //24:24
-#define RG_SSUSB_TX_BIASI_EN (0x1<<16) //16:16
-#define RG_SSUSB_FORCE_TX_BIASI (0x1<<13) //13:13
-#define RG_SSUSB_FORCE_IDEM_6DB (0x1<<8) //8:8
-#define RG_SSUSB_IDEM_6DB (0x3f<<0) //5:0
-
-//U3D_B2_PHYD_TOP4
-#define RG_SSUSB_G1_CDR_BIC_LTR (0xf<<28) //31:28
-#define RG_SSUSB_G1_CDR_BIC_LTD0 (0xf<<24) //27:24
-#define RG_SSUSB_G1_CDR_BC_LTD1 (0x1f<<16) //20:16
-#define RG_SSUSB_G1_CDR_BC_LTR (0x1f<<8) //12:8
-#define RG_SSUSB_G1_CDR_BC_LTD0 (0x1f<<0) //4:0
-
-//U3D_B2_PHYD_TOP5
-#define RG_SSUSB_G1_CDR_BIR_LTD1 (0x1f<<24) //28:24
-#define RG_SSUSB_G1_CDR_BIR_LTR (0x1f<<16) //20:16
-#define RG_SSUSB_G1_CDR_BIR_LTD0 (0x1f<<8) //12:8
-#define RG_SSUSB_G1_CDR_BIC_LTD1 (0xf<<0) //3:0
-
-//U3D_B2_PHYD_TOP6
-#define RG_SSUSB_G2_CDR_BIC_LTR (0xf<<28) //31:28
-#define RG_SSUSB_G2_CDR_BIC_LTD0 (0xf<<24) //27:24
-#define RG_SSUSB_G2_CDR_BC_LTD1 (0x1f<<16) //20:16
-#define RG_SSUSB_G2_CDR_BC_LTR (0x1f<<8) //12:8
-#define RG_SSUSB_G2_CDR_BC_LTD0 (0x1f<<0) //4:0
-
-//U3D_B2_PHYD_TOP7
-#define RG_SSUSB_G2_CDR_BIR_LTD1 (0x1f<<24) //28:24
-#define RG_SSUSB_G2_CDR_BIR_LTR (0x1f<<16) //20:16
-#define RG_SSUSB_G2_CDR_BIR_LTD0 (0x1f<<8) //12:8
-#define RG_SSUSB_G2_CDR_BIC_LTD1 (0xf<<0) //3:0
-
-//U3D_B2_PHYD_P_SIGDET1
-#define RG_SSUSB_P_SIGDET_FLT_DIS (0x1<<31) //31:31
-#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL (0x7f<<24) //30:24
-#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL (0x7f<<16) //22:16
-#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL (0x7f<<8) //14:8
-#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL (0x7f<<0) //6:0
-
-//U3D_B2_PHYD_P_SIGDET2
-#define RG_SSUSB_P_SIGDET_RX_VAL_S (0x1<<29) //29:29
-#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL (0x1<<28) //28:28
-#define RG_SSUSB_P_SIGDET_L0_EXIT_S (0x1<<27) //27:27
-#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S (0x3<<25) //26:25
-#define RG_SSUSB_P_SIGDET_L0S_EXIT_S (0x1<<24) //24:24
-#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S (0x1<<16) //16:16
-#define RG_SSUSB_P_SIGDET_PRB_SEL (0x1<<10) //10:10
-#define RG_SSUSB_P_SIGDET_BK_SIG_T (0x3<<8) //9:8
-#define RG_SSUSB_P_SIGDET_P2_RXLFPS (0x1<<6) //6:6
-#define RG_SSUSB_P_SIGDET_NON_BK_AD (0x1<<5) //5:5
-#define RG_SSUSB_P_SIGDET_BK_B_RXEQ (0x1<<4) //4:4
-#define RG_SSUSB_P_SIGDET_G2_KO_SEL (0x3<<2) //3:2
-#define RG_SSUSB_P_SIGDET_G1_KO_SEL (0x3<<0) //1:0
-
-//U3D_B2_PHYD_P_SIGDET_CAL1
-#define RG_SSUSB_P_SIGDET_CAL_OFFSET (0x1f<<24) //28:24
-#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET (0x1<<16) //16:16
-#define RG_SSUSB_P_SIGDET_CAL_EN (0x1<<8) //8:8
-#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN (0x1<<3) //3:3
-#define RG_SSUSB_P_SIGDET_FLT_EN (0x1<<2) //2:2
-#define RG_SSUSB_P_SIGDET_SAMPLE_PRD (0x1<<1) //1:1
-#define RG_SSUSB_P_SIGDET_REK (0x1<<0) //0:0
-
-//U3D_B2_PHYD_RXDET1
-#define RG_SSUSB_RXDET_PRB_SEL (0x1<<31) //31:31
-#define RG_SSUSB_FORCE_CMDET (0x1<<30) //30:30
-#define RG_SSUSB_RXDET_EN (0x1<<29) //29:29
-#define RG_SSUSB_FORCE_RXDET_EN (0x1<<28) //28:28
-#define RG_SSUSB_RXDET_K_TWICE (0x1<<27) //27:27
-#define RG_SSUSB_RXDET_STB3_SET (0x1ff<<18) //26:18
-#define RG_SSUSB_RXDET_STB2_SET (0x1ff<<9) //17:9
-#define RG_SSUSB_RXDET_STB1_SET (0x1ff<<0) //8:0
-
-//U3D_B2_PHYD_RXDET2
-#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN (0x1<<31) //31:31
-#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN (0x1<<30) //30:30
-#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN (0x1<<29) //29:29
-#define RG_SSUSB_PDN_T_SEL (0x3<<18) //19:18
-#define RG_SSUSB_RXDET_STB3_SET_P3 (0x1ff<<9) //17:9
-#define RG_SSUSB_RXDET_STB2_SET_P3 (0x1ff<<0) //8:0
-
-//U3D_B2_PHYD_MISC0
-#define RG_SSUSB_FORCE_PLL_DDS_HF_EN (0x1<<22) //22:22
-#define RG_SSUSB_PLL_DDS_HF_EN_MAN (0x1<<21) //21:21
-#define RG_SSUSB_RXLFPS_ENTXDRV (0x1<<20) //20:20
-#define RG_SSUSB_RX_FL_UNLOCKTH (0xf<<16) //19:16
-#define RG_SSUSB_LFPS_PSEL (0x1<<15) //15:15
-#define RG_SSUSB_RX_SIGDET_EN (0x1<<14) //14:14
-#define RG_SSUSB_RX_SIGDET_EN_SEL (0x1<<13) //13:13
-#define RG_SSUSB_RX_PI_CAL_EN (0x1<<12) //12:12
-#define RG_SSUSB_RX_PI_CAL_EN_SEL (0x1<<11) //11:11
-#define RG_SSUSB_P3_CLS_CK_SEL (0x1<<10) //10:10
-#define RG_SSUSB_T2RLB_PSEL (0x3<<8) //9:8
-#define RG_SSUSB_PPCTL_PSEL (0x7<<5) //7:5
-#define RG_SSUSB_PHYD_TX_DATA_INV (0x1<<4) //4:4
-#define RG_SSUSB_BERTLB_PSEL (0x3<<2) //3:2
-#define RG_SSUSB_RETRACK_DIS (0x1<<1) //1:1
-#define RG_SSUSB_PPERRCNT_CLR (0x1<<0) //0:0
-
-//U3D_B2_PHYD_MISC2
-#define RG_SSUSB_FRC_PLL_DDS_PREDIV2 (0x1<<31) //31:31
-#define RG_SSUSB_FRC_PLL_DDS_IADJ (0xf<<27) //30:27
-#define RG_SSUSB_P_SIGDET_125FILTER (0x1<<26) //26:26
-#define RG_SSUSB_P_SIGDET_RST_FILTER (0x1<<25) //25:25
-#define RG_SSUSB_P_SIGDET_EID_USE_RAW (0x1<<24) //24:24
-#define RG_SSUSB_P_SIGDET_LTD_USE_RAW (0x1<<23) //23:23
-#define RG_SSUSB_EIDLE_BF_RXDET (0x1<<22) //22:22
-#define RG_SSUSB_EIDLE_LP_STBCYC (0x1ff<<13) //21:13
-#define RG_SSUSB_TX_EIDLE_LP_POSTDLY (0x3f<<7) //12:7
-#define RG_SSUSB_TX_EIDLE_LP_PREDLY (0x3f<<1) //6:1
-#define RG_SSUSB_TX_EIDLE_LP_EN_ADV (0x1<<0) //0:0
-
-//U3D_B2_PHYD_MISC3
-#define RGS_SSUSB_DDS_CALIB_C_STATE (0x7<<16) //18:16
-#define RGS_SSUSB_PPERRCNT (0xffff<<0) //15:0
-
-//U3D_B2_ROSC_0
-#define RG_SSUSB_RING_OSC_CNTEND (0x1ff<<23) //31:23
-#define RG_SSUSB_XTAL_OSC_CNTEND (0x7f<<16) //22:16
-#define RG_SSUSB_RING_OSC_EN (0x1<<3) //3:3
-#define RG_SSUSB_RING_OSC_FORCE_EN (0x1<<2) //2:2
-#define RG_SSUSB_FRC_RING_BYPASS_DET (0x1<<1) //1:1
-#define RG_SSUSB_RING_BYPASS_DET (0x1<<0) //0:0
-
-//U3D_B2_ROSC_1
-#define RG_SSUSB_RING_OSC_FRC_P3 (0x1<<20) //20:20
-#define RG_SSUSB_RING_OSC_P3 (0x1<<19) //19:19
-#define RG_SSUSB_RING_OSC_FRC_RECAL (0x3<<17) //18:17
-#define RG_SSUSB_RING_OSC_RECAL (0x1<<16) //16:16
-#define RG_SSUSB_RING_OSC_SEL (0xff<<8) //15:8
-#define RG_SSUSB_RING_OSC_FRC_SEL (0x1<<0) //0:0
-
-//U3D_B2_ROSC_2
-#define RG_SSUSB_RING_DET_STRCYC2 (0xffff<<16) //31:16
-#define RG_SSUSB_RING_DET_STRCYC1 (0xffff<<0) //15:0
-
-//U3D_B2_ROSC_3
-#define RG_SSUSB_RING_DET_DETWIN1 (0xffff<<16) //31:16
-#define RG_SSUSB_RING_DET_STRCYC3 (0xffff<<0) //15:0
-
-//U3D_B2_ROSC_4
-#define RG_SSUSB_RING_DET_DETWIN3 (0xffff<<16) //31:16
-#define RG_SSUSB_RING_DET_DETWIN2 (0xffff<<0) //15:0
-
-//U3D_B2_ROSC_5
-#define RG_SSUSB_RING_DET_LBOND1 (0xffff<<16) //31:16
-#define RG_SSUSB_RING_DET_UBOND1 (0xffff<<0) //15:0
-
-//U3D_B2_ROSC_6
-#define RG_SSUSB_RING_DET_LBOND2 (0xffff<<16) //31:16
-#define RG_SSUSB_RING_DET_UBOND2 (0xffff<<0) //15:0
-
-//U3D_B2_ROSC_7
-#define RG_SSUSB_RING_DET_LBOND3 (0xffff<<16) //31:16
-#define RG_SSUSB_RING_DET_UBOND3 (0xffff<<0) //15:0
-
-//U3D_B2_ROSC_8
-#define RG_SSUSB_RING_RESERVE (0xffff<<16) //31:16
-#define RG_SSUSB_ROSC_PROB_SEL (0xf<<2) //5:2
-#define RG_SSUSB_RING_FREQMETER_EN (0x1<<1) //1:1
-#define RG_SSUSB_RING_DET_BPS_UBOND (0x1<<0) //0:0
-
-//U3D_B2_ROSC_9
-#define RGS_FM_RING_CNT (0xffff<<16) //31:16
-#define RGS_SSUSB_RING_OSC_STATE (0x3<<10) //11:10
-#define RGS_SSUSB_RING_OSC_STABLE (0x1<<9) //9:9
-#define RGS_SSUSB_RING_OSC_CAL_FAIL (0x1<<8) //8:8
-#define RGS_SSUSB_RING_OSC_CAL (0xff<<0) //7:0
-
-//U3D_B2_ROSC_A
-#define RGS_SSUSB_ROSC_PROB_OUT (0xff<<0) //7:0
-
-//U3D_PHYD_VERSION
-#define RGS_SSUSB_PHYD_VERSION (0xffffffff<<0) //31:0
-
-//U3D_PHYD_MODEL
-#define RGS_SSUSB_PHYD_MODEL (0xffffffff<<0) //31:0
-
-
-/* OFFSET */
-
-//U3D_B2_PHYD_TOP1
-#define RG_SSUSB_PCIE2_K_EMP_OFST (28)
-#define RG_SSUSB_PCIE2_K_FUL_OFST (24)
-#define RG_SSUSB_TX_EIDLE_LP_EN_OFST (17)
-#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST (16)
-#define RG_SSUSB_SIGDET_EN_OFST (15)
-#define RG_SSUSB_FORCE_SIGDET_EN_OFST (14)
-#define RG_SSUSB_CLKRX_EN_OFST (13)
-#define RG_SSUSB_FORCE_CLKRX_EN_OFST (12)
-#define RG_SSUSB_CLKTX_EN_OFST (11)
-#define RG_SSUSB_FORCE_CLKTX_EN_OFST (10)
-#define RG_SSUSB_CLK_REQ_N_I_OFST (9)
-#define RG_SSUSB_FORCE_CLK_REQ_N_I_OFST (8)
-#define RG_SSUSB_RATE_OFST (6)
-#define RG_SSUSB_FORCE_RATE_OFST (5)
-#define RG_SSUSB_PCIE_MODE_SEL_OFST (4)
-#define RG_SSUSB_FORCE_PCIE_MODE_SEL_OFST (3)
-#define RG_SSUSB_PHY_MODE_OFST (1)
-#define RG_SSUSB_FORCE_PHY_MODE_OFST (0)
-
-//U3D_B2_PHYD_TOP2
-#define RG_SSUSB_FORCE_IDRV_6DB_OFST (30)
-#define RG_SSUSB_IDRV_6DB_OFST (24)
-#define RG_SSUSB_FORCE_IDEM_3P5DB_OFST (22)
-#define RG_SSUSB_IDEM_3P5DB_OFST (16)
-#define RG_SSUSB_FORCE_IDRV_3P5DB_OFST (14)
-#define RG_SSUSB_IDRV_3P5DB_OFST (8)
-#define RG_SSUSB_FORCE_IDRV_0DB_OFST (6)
-#define RG_SSUSB_IDRV_0DB_OFST (0)
-
-//U3D_B2_PHYD_TOP3
-#define RG_SSUSB_TX_BIASI_OFST (25)
-#define RG_SSUSB_FORCE_TX_BIASI_EN_OFST (24)
-#define RG_SSUSB_TX_BIASI_EN_OFST (16)
-#define RG_SSUSB_FORCE_TX_BIASI_OFST (13)
-#define RG_SSUSB_FORCE_IDEM_6DB_OFST (8)
-#define RG_SSUSB_IDEM_6DB_OFST (0)
-
-//U3D_B2_PHYD_TOP4
-#define RG_SSUSB_G1_CDR_BIC_LTR_OFST (28)
-#define RG_SSUSB_G1_CDR_BIC_LTD0_OFST (24)
-#define RG_SSUSB_G1_CDR_BC_LTD1_OFST (16)
-#define RG_SSUSB_G1_CDR_BC_LTR_OFST (8)
-#define RG_SSUSB_G1_CDR_BC_LTD0_OFST (0)
-
-//U3D_B2_PHYD_TOP5
-#define RG_SSUSB_G1_CDR_BIR_LTD1_OFST (24)
-#define RG_SSUSB_G1_CDR_BIR_LTR_OFST (16)
-#define RG_SSUSB_G1_CDR_BIR_LTD0_OFST (8)
-#define RG_SSUSB_G1_CDR_BIC_LTD1_OFST (0)
-
-//U3D_B2_PHYD_TOP6
-#define RG_SSUSB_G2_CDR_BIC_LTR_OFST (28)
-#define RG_SSUSB_G2_CDR_BIC_LTD0_OFST (24)
-#define RG_SSUSB_G2_CDR_BC_LTD1_OFST (16)
-#define RG_SSUSB_G2_CDR_BC_LTR_OFST (8)
-#define RG_SSUSB_G2_CDR_BC_LTD0_OFST (0)
-
-//U3D_B2_PHYD_TOP7
-#define RG_SSUSB_G2_CDR_BIR_LTD1_OFST (24)
-#define RG_SSUSB_G2_CDR_BIR_LTR_OFST (16)
-#define RG_SSUSB_G2_CDR_BIR_LTD0_OFST (8)
-#define RG_SSUSB_G2_CDR_BIC_LTD1_OFST (0)
-
-//U3D_B2_PHYD_P_SIGDET1
-#define RG_SSUSB_P_SIGDET_FLT_DIS_OFST (31)
-#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL_OFST (24)
-#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL_OFST (16)
-#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL_OFST (8)
-#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL_OFST (0)
-
-//U3D_B2_PHYD_P_SIGDET2
-#define RG_SSUSB_P_SIGDET_RX_VAL_S_OFST (29)
-#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL_OFST (28)
-#define RG_SSUSB_P_SIGDET_L0_EXIT_S_OFST (27)
-#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S_OFST (25)
-#define RG_SSUSB_P_SIGDET_L0S_EXIT_S_OFST (24)
-#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S_OFST (16)
-#define RG_SSUSB_P_SIGDET_PRB_SEL_OFST (10)
-#define RG_SSUSB_P_SIGDET_BK_SIG_T_OFST (8)
-#define RG_SSUSB_P_SIGDET_P2_RXLFPS_OFST (6)
-#define RG_SSUSB_P_SIGDET_NON_BK_AD_OFST (5)
-#define RG_SSUSB_P_SIGDET_BK_B_RXEQ_OFST (4)
-#define RG_SSUSB_P_SIGDET_G2_KO_SEL_OFST (2)
-#define RG_SSUSB_P_SIGDET_G1_KO_SEL_OFST (0)
-
-//U3D_B2_PHYD_P_SIGDET_CAL1
-#define RG_SSUSB_P_SIGDET_CAL_OFFSET_OFST (24)
-#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET_OFST (16)
-#define RG_SSUSB_P_SIGDET_CAL_EN_OFST (8)
-#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN_OFST (3)
-#define RG_SSUSB_P_SIGDET_FLT_EN_OFST (2)
-#define RG_SSUSB_P_SIGDET_SAMPLE_PRD_OFST (1)
-#define RG_SSUSB_P_SIGDET_REK_OFST (0)
-
-//U3D_B2_PHYD_RXDET1
-#define RG_SSUSB_RXDET_PRB_SEL_OFST (31)
-#define RG_SSUSB_FORCE_CMDET_OFST (30)
-#define RG_SSUSB_RXDET_EN_OFST (29)
-#define RG_SSUSB_FORCE_RXDET_EN_OFST (28)
-#define RG_SSUSB_RXDET_K_TWICE_OFST (27)
-#define RG_SSUSB_RXDET_STB3_SET_OFST (18)
-#define RG_SSUSB_RXDET_STB2_SET_OFST (9)
-#define RG_SSUSB_RXDET_STB1_SET_OFST (0)
-
-//U3D_B2_PHYD_RXDET2
-#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN_OFST (31)
-#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN_OFST (30)
-#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN_OFST (29)
-#define RG_SSUSB_PDN_T_SEL_OFST (18)
-#define RG_SSUSB_RXDET_STB3_SET_P3_OFST (9)
-#define RG_SSUSB_RXDET_STB2_SET_P3_OFST (0)
-
-//U3D_B2_PHYD_MISC0
-#define RG_SSUSB_FORCE_PLL_DDS_HF_EN_OFST (22)
-#define RG_SSUSB_PLL_DDS_HF_EN_MAN_OFST (21)
-#define RG_SSUSB_RXLFPS_ENTXDRV_OFST (20)
-#define RG_SSUSB_RX_FL_UNLOCKTH_OFST (16)
-#define RG_SSUSB_LFPS_PSEL_OFST (15)
-#define RG_SSUSB_RX_SIGDET_EN_OFST (14)
-#define RG_SSUSB_RX_SIGDET_EN_SEL_OFST (13)
-#define RG_SSUSB_RX_PI_CAL_EN_OFST (12)
-#define RG_SSUSB_RX_PI_CAL_EN_SEL_OFST (11)
-#define RG_SSUSB_P3_CLS_CK_SEL_OFST (10)
-#define RG_SSUSB_T2RLB_PSEL_OFST (8)
-#define RG_SSUSB_PPCTL_PSEL_OFST (5)
-#define RG_SSUSB_PHYD_TX_DATA_INV_OFST (4)
-#define RG_SSUSB_BERTLB_PSEL_OFST (2)
-#define RG_SSUSB_RETRACK_DIS_OFST (1)
-#define RG_SSUSB_PPERRCNT_CLR_OFST (0)
-
-//U3D_B2_PHYD_MISC2
-#define RG_SSUSB_FRC_PLL_DDS_PREDIV2_OFST (31)
-#define RG_SSUSB_FRC_PLL_DDS_IADJ_OFST (27)
-#define RG_SSUSB_P_SIGDET_125FILTER_OFST (26)
-#define RG_SSUSB_P_SIGDET_RST_FILTER_OFST (25)
-#define RG_SSUSB_P_SIGDET_EID_USE_RAW_OFST (24)
-#define RG_SSUSB_P_SIGDET_LTD_USE_RAW_OFST (23)
-#define RG_SSUSB_EIDLE_BF_RXDET_OFST (22)
-#define RG_SSUSB_EIDLE_LP_STBCYC_OFST (13)
-#define RG_SSUSB_TX_EIDLE_LP_POSTDLY_OFST (7)
-#define RG_SSUSB_TX_EIDLE_LP_PREDLY_OFST (1)
-#define RG_SSUSB_TX_EIDLE_LP_EN_ADV_OFST (0)
-
-//U3D_B2_PHYD_MISC3
-#define RGS_SSUSB_DDS_CALIB_C_STATE_OFST (16)
-#define RGS_SSUSB_PPERRCNT_OFST (0)
-
-//U3D_B2_ROSC_0
-#define RG_SSUSB_RING_OSC_CNTEND_OFST (23)
-#define RG_SSUSB_XTAL_OSC_CNTEND_OFST (16)
-#define RG_SSUSB_RING_OSC_EN_OFST (3)
-#define RG_SSUSB_RING_OSC_FORCE_EN_OFST (2)
-#define RG_SSUSB_FRC_RING_BYPASS_DET_OFST (1)
-#define RG_SSUSB_RING_BYPASS_DET_OFST (0)
-
-//U3D_B2_ROSC_1
-#define RG_SSUSB_RING_OSC_FRC_P3_OFST (20)
-#define RG_SSUSB_RING_OSC_P3_OFST (19)
-#define RG_SSUSB_RING_OSC_FRC_RECAL_OFST (17)
-#define RG_SSUSB_RING_OSC_RECAL_OFST (16)
-#define RG_SSUSB_RING_OSC_SEL_OFST (8)
-#define RG_SSUSB_RING_OSC_FRC_SEL_OFST (0)
-
-//U3D_B2_ROSC_2
-#define RG_SSUSB_RING_DET_STRCYC2_OFST (16)
-#define RG_SSUSB_RING_DET_STRCYC1_OFST (0)
-
-//U3D_B2_ROSC_3
-#define RG_SSUSB_RING_DET_DETWIN1_OFST (16)
-#define RG_SSUSB_RING_DET_STRCYC3_OFST (0)
-
-//U3D_B2_ROSC_4
-#define RG_SSUSB_RING_DET_DETWIN3_OFST (16)
-#define RG_SSUSB_RING_DET_DETWIN2_OFST (0)
-
-//U3D_B2_ROSC_5
-#define RG_SSUSB_RING_DET_LBOND1_OFST (16)
-#define RG_SSUSB_RING_DET_UBOND1_OFST (0)
-
-//U3D_B2_ROSC_6
-#define RG_SSUSB_RING_DET_LBOND2_OFST (16)
-#define RG_SSUSB_RING_DET_UBOND2_OFST (0)
-
-//U3D_B2_ROSC_7
-#define RG_SSUSB_RING_DET_LBOND3_OFST (16)
-#define RG_SSUSB_RING_DET_UBOND3_OFST (0)
-
-//U3D_B2_ROSC_8
-#define RG_SSUSB_RING_RESERVE_OFST (16)
-#define RG_SSUSB_ROSC_PROB_SEL_OFST (2)
-#define RG_SSUSB_RING_FREQMETER_EN_OFST (1)
-#define RG_SSUSB_RING_DET_BPS_UBOND_OFST (0)
-
-//U3D_B2_ROSC_9
-#define RGS_FM_RING_CNT_OFST (16)
-#define RGS_SSUSB_RING_OSC_STATE_OFST (10)
-#define RGS_SSUSB_RING_OSC_STABLE_OFST (9)
-#define RGS_SSUSB_RING_OSC_CAL_FAIL_OFST (8)
-#define RGS_SSUSB_RING_OSC_CAL_OFST (0)
-
-//U3D_B2_ROSC_A
-#define RGS_SSUSB_ROSC_PROB_OUT_OFST (0)
-
-//U3D_PHYD_VERSION
-#define RGS_SSUSB_PHYD_VERSION_OFST (0)
-
-//U3D_PHYD_MODEL
-#define RGS_SSUSB_PHYD_MODEL_OFST (0)
-
-
-///////////////////////////////////////////////////////////////////////////////
-
-struct sifslv_chip_reg {
- PHY_LE32 xtalbias;
- PHY_LE32 syspll1;
- PHY_LE32 gpio_ctla;
- PHY_LE32 gpio_ctlb;
- PHY_LE32 gpio_ctlc;
-};
-
-//U3D_GPIO_CTLA
-#define RG_C60802_GPIO_CTLA (0xffffffff<<0) //31:0
-
-//U3D_GPIO_CTLB
-#define RG_C60802_GPIO_CTLB (0xffffffff<<0) //31:0
-
-//U3D_GPIO_CTLC
-#define RG_C60802_GPIO_CTLC (0xffffffff<<0) //31:0
-
-/* OFFSET */
-
-//U3D_GPIO_CTLA
-#define RG_C60802_GPIO_CTLA_OFST (0)
-
-//U3D_GPIO_CTLB
-#define RG_C60802_GPIO_CTLB_OFST (0)
-
-//U3D_GPIO_CTLC
-#define RG_C60802_GPIO_CTLC_OFST (0)
-
-///////////////////////////////////////////////////////////////////////////////
-
-struct sifslv_fm_feg {
- //0x0
- PHY_LE32 fmcr0;
- PHY_LE32 fmcr1;
- PHY_LE32 fmcr2;
- PHY_LE32 fmmonr0;
- //0x10
- PHY_LE32 fmmonr1;
-};
-
-//U3D_FMCR0
-#define RG_LOCKTH (0xf<<28) //31:28
-#define RG_MONCLK_SEL (0x3<<26) //27:26
-#define RG_FM_MODE (0x1<<25) //25:25
-#define RG_FREQDET_EN (0x1<<24) //24:24
-#define RG_CYCLECNT (0xffffff<<0) //23:0
-
-//U3D_FMCR1
-#define RG_TARGET (0xffffffff<<0) //31:0
-
-//U3D_FMCR2
-#define RG_OFFSET (0xffffffff<<0) //31:0
-
-//U3D_FMMONR0
-#define USB_FM_OUT (0xffffffff<<0) //31:0
-
-//U3D_FMMONR1
-#define RG_MONCLK_SEL_3 (0x1<<9) //9:9
-#define RG_FRCK_EN (0x1<<8) //8:8
-#define USBPLL_LOCK (0x1<<1) //1:1
-#define USB_FM_VLD (0x1<<0) //0:0
-
-
-/* OFFSET */
-
-//U3D_FMCR0
-#define RG_LOCKTH_OFST (28)
-#define RG_MONCLK_SEL_OFST (26)
-#define RG_FM_MODE_OFST (25)
-#define RG_FREQDET_EN_OFST (24)
-#define RG_CYCLECNT_OFST (0)
-
-//U3D_FMCR1
-#define RG_TARGET_OFST (0)
-
-//U3D_FMCR2
-#define RG_OFFSET_OFST (0)
-
-//U3D_FMMONR0
-#define USB_FM_OUT_OFST (0)
-
-//U3D_FMMONR1
-#define RG_MONCLK_SEL_3_OFST (9)
-#define RG_FRCK_EN_OFST (8)
-#define USBPLL_LOCK_OFST (1)
-#define USB_FM_VLD_OFST (0)
-
-
-///////////////////////////////////////////////////////////////////////////////
-
-PHY_INT32 phy_init(struct u3phy_info *info);
-PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
-PHY_INT32 eyescan_init(struct u3phy_info *info);
-PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
- , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
-PHY_INT32 u2_save_cur_en(struct u3phy_info *info);
-PHY_INT32 u2_save_cur_re(struct u3phy_info *info);
-PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info);
-
-#endif
-#endif
diff --git a/target/linux/ramips/files/drivers/usb/host/mtk-phy-ahb.c b/target/linux/ramips/files/drivers/usb/host/mtk-phy-ahb.c
deleted file mode 100644
index ebaf7c8b15..0000000000
--- a/target/linux/ramips/files/drivers/usb/host/mtk-phy-ahb.c
+++ /dev/null
@@ -1,58 +0,0 @@
-#include "mtk-phy.h"
-#ifdef CONFIG_U3D_HAL_SUPPORT
-#include "mu3d_hal_osal.h"
-#endif
-
-#ifdef CONFIG_U3_PHY_AHB_SUPPORT
-#include <linux/gfp.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-
-#ifndef CONFIG_U3D_HAL_SUPPORT
-#define os_writel(addr,data) {\
- (*((volatile PHY_UINT32*)(addr)) = data);\
- }
-#define os_readl(addr) *((volatile PHY_UINT32*)(addr))
-#define os_writelmsk(addr, data, msk) \
- { os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk)))); \
- }
-#define os_setmsk(addr, msk) \
- { os_writel(addr, os_readl(addr) | msk); \
- }
-#define os_clrmsk(addr, msk) \
- { os_writel(addr, os_readl(addr) &~ msk); \
- }
-/*msk the data first, then umsk with the umsk.*/
-#define os_writelmskumsk(addr, data, msk, umsk) \
-{\
- os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk))) & (umsk));\
-}
-
-#endif
-
-PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data)
-{
- os_writel(addr, data);
-
- return 0;
-}
-
-PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr)
-{
- return os_readl(addr);
-}
-
-PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data)
-{
- os_writelmsk(addr&0xfffffffc, data<<((addr%4)*8), 0xff<<((addr%4)*8));
-
- return 0;
-}
-
-PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr)
-{
- return ((os_readl(addr)>>((addr%4)*8))&0xff);
-}
-
-#endif
-
diff --git a/target/linux/ramips/files/drivers/usb/host/mtk-phy.c b/target/linux/ramips/files/drivers/usb/host/mtk-phy.c
deleted file mode 100644
index 7ed8f015b8..0000000000
--- a/target/linux/ramips/files/drivers/usb/host/mtk-phy.c
+++ /dev/null
@@ -1,102 +0,0 @@
-#include <linux/gfp.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#define U3_PHY_LIB
-#include "mtk-phy.h"
-#ifdef CONFIG_PROJECT_7621
-#include "mtk-phy-7621.h"
-#endif
-#ifdef CONFIG_PROJECT_PHY
-static struct u3phy_operator project_operators = {
- .init = phy_init,
- .change_pipe_phase = phy_change_pipe_phase,
- .eyescan_init = eyescan_init,
- .eyescan = phy_eyescan,
- .u2_slew_rate_calibration = u2_slew_rate_calibration,
-};
-#endif
-
-
-PHY_INT32 u3phy_init(){
-#ifndef CONFIG_PROJECT_PHY
- PHY_INT32 u3phy_version;
-#endif
-
- if(u3phy != NULL){
- return PHY_TRUE;
- }
-
- u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
-#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
-#endif
-#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
- u3phy->phyd_version_addr = 0x2000e4;
-#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- u3phy_p1->phyd_version_addr = 0x2000e4;
-#endif
-#else
- u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
-#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4;
-#endif
-#endif
-
-#ifdef CONFIG_PROJECT_PHY
-
- u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE;
- u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE;
- u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE;
- u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE;
- u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE;
- u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
- u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
- u3phy_ops = &project_operators;
-
-#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1;
- u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1;
- u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1;
- u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1;
- u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1;
- u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
- u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
-#endif
-#endif
-
- return PHY_TRUE;
-}
-
-PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
- PHY_INT8 cur_value;
- PHY_INT8 new_value;
-
- cur_value = U3PhyReadReg8(addr);
- new_value = (cur_value & (~mask)) | (value << offset);
- //udelay(i2cdelayus);
- U3PhyWriteReg8(addr, new_value);
- return PHY_TRUE;
-}
-
-PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
- PHY_INT32 cur_value;
- PHY_INT32 new_value;
-
- cur_value = U3PhyReadReg32(addr);
- new_value = (cur_value & (~mask)) | ((value << offset) & mask);
- U3PhyWriteReg32(addr, new_value);
- //DRV_MDELAY(100);
-
- return PHY_TRUE;
-}
-
-PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){
-
- return ((U3PhyReadReg8(addr) & mask) >> offset);
-}
-
-PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){
-
- return ((U3PhyReadReg32(addr) & mask) >> offset);
-}
-
diff --git a/target/linux/ramips/files/drivers/usb/host/mtk-phy.h b/target/linux/ramips/files/drivers/usb/host/mtk-phy.h
deleted file mode 100644
index 07ed410412..0000000000
--- a/target/linux/ramips/files/drivers/usb/host/mtk-phy.h
+++ /dev/null
@@ -1,179 +0,0 @@
-#ifndef __MTK_PHY_NEW_H
-#define __MTK_PHY_NEW_H
-
-//#define CONFIG_U3D_HAL_SUPPORT
-
-/* include system library */
-#include <linux/gfp.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-
-/* Choose PHY R/W implementation */
-//#define CONFIG_U3_PHY_GPIO_SUPPORT //SW I2C implemented by GPIO
-#define CONFIG_U3_PHY_AHB_SUPPORT //AHB, only on SoC
-
-/* Choose PHY version */
-//Select your project by defining one of the followings
-#define CONFIG_PROJECT_7621 //7621
-#define CONFIG_PROJECT_PHY
-
-/* BASE ADDRESS DEFINE, should define this on ASIC */
-#define PHY_BASE 0xBE1D0000
-#define SIFSLV_FM_FEG_BASE (PHY_BASE+0x100)
-#define SIFSLV_CHIP_BASE (PHY_BASE+0x700)
-#define U2_PHY_BASE (PHY_BASE+0x800)
-#define U3_PHYD_BASE (PHY_BASE+0x900)
-#define U3_PHYD_B2_BASE (PHY_BASE+0xa00)
-#define U3_PHYA_BASE (PHY_BASE+0xb00)
-#define U3_PHYA_DA_BASE (PHY_BASE+0xc00)
-
-#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-#define SIFSLV_FM_FEG_BASE_P1 (PHY_BASE+0x100)
-#define SIFSLV_CHIP_BASE_P1 (PHY_BASE+0x700)
-#define U2_PHY_BASE_P1 (PHY_BASE+0x1000)
-#define U3_PHYD_BASE_P1 (PHY_BASE+0x1100)
-#define U3_PHYD_B2_BASE_P1 (PHY_BASE+0x1200)
-#define U3_PHYA_BASE_P1 (PHY_BASE+0x1300)
-#define U3_PHYA_DA_BASE_P1 (PHY_BASE+0x1400)
-#endif
-
-/*
-
-0x00000100 MODULE ssusb_sifslv_fmreg ssusb_sifslv_fmreg
-0x00000700 MODULE ssusb_sifslv_ippc ssusb_sifslv_ippc
-0x00000800 MODULE ssusb_sifslv_u2phy_com ssusb_sifslv_u2_phy_com_T28
-0x00000900 MODULE ssusb_sifslv_u3phyd ssusb_sifslv_u3phyd_T28
-0x00000a00 MODULE ssusb_sifslv_u3phyd_bank2 ssusb_sifslv_u3phyd_bank2_T28
-0x00000b00 MODULE ssusb_sifslv_u3phya ssusb_sifslv_u3phya_T28
-0x00000c00 MODULE ssusb_sifslv_u3phya_da ssusb_sifslv_u3phya_da_T28
-*/
-
-
-/* TYPE DEFINE */
-typedef unsigned int PHY_UINT32;
-typedef int PHY_INT32;
-typedef unsigned short PHY_UINT16;
-typedef short PHY_INT16;
-typedef unsigned char PHY_UINT8;
-typedef char PHY_INT8;
-
-typedef PHY_UINT32 __bitwise PHY_LE32;
-
-/* CONSTANT DEFINE */
-#define PHY_FALSE 0
-#define PHY_TRUE 1
-
-/* MACRO DEFINE */
-#define DRV_WriteReg32(addr,data) ((*(volatile PHY_UINT32 *)(addr)) = (unsigned long)(data))
-#define DRV_Reg32(addr) (*(volatile PHY_UINT32 *)(addr))
-
-#define DRV_MDELAY mdelay
-#define DRV_MSLEEP msleep
-#define DRV_UDELAY udelay
-#define DRV_USLEEP usleep
-
-/* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
-PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data);
-PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr);
-PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data);
-PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr);
-
-/* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
-PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
-PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
-PHY_INT32 U3PhyReadField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
-PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
-
-struct u3phy_info {
- PHY_INT32 phy_version;
- PHY_INT32 phyd_version_addr;
-
-#ifdef CONFIG_PROJECT_PHY
- struct u2phy_reg *u2phy_regs;
- struct u3phya_reg *u3phya_regs;
- struct u3phya_da_reg *u3phya_da_regs;
- struct u3phyd_reg *u3phyd_regs;
- struct u3phyd_bank2_reg *u3phyd_bank2_regs;
- struct sifslv_chip_reg *sifslv_chip_regs;
- struct sifslv_fm_feg *sifslv_fm_regs;
-#endif
-};
-
-struct u3phy_operator {
- PHY_INT32 (*init) (struct u3phy_info *info);
- PHY_INT32 (*change_pipe_phase) (struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
- PHY_INT32 (*eyescan_init) (struct u3phy_info *info);
- PHY_INT32 (*eyescan) (struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
- PHY_INT32 (*u2_save_current_entry) (struct u3phy_info *info);
- PHY_INT32 (*u2_save_current_recovery) (struct u3phy_info *info);
- PHY_INT32 (*u2_slew_rate_calibration) (struct u3phy_info *info);
-};
-
-#ifdef U3_PHY_LIB
-#define AUTOEXT
-#else
-#define AUTOEXT extern
-#endif
-
-AUTOEXT struct u3phy_info *u3phy;
-AUTOEXT struct u3phy_info *u3phy_p1;
-AUTOEXT struct u3phy_operator *u3phy_ops;
-
-/*********eye scan required*********/
-
-#define LO_BYTE(x) ((PHY_UINT8)((x) & 0xFF))
-#define HI_BYTE(x) ((PHY_UINT8)(((x) & 0xFF00) >> 8))
-
-typedef enum
-{
- SCAN_UP,
- SCAN_DN
-} enumScanDir;
-
-struct strucScanRegion
-{
- PHY_INT8 bX_tl;
- PHY_INT8 bY_tl;
- PHY_INT8 bX_br;
- PHY_INT8 bY_br;
- PHY_INT8 bDeltaX;
- PHY_INT8 bDeltaY;
-};
-
-struct strucTestCycle
-{
- PHY_UINT16 wEyeCnt;
- PHY_INT8 bNumOfEyeCnt;
- PHY_INT8 bPICalEn;
- PHY_INT8 bNumOfIgnoreCnt;
-};
-
-#define ERRCNT_MAX 128
-#define CYCLE_COUNT_MAX 15
-
-/// the map resolution is 128 x 128 pts
-#define MAX_X 127
-#define MAX_Y 127
-#define MIN_X 0
-#define MIN_Y 0
-
-PHY_INT32 u3phy_init(void);
-
-AUTOEXT struct strucScanRegion _rEye1;
-AUTOEXT struct strucScanRegion _rEye2;
-AUTOEXT struct strucTestCycle _rTestCycle;
-AUTOEXT PHY_UINT8 _bXcurr;
-AUTOEXT PHY_UINT8 _bYcurr;
-AUTOEXT enumScanDir _eScanDir;
-AUTOEXT PHY_INT8 _fgXChged;
-AUTOEXT PHY_INT8 _bPIResult;
-/* use local variable instead to save memory use */
-#if 0
-AUTOEXT PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
-AUTOEXT PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
-#endif
-
-/***********************************/
-#endif
-
diff --git a/target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.c b/target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.c
deleted file mode 100644
index 9d9352678e..0000000000
--- a/target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.c
+++ /dev/null
@@ -1,115 +0,0 @@
-#include "xhci-mtk.h"
-#include "xhci-mtk-power.h"
-#include "xhci.h"
-#include <linux/kernel.h> /* printk() */
-#include <linux/slab.h>
-#include <linux/delay.h>
-
-static int g_num_u3_port;
-static int g_num_u2_port;
-
-
-void enableXhciAllPortPower(struct xhci_hcd *xhci){
- int i;
- u32 port_id, temp;
- u32 __iomem *addr;
-
- g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
- g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
-
- for(i=1; i<=g_num_u3_port; i++){
- port_id=i;
- addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
- temp = xhci_readl(xhci, addr);
- temp = xhci_port_state_to_neutral(temp);
- temp |= PORT_POWER;
- xhci_writel(xhci, temp, addr);
- }
- for(i=1; i<=g_num_u2_port; i++){
- port_id=i+g_num_u3_port;
- addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
- temp = xhci_readl(xhci, addr);
- temp = xhci_port_state_to_neutral(temp);
- temp |= PORT_POWER;
- xhci_writel(xhci, temp, addr);
- }
-}
-
-void enableAllClockPower(){
-
- int i;
- u32 temp;
-
- g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
- g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
-
- //2. Enable xHC
- writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
- writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
- writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
-
- //1. Enable target ports
- for(i=0; i<g_num_u3_port; i++){
- temp = readl(SSUSB_U3_CTRL(i));
- temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
- writel(temp, SSUSB_U3_CTRL(i));
- }
- for(i=0; i<g_num_u2_port; i++){
- temp = readl(SSUSB_U2_CTRL(i));
- temp = temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
- writel(temp, SSUSB_U2_CTRL(i));
- }
- msleep(100);
-}
-
-
-//(X)disable clock/power of a port
-//(X)if all ports are disabled, disable IP ctrl power
-//disable all ports and IP clock/power, this is just mention HW that the power/clock of port
-//and IP could be disable if suspended.
-//If doesn't not disable all ports at first, the IP clock/power will never be disabled
-//(some U2 and U3 ports are binded to the same connection, that is, they will never enter suspend at the same time
-//port_index: port number
-//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
-void disablePortClockPower(void){
- int i;
- u32 temp;
-
- g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
- g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
-
- for(i=0; i<g_num_u3_port; i++){
- temp = readl(SSUSB_U3_CTRL(i));
- temp = temp | (SSUSB_U3_PORT_PDN);
- writel(temp, SSUSB_U3_CTRL(i));
- }
- for(i=0; i<g_num_u2_port; i++){
- temp = readl(SSUSB_U2_CTRL(i));
- temp = temp | (SSUSB_U2_PORT_PDN);
- writel(temp, SSUSB_U2_CTRL(i));
- }
- writel(readl(SSUSB_IP_PW_CTRL_1) | (SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
-}
-
-//if IP ctrl power is disabled, enable it
-//enable clock/power of a port
-//port_index: port number
-//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
-void enablePortClockPower(int port_index, int port_rev){
- int i;
- u32 temp;
-
- writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
-
- if(port_rev == 0x3){
- temp = readl(SSUSB_U3_CTRL(port_index));
- temp = temp & (~SSUSB_U3_PORT_PDN);
- writel(temp, SSUSB_U3_CTRL(port_index));
- }
- else if(port_rev == 0x2){
- temp = readl(SSUSB_U2_CTRL(port_index));
- temp = temp & (~SSUSB_U2_PORT_PDN);
- writel(temp, SSUSB_U2_CTRL(port_index));
- }
-}
-
diff --git a/target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.h b/target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.h
deleted file mode 100644
index e57c243f56..0000000000
--- a/target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _XHCI_MTK_POWER_H
-#define _XHCI_MTK_POWER_H
-
-#include <linux/usb.h>
-#include "xhci.h"
-#include "xhci-mtk.h"
-
-void enableXhciAllPortPower(struct xhci_hcd *xhci);
-void enableAllClockPower(void);
-void disablePortClockPower(void);
-void enablePortClockPower(int port_index, int port_rev);
-
-#endif
diff --git a/target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.c b/target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.c
deleted file mode 100644
index bf6a8bdc19..0000000000
--- a/target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.c
+++ /dev/null
@@ -1,608 +0,0 @@
-#include "xhci-mtk-scheduler.h"
-#include <linux/kernel.h> /* printk() */
-
-static struct sch_ep **ss_out_eps[MAX_EP_NUM];
-static struct sch_ep **ss_in_eps[MAX_EP_NUM];
-static struct sch_ep **hs_eps[MAX_EP_NUM]; //including tt isoc
-static struct sch_ep **tt_intr_eps[MAX_EP_NUM];
-
-
-int mtk_xhci_scheduler_init(void){
- int i;
-
- for(i=0; i<MAX_EP_NUM; i++){
- ss_out_eps[i] = NULL;
- }
- for(i=0; i<MAX_EP_NUM; i++){
- ss_in_eps[i] = NULL;
- }
- for(i=0; i<MAX_EP_NUM; i++){
- hs_eps[i] = NULL;
- }
- for(i=0; i<MAX_EP_NUM; i++){
- tt_intr_eps[i] = NULL;
- }
- return 0;
-}
-
-int add_sch_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
- , int mult, int offset, int repeat, int pkts, int cs_count, int burst_mode
- , int bw_cost, mtk_u32 *ep, struct sch_ep *tmp_ep){
-
- struct sch_ep **ep_array;
- int i;
-
- if(is_in && dev_speed == USB_SPEED_SUPER ){
- ep_array = (struct sch_ep **)ss_in_eps;
- }
- else if(dev_speed == USB_SPEED_SUPER){
- ep_array = (struct sch_ep **)ss_out_eps;
- }
- else if(dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)){
- ep_array = (struct sch_ep **)hs_eps;
- }
- else{
- ep_array = (struct sch_ep **)tt_intr_eps;
- }
- for(i=0; i<MAX_EP_NUM; i++){
- if(ep_array[i] == NULL){
- tmp_ep->dev_speed = dev_speed;
- tmp_ep->isTT = isTT;
- tmp_ep->is_in = is_in;
- tmp_ep->ep_type = ep_type;
- tmp_ep->maxp = maxp;
- tmp_ep->interval = interval;
- tmp_ep->burst = burst;
- tmp_ep->mult = mult;
- tmp_ep->offset = offset;
- tmp_ep->repeat = repeat;
- tmp_ep->pkts = pkts;
- tmp_ep->cs_count = cs_count;
- tmp_ep->burst_mode = burst_mode;
- tmp_ep->bw_cost = bw_cost;
- tmp_ep->ep = ep;
- ep_array[i] = tmp_ep;
- return SCH_SUCCESS;
- }
- }
- return SCH_FAIL;
-}
-
-int count_ss_bw(int is_in, int ep_type, int maxp, int interval, int burst, int mult, int offset, int repeat
- , int td_size){
- int i, j, k;
- int bw_required[3];
- int final_bw_required;
- int bw_required_per_repeat;
- int tmp_bw_required;
- struct sch_ep *cur_sch_ep;
- struct sch_ep **ep_array;
- int cur_offset;
- int cur_ep_offset;
- int tmp_offset;
- int tmp_interval;
- int ep_offset;
- int ep_interval;
- int ep_repeat;
- int ep_mult;
-
- if(is_in){
- ep_array = (struct sch_ep **)ss_in_eps;
- }
- else{
- ep_array = (struct sch_ep **)ss_out_eps;
- }
-
- bw_required[0] = 0;
- bw_required[1] = 0;
- bw_required[2] = 0;
-
- if(repeat == 0){
- final_bw_required = 0;
- for(i=0; i<MAX_EP_NUM; i++){
- cur_sch_ep = ep_array[i];
- if(cur_sch_ep == NULL){
- continue;
- }
- ep_interval = cur_sch_ep->interval;
- ep_offset = cur_sch_ep->offset;
- if(cur_sch_ep->repeat == 0){
- if(ep_interval >= interval){
- tmp_offset = ep_offset + ep_interval - offset;
- tmp_interval = interval;
- }
- else{
- tmp_offset = offset + interval - ep_offset;
- tmp_interval = ep_interval;
- }
- if(tmp_offset % tmp_interval == 0){
- final_bw_required += cur_sch_ep->bw_cost;
- }
- }
- else{
- ep_repeat = cur_sch_ep->repeat;
- ep_mult = cur_sch_ep->mult;
- for(k=0; k<=ep_mult; k++){
- cur_ep_offset = ep_offset+(k*ep_mult);
- if(ep_interval >= interval){
- tmp_offset = cur_ep_offset + ep_interval - offset;
- tmp_interval = interval;
- }
- else{
- tmp_offset = offset + interval - cur_ep_offset;
- tmp_interval = ep_interval;
- }
- if(tmp_offset % tmp_interval == 0){
- final_bw_required += cur_sch_ep->bw_cost;
- break;
- }
- }
- }
- }
- final_bw_required += td_size;
- }
- else{
- bw_required_per_repeat = maxp * (burst+1);
- for(j=0; j<=mult; j++){
- tmp_bw_required = 0;
- cur_offset = offset+(j*repeat);
- for(i=0; i<MAX_EP_NUM; i++){
- cur_sch_ep = ep_array[i];
- if(cur_sch_ep == NULL){
- continue;
- }
- ep_interval = cur_sch_ep->interval;
- ep_offset = cur_sch_ep->offset;
- if(cur_sch_ep->repeat == 0){
- if(ep_interval >= interval){
- tmp_offset = ep_offset + ep_interval - cur_offset;
- tmp_interval = interval;
- }
- else{
- tmp_offset = cur_offset + interval - ep_offset;
- tmp_interval = ep_interval;
- }
- if(tmp_offset % tmp_interval == 0){
- tmp_bw_required += cur_sch_ep->bw_cost;
- }
- }
- else{
- ep_repeat = cur_sch_ep->repeat;
- ep_mult = cur_sch_ep->mult;
- for(k=0; k<=ep_mult; k++){
- cur_ep_offset = ep_offset+(k*ep_repeat);
- if(ep_interval >= interval){
- tmp_offset = cur_ep_offset + ep_interval - cur_offset;
- tmp_interval = interval;
- }
- else{
- tmp_offset = cur_offset + interval - cur_ep_offset;
- tmp_interval = ep_interval;
- }
- if(tmp_offset % tmp_interval == 0){
- tmp_bw_required += cur_sch_ep->bw_cost;
- break;
- }
- }
- }
- }
- bw_required[j] = tmp_bw_required;
- }
- final_bw_required = SS_BW_BOUND;
- for(j=0; j<=mult; j++){
- if(bw_required[j] < final_bw_required){
- final_bw_required = bw_required[j];
- }
- }
- final_bw_required += bw_required_per_repeat;
- }
- return final_bw_required;
-}
-
-int count_hs_bw(int ep_type, int maxp, int interval, int offset, int td_size){
- int i;
- int bw_required;
- struct sch_ep *cur_sch_ep;
- int tmp_offset;
- int tmp_interval;
- int ep_offset;
- int ep_interval;
- int cur_tt_isoc_interval; //for isoc tt check
-
- bw_required = 0;
- for(i=0; i<MAX_EP_NUM; i++){
-
- cur_sch_ep = (struct sch_ep *)hs_eps[i];
- if(cur_sch_ep == NULL){
- continue;
- }
- ep_offset = cur_sch_ep->offset;
- ep_interval = cur_sch_ep->interval;
-
- if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
- cur_tt_isoc_interval = ep_interval<<3;
- if(ep_interval >= interval){
- tmp_offset = ep_offset + cur_tt_isoc_interval - offset;
- tmp_interval = interval;
- }
- else{
- tmp_offset = offset + interval - ep_offset;
- tmp_interval = cur_tt_isoc_interval;
- }
- if(cur_sch_ep->is_in){
- if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
- bw_required += 188;
- }
- }
- else{
- if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
- bw_required += 188;
- }
- }
- }
- else{
- if(ep_interval >= interval){
- tmp_offset = ep_offset + ep_interval - offset;
- tmp_interval = interval;
- }
- else{
- tmp_offset = offset + interval - ep_offset;
- tmp_interval = ep_interval;
- }
- if(tmp_offset%tmp_interval == 0){
- bw_required += cur_sch_ep->bw_cost;
- }
- }
- }
- bw_required += td_size;
- return bw_required;
-}
-
-int count_tt_isoc_bw(int is_in, int maxp, int interval, int offset, int td_size){
- char is_cs;
- int mframe_idx, frame_idx, s_frame, s_mframe, cur_mframe;
- int bw_required, max_bw;
- int ss_cs_count;
- int cs_mframe;
- int max_frame;
- int i,j;
- struct sch_ep *cur_sch_ep;
- int ep_offset;
- int ep_interval;
- int ep_cs_count;
- int tt_isoc_interval; //for isoc tt check
- int cur_tt_isoc_interval; //for isoc tt check
- int tmp_offset;
- int tmp_interval;
-
- is_cs = 0;
-
- tt_isoc_interval = interval<<3; //frame to mframe
- if(is_in){
- is_cs = 1;
- }
- s_frame = offset/8;
- s_mframe = offset%8;
- ss_cs_count = (maxp + (188 - 1))/188;
- if(is_cs){
- cs_mframe = offset%8 + 2 + ss_cs_count;
- if (cs_mframe <= 6)
- ss_cs_count += 2;
- else if (cs_mframe == 7)
- ss_cs_count++;
- else if (cs_mframe > 8)
- return -1;
- }
- max_bw = 0;
- if(is_in){
- i=2;
- }
- for(cur_mframe = offset+i; i<ss_cs_count; cur_mframe++, i++){
- bw_required = 0;
- for(j=0; j<MAX_EP_NUM; j++){
- cur_sch_ep = (struct sch_ep *)hs_eps[j];
- if(cur_sch_ep == NULL){
- continue;
- }
- ep_offset = cur_sch_ep->offset;
- ep_interval = cur_sch_ep->interval;
- if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
- //isoc tt
- //check if mframe offset overlap
- //if overlap, add 188 to the bw
- cur_tt_isoc_interval = ep_interval<<3;
- if(cur_tt_isoc_interval >= tt_isoc_interval){
- tmp_offset = (ep_offset+cur_tt_isoc_interval) - cur_mframe;
- tmp_interval = tt_isoc_interval;
- }
- else{
- tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
- tmp_interval = cur_tt_isoc_interval;
- }
- if(cur_sch_ep->is_in){
- if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
- bw_required += 188;
- }
- }
- else{
- if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
- bw_required += 188;
- }
- }
-
- }
- else if(cur_sch_ep->ep_type == USB_EP_INT || cur_sch_ep->ep_type == USB_EP_ISOC){
- //check if mframe
- if(ep_interval >= tt_isoc_interval){
- tmp_offset = (ep_offset+ep_interval) - cur_mframe;
- tmp_interval = tt_isoc_interval;
- }
- else{
- tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
- tmp_interval = ep_interval;
- }
- if(tmp_offset%tmp_interval == 0){
- bw_required += cur_sch_ep->bw_cost;
- }
- }
- }
- bw_required += 188;
- if(bw_required > max_bw){
- max_bw = bw_required;
- }
- }
- return max_bw;
-}
-
-int count_tt_intr_bw(int interval, int frame_offset){
- //check all eps in tt_intr_eps
- int ret;
- int i,j;
- int ep_offset;
- int ep_interval;
- int tmp_offset;
- int tmp_interval;
- ret = SCH_SUCCESS;
- struct sch_ep *cur_sch_ep;
-
- for(i=0; i<MAX_EP_NUM; i++){
- cur_sch_ep = (struct sch_ep *)tt_intr_eps[i];
- if(cur_sch_ep == NULL){
- continue;
- }
- ep_offset = cur_sch_ep->offset;
- ep_interval = cur_sch_ep->interval;
- if(ep_interval >= interval){
- tmp_offset = ep_offset + ep_interval - frame_offset;
- tmp_interval = interval;
- }
- else{
- tmp_offset = frame_offset + interval - ep_offset;
- tmp_interval = ep_interval;
- }
-
- if(tmp_offset%tmp_interval==0){
- return SCH_FAIL;
- }
- }
- return SCH_SUCCESS;
-}
-
-struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep){
- int i;
- struct sch_ep **ep_array;
- struct sch_ep *cur_ep;
-
- if (is_in && dev_speed == USB_SPEED_SUPER) {
- ep_array = (struct sch_ep **)ss_in_eps;
- }
- else if (dev_speed == USB_SPEED_SUPER) {
- ep_array = (struct sch_ep **)ss_out_eps;
- }
- else if (dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)) {
- ep_array = (struct sch_ep **)hs_eps;
- }
- else {
- ep_array = (struct sch_ep **)tt_intr_eps;
- }
- for (i = 0; i < MAX_EP_NUM; i++) {
- cur_ep = (struct sch_ep *)ep_array[i];
- if(cur_ep != NULL && cur_ep->ep == ep){
- ep_array[i] = NULL;
- return cur_ep;
- }
- }
- return NULL;
-}
-
-int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
- , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep){
- mtk_u32 bPkts = 0;
- mtk_u32 bCsCount = 0;
- mtk_u32 bBm = 1;
- mtk_u32 bOffset = 0;
- mtk_u32 bRepeat = 0;
- int ret;
- struct mtk_xhci_ep_ctx *temp_ep_ctx;
- int td_size;
- int mframe_idx, frame_idx;
- int bw_cost;
- int cur_bw, best_bw, best_bw_idx,repeat, max_repeat, best_bw_repeat;
- int cur_offset, cs_mframe;
- int break_out;
- int frame_interval;
-
- printk(KERN_ERR "add_ep parameters, dev_speed %d, is_in %d, isTT %d, ep_type %d, maxp %d, interval %d, burst %d, mult %d, ep 0x%x, ep_ctx 0x%x, sch_ep 0x%x\n", dev_speed, is_in, isTT, ep_type, maxp
- , interval, burst, mult, ep, ep_ctx, sch_ep);
- if(isTT && ep_type == USB_EP_INT && ((dev_speed == USB_SPEED_LOW) || (dev_speed == USB_SPEED_FULL))){
- frame_interval = interval >> 3;
- for(frame_idx=0; frame_idx<frame_interval; frame_idx++){
- printk(KERN_ERR "check tt_intr_bw interval %d, frame_idx %d\n", frame_interval, frame_idx);
- if(count_tt_intr_bw(frame_interval, frame_idx) == SCH_SUCCESS){
- printk(KERN_ERR "check OK............\n");
- bOffset = frame_idx<<3;
- bPkts = 1;
- bCsCount = 3;
- bw_cost = maxp;
- bRepeat = 0;
- if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, frame_interval, burst, mult
- , bOffset, bRepeat, bPkts, bCsCount, bBm, maxp, ep, sch_ep) == SCH_FAIL){
- return SCH_FAIL;
- }
- ret = SCH_SUCCESS;
- break;
- }
- }
- }
- else if(isTT && ep_type == USB_EP_ISOC){
- best_bw = HS_BW_BOUND;
- best_bw_idx = -1;
- cur_bw = 0;
- td_size = maxp;
- break_out = 0;
- frame_interval = interval>>3;
- for(frame_idx=0; frame_idx<frame_interval && !break_out; frame_idx++){
- for(mframe_idx=0; mframe_idx<8; mframe_idx++){
- cur_offset = (frame_idx*8) + mframe_idx;
- cur_bw = count_tt_isoc_bw(is_in, maxp, frame_interval, cur_offset, td_size);
- if(cur_bw > 0 && cur_bw < best_bw){
- best_bw_idx = cur_offset;
- best_bw = cur_bw;
- if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
- break_out = 1;
- break;
- }
- }
- }
- }
- if(best_bw_idx == -1){
- return SCH_FAIL;
- }
- else{
- bOffset = best_bw_idx;
- bPkts = 1;
- bCsCount = (maxp + (188 - 1)) / 188;
- if(is_in){
- cs_mframe = bOffset%8 + 2 + bCsCount;
- if (cs_mframe <= 6)
- bCsCount += 2;
- else if (cs_mframe == 7)
- bCsCount++;
- }
- bw_cost = 188;
- bRepeat = 0;
- if(add_sch_ep( dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
- , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
- return SCH_FAIL;
- }
- ret = SCH_SUCCESS;
- }
- }
- else if((dev_speed == USB_SPEED_FULL || dev_speed == USB_SPEED_LOW) && ep_type == USB_EP_INT){
- bPkts = 1;
- ret = SCH_SUCCESS;
- }
- else if(dev_speed == USB_SPEED_FULL && ep_type == USB_EP_ISOC){
- bPkts = 1;
- ret = SCH_SUCCESS;
- }
- else if(dev_speed == USB_SPEED_HIGH && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
- best_bw = HS_BW_BOUND;
- best_bw_idx = -1;
- cur_bw = 0;
- td_size = maxp*(burst+1);
- for(cur_offset = 0; cur_offset<interval; cur_offset++){
- cur_bw = count_hs_bw(ep_type, maxp, interval, cur_offset, td_size);
- if(cur_bw > 0 && cur_bw < best_bw){
- best_bw_idx = cur_offset;
- best_bw = cur_bw;
- if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
- break;
- }
- }
- }
- if(best_bw_idx == -1){
- return SCH_FAIL;
- }
- else{
- bOffset = best_bw_idx;
- bPkts = burst + 1;
- bCsCount = 0;
- bw_cost = td_size;
- bRepeat = 0;
- if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
- , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
- return SCH_FAIL;
- }
- ret = SCH_SUCCESS;
- }
- }
- else if(dev_speed == USB_SPEED_SUPER && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
- best_bw = SS_BW_BOUND;
- best_bw_idx = -1;
- cur_bw = 0;
- td_size = maxp * (mult+1) * (burst+1);
- if(mult == 0){
- max_repeat = 0;
- }
- else{
- max_repeat = (interval-1)/(mult+1);
- }
- break_out = 0;
- for(frame_idx = 0; (frame_idx < interval) && !break_out; frame_idx++){
- for(repeat = max_repeat; repeat >= 0; repeat--){
- cur_bw = count_ss_bw(is_in, ep_type, maxp, interval, burst, mult, frame_idx
- , repeat, td_size);
- printk(KERN_ERR "count_ss_bw, frame_idx %d, repeat %d, td_size %d, result bw %d\n"
- , frame_idx, repeat, td_size, cur_bw);
- if(cur_bw > 0 && cur_bw < best_bw){
- best_bw_idx = frame_idx;
- best_bw_repeat = repeat;
- best_bw = cur_bw;
- if(cur_bw <= td_size || cur_bw < (HS_BW_BOUND>>1)){
- break_out = 1;
- break;
- }
- }
- }
- }
- printk(KERN_ERR "final best idx %d, best repeat %d\n", best_bw_idx, best_bw_repeat);
- if(best_bw_idx == -1){
- return SCH_FAIL;
- }
- else{
- bOffset = best_bw_idx;
- bCsCount = 0;
- bRepeat = best_bw_repeat;
- if(bRepeat == 0){
- bw_cost = (burst+1)*(mult+1)*maxp;
- bPkts = (burst+1)*(mult+1);
- }
- else{
- bw_cost = (burst+1)*maxp;
- bPkts = (burst+1);
- }
- if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
- , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
- return SCH_FAIL;
- }
- ret = SCH_SUCCESS;
- }
- }
- else{
- bPkts = 1;
- ret = SCH_SUCCESS;
- }
- if(ret == SCH_SUCCESS){
- temp_ep_ctx = (struct mtk_xhci_ep_ctx *)ep_ctx;
- temp_ep_ctx->reserved[0] |= (BPKTS(bPkts) | BCSCOUNT(bCsCount) | BBM(bBm));
- temp_ep_ctx->reserved[1] |= (BOFFSET(bOffset) | BREPEAT(bRepeat));
-
- printk(KERN_DEBUG "[DBG] BPKTS: %x, BCSCOUNT: %x, BBM: %x\n", bPkts, bCsCount, bBm);
- printk(KERN_DEBUG "[DBG] BOFFSET: %x, BREPEAT: %x\n", bOffset, bRepeat);
- return SCH_SUCCESS;
- }
- else{
- return SCH_FAIL;
- }
-}
diff --git a/target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.h b/target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.h
deleted file mode 100644
index c55dfb10da..0000000000
--- a/target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.h
+++ /dev/null
@@ -1,77 +0,0 @@
-#ifndef _XHCI_MTK_SCHEDULER_H
-#define _XHCI_MTK_SCHEDULER_H
-
-#define MTK_SCH_NEW 1
-
-#define SCH_SUCCESS 1
-#define SCH_FAIL 0
-
-#define MAX_EP_NUM 64
-#define SS_BW_BOUND 51000
-#define HS_BW_BOUND 6144
-
-#define USB_EP_CONTROL 0
-#define USB_EP_ISOC 1
-#define USB_EP_BULK 2
-#define USB_EP_INT 3
-
-#define USB_SPEED_LOW 1
-#define USB_SPEED_FULL 2
-#define USB_SPEED_HIGH 3
-#define USB_SPEED_SUPER 5
-
-/* mtk scheduler bitmasks */
-#define BPKTS(p) ((p) & 0x3f)
-#define BCSCOUNT(p) (((p) & 0x7) << 8)
-#define BBM(p) ((p) << 11)
-#define BOFFSET(p) ((p) & 0x3fff)
-#define BREPEAT(p) (((p) & 0x7fff) << 16)
-
-
-#if 1
-typedef unsigned int mtk_u32;
-typedef unsigned long long mtk_u64;
-#endif
-
-#define NULL ((void *)0)
-
-struct mtk_xhci_ep_ctx {
- mtk_u32 ep_info;
- mtk_u32 ep_info2;
- mtk_u64 deq;
- mtk_u32 tx_info;
- /* offset 0x14 - 0x1f reserved for HC internal use */
- mtk_u32 reserved[3];
-};
-
-
-struct sch_ep
-{
- //device info
- int dev_speed;
- int isTT;
- //ep info
- int is_in;
- int ep_type;
- int maxp;
- int interval;
- int burst;
- int mult;
- //scheduling info
- int offset;
- int repeat;
- int pkts;
- int cs_count;
- int burst_mode;
- //other
- int bw_cost; //bandwidth cost in each repeat; including overhead
- mtk_u32 *ep; //address of usb_endpoint pointer
-};
-
-int mtk_xhci_scheduler_init(void);
-int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
- , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep);
-struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep);
-
-
-#endif
diff --git a/target/linux/ramips/files/drivers/usb/host/xhci-mtk.c b/target/linux/ramips/files/drivers/usb/host/xhci-mtk.c
deleted file mode 100644
index 2eed0a174a..0000000000
--- a/target/linux/ramips/files/drivers/usb/host/xhci-mtk.c
+++ /dev/null
@@ -1,265 +0,0 @@
-#include "xhci-mtk.h"
-#include "xhci-mtk-power.h"
-#include "xhci.h"
-#include "mtk-phy.h"
-#ifdef CONFIG_C60802_SUPPORT
-#include "mtk-phy-c60802.h"
-#endif
-#include "xhci-mtk-scheduler.h"
-#include <linux/kernel.h> /* printk() */
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <asm/uaccess.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-
-void setInitialReg(void )
-{
- __u32 __iomem *addr;
- u32 temp;
-
- /* set SSUSB DMA burst size to 128B */
- addr = SSUSB_U3_XHCI_BASE + SSUSB_HDMA_CFG;
- temp = SSUSB_HDMA_CFG_MT7621_VALUE;
- writel(temp, addr);
-
- /* extend U3 LTSSM Polling.LFPS timeout value */
- addr = SSUSB_U3_XHCI_BASE + U3_LTSSM_TIMING_PARAMETER3;
- temp = U3_LTSSM_TIMING_PARAMETER3_VALUE;
- writel(temp, addr);
-
- /* EOF */
- addr = SSUSB_U3_XHCI_BASE + SYNC_HS_EOF;
- temp = SYNC_HS_EOF_VALUE;
- writel(temp, addr);
-
-#if defined (CONFIG_PERIODIC_ENP)
- /* HSCH_CFG1: SCH2_FIFO_DEPTH */
- addr = SSUSB_U3_XHCI_BASE + HSCH_CFG1;
- temp = readl(addr);
- temp &= ~(0x3 << SCH2_FIFO_DEPTH_OFFSET);
- writel(temp, addr);
-#endif
-
- /* Doorbell handling */
- addr = SIFSLV_IPPC + SSUSB_IP_SPAR0;
- temp = 0x1;
- writel(temp, addr);
-
- /* Set SW PLL Stable mode to 1 for U2 LPM device remote wakeup */
- /* Port 0 */
- addr = U2_PHY_BASE + U2_PHYD_CR1;
- temp = readl(addr);
- temp &= ~(0x3 << 18);
- temp |= (1 << 18);
- writel(temp, addr);
-
- /* Port 1 */
- addr = U2_PHY_BASE_P1 + U2_PHYD_CR1;
- temp = readl(addr);
- temp &= ~(0x3 << 18);
- temp |= (1 << 18);
- writel(temp, addr);
-}
-
-
-void setLatchSel(void){
- __u32 __iomem *latch_sel_addr;
- u32 latch_sel_value;
- latch_sel_addr = U3_PIPE_LATCH_SEL_ADD;
- latch_sel_value = ((U3_PIPE_LATCH_TX)<<2) | (U3_PIPE_LATCH_RX);
- writel(latch_sel_value, latch_sel_addr);
-}
-
-void reinitIP(void){
- __u32 __iomem *ip_reset_addr;
- u32 ip_reset_value;
-
- enableAllClockPower();
- mtk_xhci_scheduler_init();
-}
-
-void dbg_prb_out(void){
- mtk_probe_init(0x0f0f0f0f);
- mtk_probe_out(0xffffffff);
- mtk_probe_out(0x01010101);
- mtk_probe_out(0x02020202);
- mtk_probe_out(0x04040404);
- mtk_probe_out(0x08080808);
- mtk_probe_out(0x10101010);
- mtk_probe_out(0x20202020);
- mtk_probe_out(0x40404040);
- mtk_probe_out(0x80808080);
- mtk_probe_out(0x55555555);
- mtk_probe_out(0xaaaaaaaa);
-}
-
-
-
-///////////////////////////////////////////////////////////////////////////////
-
-#define RET_SUCCESS 0
-#define RET_FAIL 1
-
-static int dbg_u3w(int argc, char**argv)
-{
- int u4TimingValue;
- char u1TimingValue;
- int u4TimingAddress;
-
- if (argc<3)
- {
- printk(KERN_ERR "Arg: address value\n");
- return RET_FAIL;
- }
- u3phy_init();
-
- u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
- u4TimingValue = (int)simple_strtol(argv[2], &argv[2], 16);
- u1TimingValue = u4TimingValue & 0xff;
- /* access MMIO directly */
- writel(u1TimingValue, u4TimingAddress);
- printk(KERN_ERR "Write done\n");
- return RET_SUCCESS;
-
-}
-
-static int dbg_u3r(int argc, char**argv)
-{
- char u1ReadTimingValue;
- int u4TimingAddress;
- if (argc<2)
- {
- printk(KERN_ERR "Arg: address\n");
- return 0;
- }
- u3phy_init();
- mdelay(500);
- u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
- /* access MMIO directly */
- u1ReadTimingValue = readl(u4TimingAddress);
- printk(KERN_ERR "Value = 0x%x\n", u1ReadTimingValue);
- return 0;
-}
-
-static int dbg_u3init(int argc, char**argv)
-{
- int ret;
- ret = u3phy_init();
- printk(KERN_ERR "phy registers and operations initial done\n");
- if(u3phy_ops->u2_slew_rate_calibration){
- u3phy_ops->u2_slew_rate_calibration(u3phy);
- }
- else{
- printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
- }
- if(u3phy_ops->init(u3phy) == PHY_TRUE)
- return RET_SUCCESS;
- return RET_FAIL;
-}
-
-void dbg_setU1U2(int argc, char**argv){
- struct xhci_hcd *xhci;
- int u1_value;
- int u2_value;
- u32 port_id, temp;
- u32 __iomem *addr;
-
- if (argc<3)
- {
- printk(KERN_ERR "Arg: u1value u2value\n");
- return RET_FAIL;
- }
-
- u1_value = (int)simple_strtol(argv[1], &argv[1], 10);
- u2_value = (int)simple_strtol(argv[2], &argv[2], 10);
- addr = (SSUSB_U3_XHCI_BASE + 0x424);
- temp = readl(addr);
- temp = temp & (~(0x0000ffff));
- temp = temp | u1_value | (u2_value<<8);
- writel(temp, addr);
-}
-///////////////////////////////////////////////////////////////////////////////
-
-int call_function(char *buf)
-{
- int i;
- int argc;
- char *argv[80];
-
- argc = 0;
- do
- {
- argv[argc] = strsep(&buf, " ");
- printk(KERN_DEBUG "[%d] %s\r\n", argc, argv[argc]);
- argc++;
- } while (buf);
- if (!strcmp("dbg.r", argv[0]))
- dbg_prb_out();
- else if (!strcmp("dbg.u3w", argv[0]))
- dbg_u3w(argc, argv);
- else if (!strcmp("dbg.u3r", argv[0]))
- dbg_u3r(argc, argv);
- else if (!strcmp("dbg.u3i", argv[0]))
- dbg_u3init(argc, argv);
- else if (!strcmp("pw.u1u2", argv[0]))
- dbg_setU1U2(argc, argv);
- return 0;
-}
-
-long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- char w_buf[200];
- char r_buf[200] = "this is a test";
- int len = 200;
-
- switch (cmd) {
- case IOCTL_READ:
- copy_to_user((char *) arg, r_buf, len);
- printk(KERN_DEBUG "IOCTL_READ: %s\r\n", r_buf);
- break;
- case IOCTL_WRITE:
- copy_from_user(w_buf, (char *) arg, len);
- printk(KERN_DEBUG "IOCTL_WRITE: %s\r\n", w_buf);
-
- //invoke function
- return call_function(w_buf);
- break;
- default:
- return -ENOTTY;
- }
-
- return len;
-}
-
-int xhci_mtk_test_open(struct inode *inode, struct file *file)
-{
-
- printk(KERN_DEBUG "xhci_mtk_test open: successful\n");
- return 0;
-}
-
-int xhci_mtk_test_release(struct inode *inode, struct file *file)
-{
-
- printk(KERN_DEBUG "xhci_mtk_test release: successful\n");
- return 0;
-}
-
-ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr)
-{
-
- printk(KERN_DEBUG "xhci_mtk_test read: returning zero bytes\n");
- return 0;
-}
-
-ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos)
-{
-
- printk(KERN_DEBUG "xhci_mtk_test write: accepting zero bytes\n");
- return 0;
-}
-
-
-
-
diff --git a/target/linux/ramips/files/drivers/usb/host/xhci-mtk.h b/target/linux/ramips/files/drivers/usb/host/xhci-mtk.h
deleted file mode 100644
index 0f2d5e834c..0000000000
--- a/target/linux/ramips/files/drivers/usb/host/xhci-mtk.h
+++ /dev/null
@@ -1,120 +0,0 @@
-#ifndef _XHCI_MTK_H
-#define _XHCI_MTK_H
-
-#include <linux/usb.h>
-#include "xhci.h"
-
-#define SSUSB_U3_XHCI_BASE 0xBE1C0000
-#define SSUSB_U3_MAC_BASE 0xBE1C2400
-#define SSUSB_U3_SYS_BASE 0xBE1C2600
-#define SSUSB_U2_SYS_BASE 0xBE1C3400
-#define SSUB_SIF_SLV_TOP 0xBE1D0000
-#define SIFSLV_IPPC (SSUB_SIF_SLV_TOP + 0x700)
-
-#define U3_PIPE_LATCH_SEL_ADD SSUSB_U3_MAC_BASE + 0x130
-#define U3_PIPE_LATCH_TX 0
-#define U3_PIPE_LATCH_RX 0
-
-#define U3_UX_EXIT_LFPS_TIMING_PAR 0xa0
-#define U3_REF_CK_PAR 0xb0
-#define U3_RX_UX_EXIT_LFPS_REF_OFFSET 8
-#define U3_RX_UX_EXIT_LFPS_REF 3
-#define U3_REF_CK_VAL 10
-
-#define U3_TIMING_PULSE_CTRL 0xb4
-#define CNT_1US_VALUE 63 //62.5MHz:63, 70MHz:70, 80MHz:80, 100MHz:100, 125MHz:125
-
-#define USB20_TIMING_PARAMETER 0x40
-#define TIME_VALUE_1US 63 //62.5MHz:63, 80MHz:80, 100MHz:100, 125MHz:125
-
-#define LINK_PM_TIMER 0x8
-#define PM_LC_TIMEOUT_VALUE 3
-
-#define XHCI_IMOD 0x624
-#define XHCI_IMOD_MT7621_VALUE 0x10
-
-#define SSUSB_HDMA_CFG 0x950
-#define SSUSB_HDMA_CFG_MT7621_VALUE 0x10E0E0C
-
-#define U3_LTSSM_TIMING_PARAMETER3 0x2514
-#define U3_LTSSM_TIMING_PARAMETER3_VALUE 0x3E8012C
-
-#define U2_PHYD_CR1 0x64
-
-#define SSUSB_IP_SPAR0 0xC8
-
-#define SYNC_HS_EOF 0x938
-#define SYNC_HS_EOF_VALUE 0x201F3
-
-#define HSCH_CFG1 0x960
-#define SCH2_FIFO_DEPTH_OFFSET 16
-
-
-#define SSUSB_IP_PW_CTRL (SIFSLV_IPPC+0x0)
-#define SSUSB_IP_SW_RST (1<<0)
-#define SSUSB_IP_PW_CTRL_1 (SIFSLV_IPPC+0x4)
-#define SSUSB_IP_PDN (1<<0)
-#define SSUSB_U3_CTRL(p) (SIFSLV_IPPC+0x30+(p*0x08))
-#define SSUSB_U3_PORT_DIS (1<<0)
-#define SSUSB_U3_PORT_PDN (1<<1)
-#define SSUSB_U3_PORT_HOST_SEL (1<<2)
-#define SSUSB_U3_PORT_CKBG_EN (1<<3)
-#define SSUSB_U3_PORT_MAC_RST (1<<4)
-#define SSUSB_U3_PORT_PHYD_RST (1<<5)
-#define SSUSB_U2_CTRL(p) (SIFSLV_IPPC+(0x50)+(p*0x08))
-#define SSUSB_U2_PORT_DIS (1<<0)
-#define SSUSB_U2_PORT_PDN (1<<1)
-#define SSUSB_U2_PORT_HOST_SEL (1<<2)
-#define SSUSB_U2_PORT_CKBG_EN (1<<3)
-#define SSUSB_U2_PORT_MAC_RST (1<<4)
-#define SSUSB_U2_PORT_PHYD_RST (1<<5)
-#define SSUSB_IP_CAP (SIFSLV_IPPC+0x024)
-
-#define SSUSB_U3_PORT_NUM(p) (p & 0xff)
-#define SSUSB_U2_PORT_NUM(p) ((p>>8) & 0xff)
-
-
-#define XHCI_MTK_TEST_MAJOR 234
-#define DEVICE_NAME "xhci_mtk_test"
-
-#define CLI_MAGIC 'CLI'
-#define IOCTL_READ _IOR(CLI_MAGIC, 0, int)
-#define IOCTL_WRITE _IOW(CLI_MAGIC, 1, int)
-
-void reinitIP(void);
-void setInitialReg(void);
-void dbg_prb_out(void);
-int call_function(char *buf);
-
-long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
-int xhci_mtk_test_open(struct inode *inode, struct file *file);
-int xhci_mtk_test_release(struct inode *inode, struct file *file);
-ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr);
-ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos);
-
-/*
- mediatek probe out
-*/
-/************************************************************************************/
-
-#define SW_PRB_OUT_ADDR (SIFSLV_IPPC+0xc0)
-#define PRB_MODULE_SEL_ADDR (SIFSLV_IPPC+0xbc)
-
-static inline void mtk_probe_init(const u32 byte){
- __u32 __iomem *ptr = (__u32 __iomem *) PRB_MODULE_SEL_ADDR;
- writel(byte, ptr);
-}
-
-static inline void mtk_probe_out(const u32 value){
- __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
- writel(value, ptr);
-}
-
-static inline u32 mtk_probe_value(void){
- __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
-
- return readl(ptr);
-}
-
-
-#endif
diff --git a/target/linux/ramips/mt7621/config-3.10 b/target/linux/ramips/mt7621/config-3.10
index 194bb4a1cc..86bc7bef4f 100644
--- a/target/linux/ramips/mt7621/config-3.10
+++ b/target/linux/ramips/mt7621/config-3.10
@@ -1,6 +1,8 @@
+# CONFIG_32B_DESC is not set
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
@@ -35,6 +37,14 @@ CONFIG_DMA_NONCOHERENT=y
CONFIG_DTB_RT_NONE=y
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
+CONFIG_ESW_DOUBLE_VLAN_TAG=y
+# CONFIG_GE1_MII_AN is not set
+# CONFIG_GE1_MII_FORCE_100 is not set
+# CONFIG_GE1_RGMII_AN is not set
+CONFIG_GE1_RGMII_FORCE_1000=y
+# CONFIG_GE1_RGMII_NONE is not set
+# CONFIG_GE1_RVMII_FORCE_100 is not set
+# CONFIG_GE1_TRGMII_FORCE_1200 is not set
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@@ -88,6 +98,7 @@ CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_GIC=y
CONFIG_IRQ_WORK=y
+# CONFIG_LAN_WAN_SUPPORT is not set
CONFIG_M25PXX_USE_FAST_READ=y
CONFIG_MDIO_BOARDINFO=y
# CONFIG_MII is not set
@@ -105,6 +116,7 @@ CONFIG_MIPS_MT_SMP=y
CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MT7621_ASIC=y
# CONFIG_MT7621_WDT is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CMDLINE_PARTS=y
@@ -137,6 +149,7 @@ CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_PCI=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
+CONFIG_PDMA_NEW=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PHYLIB=y
# CONFIG_PINCONF is not set
@@ -145,12 +158,30 @@ CONFIG_PINCTRL_RT2880=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PINMUX=y
# CONFIG_PREEMPT_RCU is not set
+CONFIG_RAETH=y
+CONFIG_RAETH_CHECKSUM_OFFLOAD=y
+# CONFIG_RAETH_GMAC2 is not set
+# CONFIG_RAETH_HW_VLAN_RX is not set
+# CONFIG_RAETH_HW_VLAN_TX is not set
+# CONFIG_RAETH_LRO is not set
+# CONFIG_RAETH_NAPI is not set
+# CONFIG_RAETH_QDMA is not set
+CONFIG_RAETH_SCATTER_GATHER_RX_DMA=y
+# CONFIG_RAETH_SKB_RECYCLE_2K is not set
+# CONFIG_RAETH_SPECIAL_TAG is not set
+# CONFIG_RAETH_TSO is not set
CONFIG_RALINK=y
+CONFIG_RALINK_MT7621=y
CONFIG_RALINK_USBPHY=y
+# CONFIG_RALINK_WDT is not set
+CONFIG_RA_NAT_NONE=y
+# CONFIG_RA_NETWORK_TASKLET_BH is not set
+CONFIG_RA_NETWORK_WORKQUEUE_BH=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
+CONFIG_RT_3052_ESW=y
# CONFIG_SAMSUNG_USB2PHY is not set
# CONFIG_SAMSUNG_USB3PHY is not set
# CONFIG_SAMSUNG_USBPHY is not set
@@ -199,6 +230,8 @@ CONFIG_USB_XHCI_HCD=m
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USE_GENERIC_SMP_HELPERS=y
CONFIG_USE_OF=y
+CONFIG_WAN_AT_P0=y
+# CONFIG_WAN_AT_P4 is not set
CONFIG_WATCHDOG_CORE=y
CONFIG_WEAK_ORDERING=y
CONFIG_XPS=y
diff --git a/target/linux/ramips/mt7621/profiles/00-default.mk b/target/linux/ramips/mt7621/profiles/00-default.mk
index a905d1ed80..fb04ba788c 100644
--- a/target/linux/ramips/mt7621/profiles/00-default.mk
+++ b/target/linux/ramips/mt7621/profiles/00-default.mk
@@ -8,7 +8,7 @@
define Profile/Default
NAME:=Default Profile
PACKAGES:=\
- kmod-usb-core kmod-usb-dwc2 \
+ kmod-usb-core kmod-usb3 \
kmod-ledtrig-usbdev
endef
diff --git a/target/linux/ramips/patches-3.10/0100-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch b/target/linux/ramips/patches-3.10/0100-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch
index e87eb4d394..1d2e728cff 100644
--- a/target/linux/ramips/patches-3.10/0100-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch
+++ b/target/linux/ramips/patches-3.10/0100-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch
@@ -1,7 +1,7 @@
-From cdc1b12b3debaf5b3894fd146e73221a8acd0152 Mon Sep 17 00:00:00 2001
+From 1be15a87eea5f26fb24b6aac332530cd3e2d984e Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 14 Jul 2013 23:08:11 +0200
-Subject: [PATCH 20/25] MIPS: use set_mode() to enable/disable the cevt-r4k
+Subject: [PATCH 100/133] MIPS: use set_mode() to enable/disable the cevt-r4k
irq
Signed-off-by: John Crispin <blogic@openwrt.org>
@@ -24,13 +24,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
int cp0_timer_irq_installed;
-@@ -90,6 +84,32 @@ struct irqaction c0_compare_irqaction =
+@@ -90,9 +84,38 @@ struct irqaction c0_compare_irqaction =
.name = "timer",
};
+void mips_set_clock_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
+{
++#ifdef CONFIG_CEVT_SYSTICK_QUIRK
+ switch (mode) {
+ case CLOCK_EVT_MODE_ONESHOT:
+ if (cp0_timer_irq_installed)
@@ -53,21 +54,27 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ pr_err("Unhandeled mips clock_mode\n");
+ break;
+ }
++#endif
+}
void mips_event_handler(struct clock_event_device *dev)
{
-@@ -215,13 +235,6 @@ int __cpuinit r4k_clockevent_init(void)
++
+ }
+
+ /*
+@@ -215,12 +238,14 @@ int __cpuinit r4k_clockevent_init(void)
#endif
clockevents_register_device(cd);
-- if (cp0_timer_irq_installed)
-- return 0;
--
-- cp0_timer_irq_installed = 1;
--
-- setup_irq(irq, &c0_compare_irqaction);
--
++#ifndef CONFIG_CEVT_SYSTICK_QUIRK
+ if (cp0_timer_irq_installed)
+ return 0;
+
+ cp0_timer_irq_installed = 1;
+
+ setup_irq(irq, &c0_compare_irqaction);
++#endif
+
return 0;
}
-
diff --git a/target/linux/ramips/patches-3.10/0102-MIPS-ralink-add-verbose-pmu-info.patch b/target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-verbose-pmu-info.patch
similarity index 92%
rename from target/linux/ramips/patches-3.10/0102-MIPS-ralink-add-verbose-pmu-info.patch
rename to target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-verbose-pmu-info.patch
index 687b883fe3..5a7d5f9997 100644
--- a/target/linux/ramips/patches-3.10/0102-MIPS-ralink-add-verbose-pmu-info.patch
+++ b/target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-verbose-pmu-info.patch
@@ -1,7 +1,7 @@
-From 74339d6eab7a37f7c629b737bf686d30e5014ce2 Mon Sep 17 00:00:00 2001
+From 5689333e7e4396a827a2cb6fa1242159e9af56de Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 20 May 2013 20:57:09 +0200
-Subject: [PATCH 06/33] MIPS: ralink: add verbose pmu info
+Subject: [PATCH 101/133] MIPS: ralink: add verbose pmu info
Print the PMU and LDO settings on boot.
diff --git a/target/linux/ramips/patches-3.10/0103-MIPS-ralink-adds-a-bootrom-dumper-module.patch b/target/linux/ramips/patches-3.10/0102-MIPS-ralink-adds-a-bootrom-dumper-module.patch
similarity index 93%
rename from target/linux/ramips/patches-3.10/0103-MIPS-ralink-adds-a-bootrom-dumper-module.patch
rename to target/linux/ramips/patches-3.10/0102-MIPS-ralink-adds-a-bootrom-dumper-module.patch
index c0910326c9..e295a4aa4d 100644
--- a/target/linux/ramips/patches-3.10/0103-MIPS-ralink-adds-a-bootrom-dumper-module.patch
+++ b/target/linux/ramips/patches-3.10/0102-MIPS-ralink-adds-a-bootrom-dumper-module.patch
@@ -1,7 +1,7 @@
-From 71409a190a0c8e3597cae7d46321742e29d8994b Mon Sep 17 00:00:00 2001
+From 23d18a1b3d0a7e5faa08b6bece6692667c930975 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 21 May 2013 15:50:31 +0200
-Subject: [PATCH 07/33] MIPS: ralink: adds a bootrom dumper module
+Subject: [PATCH 102/133] MIPS: ralink: adds a bootrom dumper module
This patch adds a trivial driver that allows userland to extract the bootrom of
a SoC via debugfs.
diff --git a/target/linux/ramips/patches-3.10/0104-MIPS-ralink-add-illegal-access-driver.patch b/target/linux/ramips/patches-3.10/0103-MIPS-ralink-add-illegal-access-driver.patch
similarity index 95%
rename from target/linux/ramips/patches-3.10/0104-MIPS-ralink-add-illegal-access-driver.patch
rename to target/linux/ramips/patches-3.10/0103-MIPS-ralink-add-illegal-access-driver.patch
index 082c324531..4dfa7b5372 100644
--- a/target/linux/ramips/patches-3.10/0104-MIPS-ralink-add-illegal-access-driver.patch
+++ b/target/linux/ramips/patches-3.10/0103-MIPS-ralink-add-illegal-access-driver.patch
@@ -1,7 +1,7 @@
-From 46446fcfc6e823005ebe71357b5995524e75542c Mon Sep 17 00:00:00 2001
+From c5fe00f24f56b15f982dda355089986d57488b36 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 16 May 2013 23:28:23 +0200
-Subject: [PATCH 08/33] MIPS: ralink: add illegal access driver
+Subject: [PATCH 103/133] MIPS: ralink: add illegal access driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---
diff --git a/target/linux/ramips/patches-3.10/0105-MIPS-ralink-workaround-DTB-memory-issue.patch b/target/linux/ramips/patches-3.10/0104-MIPS-ralink-workaround-DTB-memory-issue.patch
similarity index 82%
rename from target/linux/ramips/patches-3.10/0105-MIPS-ralink-workaround-DTB-memory-issue.patch
rename to target/linux/ramips/patches-3.10/0104-MIPS-ralink-workaround-DTB-memory-issue.patch
index 662b356304..c9a12b3676 100644
--- a/target/linux/ramips/patches-3.10/0105-MIPS-ralink-workaround-DTB-memory-issue.patch
+++ b/target/linux/ramips/patches-3.10/0104-MIPS-ralink-workaround-DTB-memory-issue.patch
@@ -1,7 +1,7 @@
-From 070a389ae536a75b9184784f625949c215c533b6 Mon Sep 17 00:00:00 2001
+From b83808826ac7a5c727f5314b5a3bf07fcd6ec929 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 23 May 2013 18:50:56 +0200
-Subject: [PATCH 09/33] MIPS: ralink: workaround DTB memory issue
+Subject: [PATCH 104/133] MIPS: ralink: workaround DTB memory issue
If the DTB is too big a bug happens on boot when init ram is freed.
This is a temporary fix until the real cause is found.
diff --git a/target/linux/ramips/patches-3.10/0105-MIPS-ralink-add-missing-clk_set_rate-to-clk.c.patch b/target/linux/ramips/patches-3.10/0105-MIPS-ralink-add-missing-clk_set_rate-to-clk.c.patch
new file mode 100644
index 0000000000..e9b30e03e3
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0105-MIPS-ralink-add-missing-clk_set_rate-to-clk.c.patch
@@ -0,0 +1,25 @@
+From 6f72aea69951479b7daad1d38b506ede4f8a1676 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 04:38:07 +0000
+Subject: [PATCH 105/133] MIPS: ralink: add missing clk_set_rate() to clk.c
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/clk.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/mips/ralink/clk.c
++++ b/arch/mips/ralink/clk.c
+@@ -56,6 +56,12 @@ unsigned long clk_get_rate(struct clk *c
+ }
+ EXPORT_SYMBOL_GPL(clk_get_rate);
+
++int clk_set_rate(struct clk *clk, unsigned long rate)
++{
++ return -1;
++}
++EXPORT_SYMBOL_GPL(clk_set_rate);
++
+ void __init plat_time_init(void)
+ {
+ struct clk *clk;
diff --git a/target/linux/ramips/patches-3.10/999-mt7620n.patch b/target/linux/ramips/patches-3.10/0106-MIPS-ralink-add-support-for-MT7620n.patch
similarity index 74%
rename from target/linux/ramips/patches-3.10/999-mt7620n.patch
rename to target/linux/ramips/patches-3.10/0106-MIPS-ralink-add-support-for-MT7620n.patch
index da5c6f9c7a..bb1ff7dc61 100644
--- a/target/linux/ramips/patches-3.10/999-mt7620n.patch
+++ b/target/linux/ramips/patches-3.10/0106-MIPS-ralink-add-support-for-MT7620n.patch
@@ -1,3 +1,16 @@
+From 45ba0675286e2a71f6a577833ab13b951bb7e31a Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 04:40:02 +0000
+Subject: [PATCH 106/133] MIPS: ralink: add support for MT7620n
+
+This is the small version of MT7620a.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ralink/mt7620.h | 7 ++-----
+ arch/mips/ralink/mt7620.c | 19 ++++++++++++-------
+ 2 files changed, 14 insertions(+), 12 deletions(-)
+
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -24,11 +24,8 @@
@@ -16,7 +29,7 @@
#define CHIP_REV_PKG_SHIFT 16
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
-@@ -167,22 +167,27 @@ void prom_soc_init(struct ralink_soc_inf
+@@ -226,22 +226,27 @@ void prom_soc_init(struct ralink_soc_inf
u32 cfg0;
u32 pmu0;
u32 pmu1;
diff --git a/target/linux/ramips/patches-3.10/0106-USB-dwc2.patch b/target/linux/ramips/patches-3.10/0106-USB-dwc2.patch
deleted file mode 100644
index 90e8ee5e6b..0000000000
--- a/target/linux/ramips/patches-3.10/0106-USB-dwc2.patch
+++ /dev/null
@@ -1,19 +0,0 @@
---- a/drivers/staging/dwc2/hcd.c
-+++ b/drivers/staging/dwc2/hcd.c
-@@ -47,6 +47,7 @@
- #include <linux/io.h>
- #include <linux/slab.h>
- #include <linux/usb.h>
-+#include <linux/reset.h>
-
- #include <linux/usb/hcd.h>
- #include <linux/usb/ch11.h>
-@@ -2712,6 +2713,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hso
-
- dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
-
-+ device_reset(hsotg->dev);
-+
- /*
- * Attempt to ensure this device is really a DWC_otg Controller.
- * Read and verify the GSNPSID register contents. The value should be
diff --git a/target/linux/ramips/patches-3.10/0107-MIPS-ralink-allow-manual-memory-override.patch b/target/linux/ramips/patches-3.10/0107-MIPS-ralink-allow-manual-memory-override.patch
new file mode 100644
index 0000000000..4fb2b2be37
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0107-MIPS-ralink-allow-manual-memory-override.patch
@@ -0,0 +1,45 @@
+From ee46d05eefefb0fb40b5682b4f6f3876b496044b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 04:40:48 +0000
+Subject: [PATCH 107/133] MIPS: ralink: allow manual memory override
+
+RT5350 relies on the bootloader setting up the memc correctly.
+On sme boards the setup is incorrect leading to 32 MB being available but only 16 being recognized. Allow these boards to manually override the memory range
+.
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/of.c | 16 +++++++++++++++-
+ 1 file changed, 15 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -77,6 +77,17 @@ void __init device_tree_init(void)
+ //free_bootmem(base, size);
+ }
+
++static int memory_dtb;
++
++static int __init early_init_dt_find_memory(unsigned long node, const char *uname,
++ int depth, void *data)
++{
++ if (depth == 1 && !strcmp(uname, "memory@0"))
++ memory_dtb = 1;
++
++ return 0;
++}
++
+ void __init plat_mem_setup(void)
+ {
+ set_io_port_base(KSEG1);
+@@ -87,7 +98,10 @@ void __init plat_mem_setup(void)
+ */
+ __dt_setup_arch(&__dtb_start);
+
+- if (soc_info.mem_size)
++ of_scan_flat_dt(early_init_dt_find_memory, NULL);
++ if (memory_dtb)
++ of_scan_flat_dt(early_init_dt_scan_memory, NULL);
++ else if (soc_info.mem_size)
+ add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
+ BOOT_MEM_RAM);
+ else
diff --git a/target/linux/ramips/patches-3.10/0121-MIPS-ralink-add-rt_sysc_m32-helper.patch b/target/linux/ramips/patches-3.10/0108-MIPS-ralink-add-rt_sysc_m32-helper.patch
similarity index 85%
rename from target/linux/ramips/patches-3.10/0121-MIPS-ralink-add-rt_sysc_m32-helper.patch
rename to target/linux/ramips/patches-3.10/0108-MIPS-ralink-add-rt_sysc_m32-helper.patch
index 915c5bed5c..6d9c0d3a5d 100644
--- a/target/linux/ramips/patches-3.10/0121-MIPS-ralink-add-rt_sysc_m32-helper.patch
+++ b/target/linux/ramips/patches-3.10/0108-MIPS-ralink-add-rt_sysc_m32-helper.patch
@@ -1,7 +1,7 @@
-From 3af962f91035ae4500e63c758c49f1c067bdae09 Mon Sep 17 00:00:00 2001
+From 1fe4d719d1c973c01f4b6a4c0de47bfac77e3eca Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 19 May 2013 00:42:23 +0200
-Subject: [PATCH 04/33] MIPS: ralink: add rt_sysc_m32 helper
+Subject: [PATCH 108/133] MIPS: ralink: add rt_sysc_m32 helper
Signed-off-by: John Crispin <blogic@openwrt.org>
---
diff --git a/target/linux/ramips/patches-3.10/0201-owrt-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on.patch b/target/linux/ramips/patches-3.10/0109-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on-time.patch
similarity index 98%
rename from target/linux/ramips/patches-3.10/0201-owrt-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on.patch
rename to target/linux/ramips/patches-3.10/0109-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on-time.patch
index ee4d72fcb5..193374e91c 100644
--- a/target/linux/ramips/patches-3.10/0201-owrt-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on.patch
+++ b/target/linux/ramips/patches-3.10/0109-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on-time.patch
@@ -1,8 +1,8 @@
-From daf08289dc0ac69af0d8293dacd5ca6291400593 Mon Sep 17 00:00:00 2001
+From ca21f813087ca5a8b02ec00efcd9c3f3fbf3bc1f Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 24 Mar 2013 17:17:17 +0100
-Subject: [PATCH 30/33] owrt: MIPS: ralink: add pseudo pwm led trigger based
- on timer0
+Subject: [PATCH 109/133] MIPS: ralink: add pseudo pwm led trigger based on
+ timer0
Signed-off-by: John Crispin <blogic@openwrt.org>
---
diff --git a/target/linux/ramips/patches-3.10/0110-MIPS-ralink-add-a-helper-for-reading-the-ECO-version.patch b/target/linux/ramips/patches-3.10/0110-MIPS-ralink-add-a-helper-for-reading-the-ECO-version.patch
new file mode 100644
index 0000000000..7a646400c4
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0110-MIPS-ralink-add-a-helper-for-reading-the-ECO-version.patch
@@ -0,0 +1,23 @@
+From f57edea9db0f7f437bc4f2ae408f6dd8bfbb9062 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 04:53:02 +0000
+Subject: [PATCH 110/133] MIPS: ralink: add a helper for reading the ECO
+ version
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ralink/mt7620.h | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -79,4 +79,9 @@
+ #define MT7620_GPIO_MODE_EPHY BIT(15)
+ #define MT7620_GPIO_MODE_WDT BIT(22)
+
++static inline int mt7620_get_eco(void)
++{
++ return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
++}
++
+ #endif
diff --git a/target/linux/ramips/patches-3.10/0300-DMA-add-rt2880-dma-engine.patch b/target/linux/ramips/patches-3.10/0111-DMA-ralink-add-rt2880-dma-engine.patch
similarity index 98%
rename from target/linux/ramips/patches-3.10/0300-DMA-add-rt2880-dma-engine.patch
rename to target/linux/ramips/patches-3.10/0111-DMA-ralink-add-rt2880-dma-engine.patch
index 7bddcaf2f9..2aafd00d19 100644
--- a/target/linux/ramips/patches-3.10/0300-DMA-add-rt2880-dma-engine.patch
+++ b/target/linux/ramips/patches-3.10/0111-DMA-ralink-add-rt2880-dma-engine.patch
@@ -1,14 +1,16 @@
-From 776726ff626249276936a7e1f865103ea4e1b7e9 Mon Sep 17 00:00:00 2001
+From 2d7e32d4825e20e9db4f0dff6b3e3c25c8c7ad7d Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 3 Dec 2013 17:05:05 +0100
-Subject: [PATCH] DMA: add rt2880 dma engine
+Subject: [PATCH 111/133] DMA: ralink: add rt2880 dma engine
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/dma/Kconfig | 6 +
drivers/dma/Makefile | 1 +
- drivers/dma/ralink-gdma.c | 596 +++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 603 insertions(+)
+ drivers/dma/dmaengine.c | 26 ++
+ drivers/dma/ralink-gdma.c | 577 +++++++++++++++++++++++++++++++++++++++++++++
+ include/linux/dmaengine.h | 1 +
+ 5 files changed, 611 insertions(+)
create mode 100644 drivers/dma/ralink-gdma.c
--- a/drivers/dma/Kconfig
@@ -26,6 +28,48 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
config DMA_ENGINE
bool
+--- a/drivers/dma/Makefile
++++ b/drivers/dma/Makefile
+@@ -38,3 +38,4 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
+ obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
+ obj-$(CONFIG_DMA_OMAP) += omap-dma.o
+ obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
++obj-$(CONFIG_DMA_RALINK) += ralink-gdma.o
+--- a/drivers/dma/dmaengine.c
++++ b/drivers/dma/dmaengine.c
+@@ -504,6 +504,32 @@ static struct dma_chan *private_candidat
+ }
+
+ /**
++ * dma_request_slave_channel - try to get specific channel exclusively
++ * @chan: target channel
++ */
++struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
++{
++ int err = -EBUSY;
++
++ /* lock against __dma_request_channel */
++ mutex_lock(&dma_list_mutex);
++
++ if (chan->client_count == 0) {
++ err = dma_chan_get(chan);
++ if (err)
++ pr_debug("%s: failed to get %s: (%d)\n",
++ __func__, dma_chan_name(chan), err);
++ } else
++ chan = NULL;
++
++ mutex_unlock(&dma_list_mutex);
++
++ return chan;
++}
++EXPORT_SYMBOL_GPL(dma_get_slave_channel);
++
++
++/**
+ * dma_request_channel - try to allocate an exclusive channel
+ * @mask: capabilities that the channel must satisfy
+ * @fn: optional callback to disposition available channels
--- /dev/null
+++ b/drivers/dma/ralink-gdma.c
@@ -0,0 +1,577 @@
@@ -606,41 +650,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
+MODULE_DESCRIPTION("GDMA4740 DMA driver");
+MODULE_LICENSE("GPLv2");
---- a/drivers/dma/dmaengine.c
-+++ b/drivers/dma/dmaengine.c
-@@ -504,6 +504,32 @@ static struct dma_chan *private_candidat
- }
-
- /**
-+ * dma_request_slave_channel - try to get specific channel exclusively
-+ * @chan: target channel
-+ */
-+struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
-+{
-+ int err = -EBUSY;
-+
-+ /* lock against __dma_request_channel */
-+ mutex_lock(&dma_list_mutex);
-+
-+ if (chan->client_count == 0) {
-+ err = dma_chan_get(chan);
-+ if (err)
-+ pr_debug("%s: failed to get %s: (%d)\n",
-+ __func__, dma_chan_name(chan), err);
-+ } else
-+ chan = NULL;
-+
-+ mutex_unlock(&dma_list_mutex);
-+
-+ return chan;
-+}
-+EXPORT_SYMBOL_GPL(dma_get_slave_channel);
-+
-+
-+/**
- * dma_request_channel - try to allocate an exclusive channel
- * @mask: capabilities that the channel must satisfy
- * @fn: optional callback to disposition available channels
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -999,6 +999,7 @@ static inline void dma_release_channel(s
@@ -651,10 +660,3 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
struct dma_chan *net_dma_find_channel(void);
#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
---- a/drivers/dma/Makefile
-+++ b/drivers/dma/Makefile
-@@ -38,3 +38,4 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
- obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
- obj-$(CONFIG_DMA_OMAP) += omap-dma.o
- obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
-+obj-$(CONFIG_DMA_RALINK) += ralink-gdma.o
diff --git a/target/linux/ramips/patches-3.10/0301-asoc-add-mt7620-support.patch b/target/linux/ramips/patches-3.10/0112-asoc-add-mt7620-support.patch
similarity index 97%
rename from target/linux/ramips/patches-3.10/0301-asoc-add-mt7620-support.patch
rename to target/linux/ramips/patches-3.10/0112-asoc-add-mt7620-support.patch
index c85f4177a0..469d2e404f 100644
--- a/target/linux/ramips/patches-3.10/0301-asoc-add-mt7620-support.patch
+++ b/target/linux/ramips/patches-3.10/0112-asoc-add-mt7620-support.patch
@@ -1,24 +1,42 @@
-From c72bc41d018519de5d63ec7790965fbf4605276a Mon Sep 17 00:00:00 2001
+From d4398d880eba386cb85d0a1a2ba39a336876dc0a Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 3 Dec 2013 20:18:13 +0100
-Subject: [PATCH] asoc: add mt7620 support
+Subject: [PATCH 112/133] asoc: add mt7620 support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
+ arch/mips/ralink/of.c | 2 +
sound/soc/Kconfig | 1 +
sound/soc/Makefile | 1 +
- sound/soc/ralink/Kconfig | 24 +++
- sound/soc/ralink/Makefile | 13 ++
- sound/soc/ralink/mt7620-i2s.c | 429 ++++++++++++++++++++++++++++++++++++++
- sound/soc/ralink/mt7620-pcm.c | 77 +++++++
- sound/soc/ralink/mt7620-wm8960.c | 124 +++++++++++
- 7 files changed, 669 insertions(+)
+ sound/soc/ralink/Kconfig | 15 ++
+ sound/soc/ralink/Makefile | 11 +
+ sound/soc/ralink/mt7620-i2s.c | 466 ++++++++++++++++++++++++++++++++++++++
+ sound/soc/ralink/mt7620-wm8960.c | 125 ++++++++++
+ sound/soc/soc-io.c | 10 -
+ 8 files changed, 621 insertions(+), 10 deletions(-)
create mode 100644 sound/soc/ralink/Kconfig
create mode 100644 sound/soc/ralink/Makefile
create mode 100644 sound/soc/ralink/mt7620-i2s.c
- create mode 100644 sound/soc/ralink/mt7620-pcm.c
create mode 100644 sound/soc/ralink/mt7620-wm8960.c
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -15,6 +15,7 @@
+ #include <linux/of_fdt.h>
+ #include <linux/kernel.h>
+ #include <linux/bootmem.h>
++#include <linux/module.h>
+ #include <linux/of_platform.h>
+ #include <linux/of_address.h>
+
+@@ -25,6 +26,7 @@
+ #include "common.h"
+
+ __iomem void *rt_sysc_membase;
++EXPORT_SYMBOL(rt_sysc_membase);
+ __iomem void *rt_memc_membase;
+
+ extern struct boot_param_header __dtb_start;
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -48,6 +48,7 @@ source "sound/soc/kirkwood/Kconfig"
@@ -668,24 +686,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+MODULE_DESCRIPTION("ALSA SoC QI LB60 Audio support");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:qi-lb60-audio");
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -15,6 +15,7 @@
- #include <linux/of_fdt.h>
- #include <linux/kernel.h>
- #include <linux/bootmem.h>
-+#include <linux/module.h>
- #include <linux/of_platform.h>
- #include <linux/of_address.h>
-
-@@ -25,6 +26,7 @@
- #include "common.h"
-
- __iomem void *rt_sysc_membase;
-+EXPORT_SYMBOL(rt_sysc_membase);
- __iomem void *rt_memc_membase;
-
- extern struct boot_param_header __dtb_start;
--- a/sound/soc/soc-io.c
+++ b/sound/soc/soc-io.c
@@ -19,7 +19,6 @@
diff --git a/target/linux/ramips/patches-3.10/0122-pinmux.patch b/target/linux/ramips/patches-3.10/0113-pinctrl-ralink-add-pinctrl-driver.patch
similarity index 96%
rename from target/linux/ramips/patches-3.10/0122-pinmux.patch
rename to target/linux/ramips/patches-3.10/0113-pinctrl-ralink-add-pinctrl-driver.patch
index 20fc4286f2..b3750590e7 100644
--- a/target/linux/ramips/patches-3.10/0122-pinmux.patch
+++ b/target/linux/ramips/patches-3.10/0113-pinctrl-ralink-add-pinctrl-driver.patch
@@ -1,17 +1,24 @@
-From d59fe652e3674e98caa688b4ddc9308007267adc Mon Sep 17 00:00:00 2001
+From 47bbf432252b39361728c7685292dc9f889e6537 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 19 Aug 2013 13:49:52 +0200
-Subject: [PATCH] pinctrl: ralink; add pinctrl driver
+Subject: [PATCH 113/133] pinctrl: ralink: add pinctrl driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---
- arch/mips/Kconfig | 2 +
- arch/mips/ralink/common.h | 21 +--
- arch/mips/ralink/dts/mt7620a.dtsi | 7 +
- drivers/pinctrl/Kconfig | 5 +
- drivers/pinctrl/Makefile | 1 +
- drivers/pinctrl/pinctrl-rt2880.c | 368 +++++++++++++++++++++++++++++++++++++
- 6 files changed, 385 insertions(+), 19 deletions(-)
+ arch/mips/Kconfig | 2 +
+ arch/mips/include/asm/mach-ralink/mt7620.h | 41 ++-
+ arch/mips/include/asm/mach-ralink/pinmux.h | 53 ++++
+ arch/mips/include/asm/mach-ralink/rt305x.h | 34 +-
+ arch/mips/include/asm/mach-ralink/rt3883.h | 16 +-
+ arch/mips/ralink/common.h | 19 --
+ arch/mips/ralink/mt7620.c | 161 ++++------
+ arch/mips/ralink/rt305x.c | 146 ++++-----
+ arch/mips/ralink/rt3883.c | 173 +++--------
+ drivers/pinctrl/Kconfig | 5 +
+ drivers/pinctrl/Makefile | 1 +
+ drivers/pinctrl/pinctrl-rt2880.c | 467 ++++++++++++++++++++++++++++
+ 12 files changed, 740 insertions(+), 378 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-ralink/pinmux.h
create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
--- a/arch/mips/Kconfig
@@ -25,1278 +32,1280 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
config SGI_IP22
bool "SGI IP22 (Indy/Indigo2)"
---- a/drivers/pinctrl/Kconfig
-+++ b/drivers/pinctrl/Kconfig
-@@ -114,6 +114,11 @@ config PINCTRL_LANTIQ
- select PINMUX
- select PINCONF
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -56,7 +56,6 @@
+ #define MT7620_DDR2_SIZE_MIN 32
+ #define MT7620_DDR2_SIZE_MAX 256
-+config PINCTRL_RT2880
-+ bool
-+ depends on RALINK
-+ select PINMUX
+-#define MT7620_GPIO_MODE_I2C BIT(0)
+ #define MT7620_GPIO_MODE_UART0_SHIFT 2
+ #define MT7620_GPIO_MODE_UART0_MASK 0x7
+ #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
+@@ -68,16 +67,36 @@
+ #define MT7620_GPIO_MODE_GPIO_UARTF 0x5
+ #define MT7620_GPIO_MODE_GPIO_I2S 0x6
+ #define MT7620_GPIO_MODE_GPIO 0x7
+-#define MT7620_GPIO_MODE_UART1 BIT(5)
+-#define MT7620_GPIO_MODE_MDIO BIT(8)
+-#define MT7620_GPIO_MODE_RGMII1 BIT(9)
+-#define MT7620_GPIO_MODE_RGMII2 BIT(10)
+-#define MT7620_GPIO_MODE_SPI BIT(11)
+-#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
+-#define MT7620_GPIO_MODE_WLED BIT(13)
+-#define MT7620_GPIO_MODE_JTAG BIT(15)
+-#define MT7620_GPIO_MODE_EPHY BIT(15)
+-#define MT7620_GPIO_MODE_WDT BIT(22)
+
- config PINCTRL_FALCON
- bool
- depends on SOC_FALCON
---- a/drivers/pinctrl/Makefile
-+++ b/drivers/pinctrl/Makefile
-@@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinc
- obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
- obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
- obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
-+obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
++#define MT7620_GPIO_MODE_NAND 0
++#define MT7620_GPIO_MODE_SD 1
++#define MT7620_GPIO_MODE_ND_SD_GPIO 2
++#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
++#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
++
++#define MT7620_GPIO_MODE_PCIE_RST 0
++#define MT7620_GPIO_MODE_PCIE_REF 1
++#define MT7620_GPIO_MODE_PCIE_GPIO 2
++#define MT7620_GPIO_MODE_PCIE_MASK 0x3
++#define MT7620_GPIO_MODE_PCIE_SHIFT 16
++
++#define MT7620_GPIO_MODE_WDT_RST 0
++#define MT7620_GPIO_MODE_WDT_REF 1
++#define MT7620_GPIO_MODE_WDT_GPIO 2
++#define MT7620_GPIO_MODE_WDT_MASK 0x3
++#define MT7620_GPIO_MODE_WDT_SHIFT 21
++
++#define MT7620_GPIO_MODE_I2C 0
++#define MT7620_GPIO_MODE_UART1 5
++#define MT7620_GPIO_MODE_MDIO 8
++#define MT7620_GPIO_MODE_RGMII1 9
++#define MT7620_GPIO_MODE_RGMII2 10
++#define MT7620_GPIO_MODE_SPI 11
++#define MT7620_GPIO_MODE_SPI_REF_CLK 12
++#define MT7620_GPIO_MODE_WLED 13
++#define MT7620_GPIO_MODE_JTAG 15
++#define MT7620_GPIO_MODE_EPHY 15
++#define MT7620_GPIO_MODE_PA 20
- obj-$(CONFIG_PLAT_ORION) += mvebu/
- obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
+ static inline int mt7620_get_eco(void)
+ {
--- /dev/null
-+++ b/drivers/pinctrl/pinctrl-rt2880.c
-@@ -0,0 +1,466 @@
++++ b/arch/mips/include/asm/mach-ralink/pinmux.h
+@@ -0,0 +1,53 @@
+/*
-+ * linux/drivers/pinctrl/pinctrl-rt2880.c
-+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ *
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ */
+
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/io.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/of.h>
-+#include <linux/pinctrl/pinctrl.h>
-+#include <linux/pinctrl/pinconf.h>
-+#include <linux/pinctrl/pinmux.h>
-+#include <linux/pinctrl/consumer.h>
-+#include <linux/pinctrl/machine.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+#include <asm/mach-ralink/pinmux.h>
-+#include <asm/mach-ralink/mt7620.h>
++#ifndef _RT288X_PINMUX_H__
++#define _RT288X_PINMUX_H__
+
-+#include "core.h"
++#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
++#define GRP(_name, _func, _mask, _shift) \
++ { .name = _name, .mask = _mask, .shift = _shift, \
++ .func = _func, .gpio = _mask, \
++ .func_count = ARRAY_SIZE(_func) }
+
-+#define SYSC_REG_GPIO_MODE 0x60
++#define GRP_G(_name, _func, _mask, _gpio, _shift) \
++ { .name = _name, .mask = _mask, .shift = _shift, \
++ .func = _func, .gpio = _gpio, \
++ .func_count = ARRAY_SIZE(_func) }
+
-+struct rt2880_priv {
-+ struct device *dev;
++struct rt2880_pmx_group;
+
-+ struct pinctrl_pin_desc *pads;
-+ struct pinctrl_desc *desc;
++struct rt2880_pmx_func {
++ const char *name;
++ const char value;
+
-+ struct rt2880_pmx_func **func;
-+ int func_count;
++ int pin_first;
++ int pin_count;
++ int *pins;
+
-+ struct rt2880_pmx_group *groups;
-+ const char **group_names;
++ int *groups;
+ int group_count;
+
-+ uint8_t *gpio;
-+ int max_pins;
++ int enabled;
+};
+
-+struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
-+
-+static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ return p->group_count;
-+}
-+
-+static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
-+ unsigned group)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (group >= p->group_count)
-+ return NULL;
-+
-+ return p->group_names[group];
-+}
++struct rt2880_pmx_group {
++ const char *name;
++ int enabled;
+
-+static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
-+ unsigned group,
-+ const unsigned **pins,
-+ unsigned *num_pins)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
++ const u32 shift;
++ const char mask;
++ const char gpio;
+
-+ if (group >= p->group_count)
-+ return -EINVAL;
++ struct rt2880_pmx_func *func;
++ int func_count;
++};
+
-+ *pins = p->groups[group].func[0].pins;
-+ *num_pins = p->groups[group].func[0].pin_count;
++extern struct rt2880_pmx_group *rt2880_pinmux_data;
+
-+ return 0;
-+}
++#endif
+--- a/arch/mips/include/asm/mach-ralink/rt305x.h
++++ b/arch/mips/include/asm/mach-ralink/rt305x.h
+@@ -125,24 +125,28 @@ static inline int soc_is_rt5350(void)
+ #define RT305X_GPIO_GE0_TXD0 40
+ #define RT305X_GPIO_GE0_RXCLK 51
+
+-#define RT305X_GPIO_MODE_I2C BIT(0)
+-#define RT305X_GPIO_MODE_SPI BIT(1)
+ #define RT305X_GPIO_MODE_UART0_SHIFT 2
+ #define RT305X_GPIO_MODE_UART0_MASK 0x7
+ #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
+-#define RT305X_GPIO_MODE_UARTF 0x0
+-#define RT305X_GPIO_MODE_PCM_UARTF 0x1
+-#define RT305X_GPIO_MODE_PCM_I2S 0x2
+-#define RT305X_GPIO_MODE_I2S_UARTF 0x3
+-#define RT305X_GPIO_MODE_PCM_GPIO 0x4
+-#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
+-#define RT305X_GPIO_MODE_GPIO_I2S 0x6
+-#define RT305X_GPIO_MODE_GPIO 0x7
+-#define RT305X_GPIO_MODE_UART1 BIT(5)
+-#define RT305X_GPIO_MODE_JTAG BIT(6)
+-#define RT305X_GPIO_MODE_MDIO BIT(7)
+-#define RT305X_GPIO_MODE_SDRAM BIT(8)
+-#define RT305X_GPIO_MODE_RGMII BIT(9)
++#define RT305X_GPIO_MODE_UARTF 0
++#define RT305X_GPIO_MODE_PCM_UARTF 1
++#define RT305X_GPIO_MODE_PCM_I2S 2
++#define RT305X_GPIO_MODE_I2S_UARTF 3
++#define RT305X_GPIO_MODE_PCM_GPIO 4
++#define RT305X_GPIO_MODE_GPIO_UARTF 5
++#define RT305X_GPIO_MODE_GPIO_I2S 6
++#define RT305X_GPIO_MODE_GPIO 7
+
-+static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
-+ struct pinctrl_map *map, unsigned num_maps)
-+{
-+ int i;
++#define RT305X_GPIO_MODE_I2C 0
++#define RT305X_GPIO_MODE_SPI 1
++#define RT305X_GPIO_MODE_UART1 5
++#define RT305X_GPIO_MODE_JTAG 6
++#define RT305X_GPIO_MODE_MDIO 7
++#define RT305X_GPIO_MODE_SDRAM 8
++#define RT305X_GPIO_MODE_RGMII 9
++#define RT5350_GPIO_MODE_PHY_LED 14
++#define RT3352_GPIO_MODE_LNA 18
++#define RT3352_GPIO_MODE_PA 20
+
+ #define RT3352_SYSC_REG_SYSCFG0 0x010
+ #define RT3352_SYSC_REG_SYSCFG1 0x014
+--- a/arch/mips/include/asm/mach-ralink/rt3883.h
++++ b/arch/mips/include/asm/mach-ralink/rt3883.h
+@@ -112,8 +112,6 @@
+ #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
+ #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
+
+-#define RT3883_GPIO_MODE_I2C BIT(0)
+-#define RT3883_GPIO_MODE_SPI BIT(1)
+ #define RT3883_GPIO_MODE_UART0_SHIFT 2
+ #define RT3883_GPIO_MODE_UART0_MASK 0x7
+ #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
+@@ -125,11 +123,15 @@
+ #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
+ #define RT3883_GPIO_MODE_GPIO_I2S 0x6
+ #define RT3883_GPIO_MODE_GPIO 0x7
+-#define RT3883_GPIO_MODE_UART1 BIT(5)
+-#define RT3883_GPIO_MODE_JTAG BIT(6)
+-#define RT3883_GPIO_MODE_MDIO BIT(7)
+-#define RT3883_GPIO_MODE_GE1 BIT(9)
+-#define RT3883_GPIO_MODE_GE2 BIT(10)
+
-+ for (i = 0; i < num_maps; i++)
-+ if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
-+ map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
-+ kfree(map[i].data.configs.configs);
-+ kfree(map);
-+}
++#define RT3883_GPIO_MODE_I2C 0
++#define RT3883_GPIO_MODE_SPI 1
++#define RT3883_GPIO_MODE_UART1 5
++#define RT3883_GPIO_MODE_JTAG 6
++#define RT3883_GPIO_MODE_MDIO 7
++#define RT3883_GPIO_MODE_GE1 9
++#define RT3883_GPIO_MODE_GE2 10
+
-+static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
-+ struct seq_file *s,
-+ unsigned offset)
-+{
-+ seq_printf(s, "ralink pio");
-+}
-+
-+static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
-+ struct device_node *np,
-+ struct pinctrl_map **map)
-+{
-+ const char *function;
-+ int func = of_property_read_string(np, "ralink,function", &function);
-+ int grps = of_property_count_strings(np, "ralink,group");
-+ int i;
-+
-+ if (func || !grps)
-+ return;
-+
-+ for (i = 0; i < grps; i++) {
-+ const char *group;
-+
-+ of_property_read_string_index(np, "ralink,group", i, &group);
-+
-+ (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
-+ (*map)->name = function;
-+ (*map)->data.mux.group = group;
-+ (*map)->data.mux.function = function;
-+ (*map)++;
-+ }
-+}
-+
-+static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
-+ struct device_node *np_config,
-+ struct pinctrl_map **map,
-+ unsigned *num_maps)
-+{
-+ int max_maps = 0;
-+ struct pinctrl_map *tmp;
-+ struct device_node *np;
-+
-+ for_each_child_of_node(np_config, np) {
-+ int ret = of_property_count_strings(np, "ralink,group");
-+
-+ if (ret >= 0)
-+ max_maps += ret;
-+ }
-+
-+ if (!max_maps)
-+ return max_maps;
-+
-+ *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
-+ if (!*map)
-+ return -ENOMEM;
-+
-+ tmp = *map;
-+
-+ for_each_child_of_node(np_config, np)
-+ rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
-+ *num_maps = max_maps;
-+
-+ return 0;
-+}
+ #define RT3883_GPIO_MODE_PCI_SHIFT 11
+ #define RT3883_GPIO_MODE_PCI_MASK 0x7
+ #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
+--- a/arch/mips/ralink/common.h
++++ b/arch/mips/ralink/common.h
+@@ -11,25 +11,6 @@
+
+ #define RAMIPS_SYS_TYPE_LEN 32
+
+-struct ralink_pinmux_grp {
+- const char *name;
+- u32 mask;
+- int gpio_first;
+- int gpio_last;
+-};
+-
+-struct ralink_pinmux {
+- struct ralink_pinmux_grp *mode;
+- struct ralink_pinmux_grp *uart;
+- int uart_shift;
+- u32 uart_mask;
+- void (*wdt_reset)(void);
+- struct ralink_pinmux_grp *pci;
+- int pci_shift;
+- u32 pci_mask;
+-};
+-extern struct ralink_pinmux rt_gpio_pinmux;
+-
+ struct ralink_soc_info {
+ unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
+ unsigned char *compatible;
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -17,6 +17,7 @@
+ #include <asm/mipsregs.h>
+ #include <asm/mach-ralink/ralink_regs.h>
+ #include <asm/mach-ralink/mt7620.h>
++#include <asm/mach-ralink/pinmux.h>
+
+ #include "common.h"
+
+@@ -48,118 +49,58 @@ static int dram_type;
+ /* the pll dividers */
+ static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
+
+-static struct ralink_pinmux_grp mode_mux[] = {
+- {
+- .name = "i2c",
+- .mask = MT7620_GPIO_MODE_I2C,
+- .gpio_first = 1,
+- .gpio_last = 2,
+- }, {
+- .name = "spi",
+- .mask = MT7620_GPIO_MODE_SPI,
+- .gpio_first = 3,
+- .gpio_last = 6,
+- }, {
+- .name = "uartlite",
+- .mask = MT7620_GPIO_MODE_UART1,
+- .gpio_first = 15,
+- .gpio_last = 16,
+- }, {
+- .name = "wdt",
+- .mask = MT7620_GPIO_MODE_WDT,
+- .gpio_first = 17,
+- .gpio_last = 17,
+- }, {
+- .name = "mdio",
+- .mask = MT7620_GPIO_MODE_MDIO,
+- .gpio_first = 22,
+- .gpio_last = 23,
+- }, {
+- .name = "rgmii1",
+- .mask = MT7620_GPIO_MODE_RGMII1,
+- .gpio_first = 24,
+- .gpio_last = 35,
+- }, {
+- .name = "spi refclk",
+- .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
+- .gpio_first = 37,
+- .gpio_last = 39,
+- }, {
+- .name = "jtag",
+- .mask = MT7620_GPIO_MODE_JTAG,
+- .gpio_first = 40,
+- .gpio_last = 44,
+- }, {
+- /* shared lines with jtag */
+- .name = "ephy",
+- .mask = MT7620_GPIO_MODE_EPHY,
+- .gpio_first = 40,
+- .gpio_last = 44,
+- }, {
+- .name = "nand",
+- .mask = MT7620_GPIO_MODE_JTAG,
+- .gpio_first = 45,
+- .gpio_last = 59,
+- }, {
+- .name = "rgmii2",
+- .mask = MT7620_GPIO_MODE_RGMII2,
+- .gpio_first = 60,
+- .gpio_last = 71,
+- }, {
+- .name = "wled",
+- .mask = MT7620_GPIO_MODE_WLED,
+- .gpio_first = 72,
+- .gpio_last = 72,
+- }, {0}
++static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
++static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
++static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
++static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
++static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
++static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
++static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
++static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
++static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
++static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
++static struct rt2880_pmx_func uartf_grp[] = {
++ FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
++ FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
++ FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
++ FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
++ FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
++ FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
++ FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
+ };
+-
+-static struct ralink_pinmux_grp uart_mux[] = {
+- {
+- .name = "uartf",
+- .mask = MT7620_GPIO_MODE_UARTF,
+- .gpio_first = 7,
+- .gpio_last = 14,
+- }, {
+- .name = "pcm uartf",
+- .mask = MT7620_GPIO_MODE_PCM_UARTF,
+- .gpio_first = 7,
+- .gpio_last = 14,
+- }, {
+- .name = "pcm i2s",
+- .mask = MT7620_GPIO_MODE_PCM_I2S,
+- .gpio_first = 7,
+- .gpio_last = 14,
+- }, {
+- .name = "i2s uartf",
+- .mask = MT7620_GPIO_MODE_I2S_UARTF,
+- .gpio_first = 7,
+- .gpio_last = 14,
+- }, {
+- .name = "pcm gpio",
+- .mask = MT7620_GPIO_MODE_PCM_GPIO,
+- .gpio_first = 11,
+- .gpio_last = 14,
+- }, {
+- .name = "gpio uartf",
+- .mask = MT7620_GPIO_MODE_GPIO_UARTF,
+- .gpio_first = 7,
+- .gpio_last = 10,
+- }, {
+- .name = "gpio i2s",
+- .mask = MT7620_GPIO_MODE_GPIO_I2S,
+- .gpio_first = 7,
+- .gpio_last = 10,
+- }, {
+- .name = "gpio",
+- .mask = MT7620_GPIO_MODE_GPIO,
+- }, {0}
++static struct rt2880_pmx_func wdt_grp[] = {
++ FUNC("wdt rst", 0, 17, 1),
++ FUNC("wdt refclk", 0, 17, 1),
++ };
++static struct rt2880_pmx_func pcie_rst_grp[] = {
++ FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
++ FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
++};
++static struct rt2880_pmx_func nd_sd_grp[] = {
++ FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
++ FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
+ };
+
+-struct ralink_pinmux rt_gpio_pinmux = {
+- .mode = mode_mux,
+- .uart = uart_mux,
+- .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
+- .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
++static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
++ GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
++ GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
++ MT7620_GPIO_MODE_UART0_SHIFT),
++ GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
++ GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
++ GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
++ MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
++ GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
++ GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
++ GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
++ GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
++ MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
++ GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
++ MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
++ GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
++ GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
++ GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
++ GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
++ { 0 }
+ };
+
+ void __init ralink_clk_init(void)
+@@ -286,4 +227,6 @@ void prom_soc_init(struct ralink_soc_inf
+ (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
+ pr_info("Digital PMU set to %s control\n",
+ (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
+
-+static const struct pinctrl_ops rt2880_pctrl_ops = {
-+ .get_groups_count = rt2880_get_group_count,
-+ .get_group_name = rt2880_get_group_name,
-+ .get_group_pins = rt2880_get_group_pins,
-+ .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
-+ .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
-+ .dt_free_map = rt2880_pinctrl_dt_free_map,
++ rt2880_pinmux_data = mt7620a_pinmux_data;
+ }
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -17,90 +17,71 @@
+ #include <asm/mipsregs.h>
+ #include <asm/mach-ralink/ralink_regs.h>
+ #include <asm/mach-ralink/rt305x.h>
++#include <asm/mach-ralink/pinmux.h>
+
+ #include "common.h"
+
+ enum rt305x_soc_type rt305x_soc;
+
+-static struct ralink_pinmux_grp mode_mux[] = {
+- {
+- .name = "i2c",
+- .mask = RT305X_GPIO_MODE_I2C,
+- .gpio_first = RT305X_GPIO_I2C_SD,
+- .gpio_last = RT305X_GPIO_I2C_SCLK,
+- }, {
+- .name = "spi",
+- .mask = RT305X_GPIO_MODE_SPI,
+- .gpio_first = RT305X_GPIO_SPI_EN,
+- .gpio_last = RT305X_GPIO_SPI_CLK,
+- }, {
+- .name = "uartlite",
+- .mask = RT305X_GPIO_MODE_UART1,
+- .gpio_first = RT305X_GPIO_UART1_TXD,
+- .gpio_last = RT305X_GPIO_UART1_RXD,
+- }, {
+- .name = "jtag",
+- .mask = RT305X_GPIO_MODE_JTAG,
+- .gpio_first = RT305X_GPIO_JTAG_TDO,
+- .gpio_last = RT305X_GPIO_JTAG_TDI,
+- }, {
+- .name = "mdio",
+- .mask = RT305X_GPIO_MODE_MDIO,
+- .gpio_first = RT305X_GPIO_MDIO_MDC,
+- .gpio_last = RT305X_GPIO_MDIO_MDIO,
+- }, {
+- .name = "sdram",
+- .mask = RT305X_GPIO_MODE_SDRAM,
+- .gpio_first = RT305X_GPIO_SDRAM_MD16,
+- .gpio_last = RT305X_GPIO_SDRAM_MD31,
+- }, {
+- .name = "rgmii",
+- .mask = RT305X_GPIO_MODE_RGMII,
+- .gpio_first = RT305X_GPIO_GE0_TXD0,
+- .gpio_last = RT305X_GPIO_GE0_RXCLK,
+- }, {0}
++static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
++static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
++static struct rt2880_pmx_func uartf_func[] = {
++ FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
++ FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
++ FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
++ FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
++ FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
++ FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
++ FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
+};
++static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
++static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
++static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
++static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
++static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
++static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) };
++static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
++static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
++static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
++static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
+
-+static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ return p->func_count;
-+}
-+
-+static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
-+ unsigned func)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ return p->func[func]->name;
-+}
-+
-+static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
-+ unsigned func,
-+ const char * const **groups,
-+ unsigned * const num_groups)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (p->func[func]->group_count == 1)
-+ *groups = &p->group_names[p->func[func]->groups[0]];
-+ else
-+ *groups = p->group_names;
-+
-+ *num_groups = p->func[func]->group_count;
-+
-+ return 0;
-+}
-+
-+static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
-+ unsigned func,
-+ unsigned group)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
-+ u32 mode = 0;
-+
-+ /* dont allow double use */
-+ if (p->groups[group].enabled) {
-+ dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
-+ return -EBUSY;
-+ }
-+
-+ p->groups[group].enabled = 1;
-+ p->func[func]->enabled = 1;
++static struct rt2880_pmx_group rt3050_pinmux_data[] = {
++ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
++ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
++ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
++ RT305X_GPIO_MODE_UART0_SHIFT),
++ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
++ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
++ GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
++ GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
++ GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
++ { 0 }
++};
+
-+ mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
-+ mode &= ~(p->groups[group].mask << p->groups[group].shift);
++static struct rt2880_pmx_group rt3352_pinmux_data[] = {
++ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
++ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
++ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
++ RT305X_GPIO_MODE_UART0_SHIFT),
++ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
++ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
++ GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
++ GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
++ GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
++ GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
++ GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
++ { 0 }
+ };
+
+-static struct ralink_pinmux_grp uart_mux[] = {
+- {
+- .name = "uartf",
+- .mask = RT305X_GPIO_MODE_UARTF,
+- .gpio_first = RT305X_GPIO_7,
+- .gpio_last = RT305X_GPIO_14,
+- }, {
+- .name = "pcm uartf",
+- .mask = RT305X_GPIO_MODE_PCM_UARTF,
+- .gpio_first = RT305X_GPIO_7,
+- .gpio_last = RT305X_GPIO_14,
+- }, {
+- .name = "pcm i2s",
+- .mask = RT305X_GPIO_MODE_PCM_I2S,
+- .gpio_first = RT305X_GPIO_7,
+- .gpio_last = RT305X_GPIO_14,
+- }, {
+- .name = "i2s uartf",
+- .mask = RT305X_GPIO_MODE_I2S_UARTF,
+- .gpio_first = RT305X_GPIO_7,
+- .gpio_last = RT305X_GPIO_14,
+- }, {
+- .name = "pcm gpio",
+- .mask = RT305X_GPIO_MODE_PCM_GPIO,
+- .gpio_first = RT305X_GPIO_10,
+- .gpio_last = RT305X_GPIO_14,
+- }, {
+- .name = "gpio uartf",
+- .mask = RT305X_GPIO_MODE_GPIO_UARTF,
+- .gpio_first = RT305X_GPIO_7,
+- .gpio_last = RT305X_GPIO_10,
+- }, {
+- .name = "gpio i2s",
+- .mask = RT305X_GPIO_MODE_GPIO_I2S,
+- .gpio_first = RT305X_GPIO_7,
+- .gpio_last = RT305X_GPIO_10,
+- }, {
+- .name = "gpio",
+- .mask = RT305X_GPIO_MODE_GPIO,
+- }, {0}
++static struct rt2880_pmx_group rt5350_pinmux_data[] = {
++ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
++ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
++ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
++ RT305X_GPIO_MODE_UART0_SHIFT),
++ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
++ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
++ GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
++ { 0 }
+ };
+
+ static void rt305x_wdt_reset(void)
+@@ -114,14 +95,6 @@ static void rt305x_wdt_reset(void)
+ rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
+ }
+
+-struct ralink_pinmux rt_gpio_pinmux = {
+- .mode = mode_mux,
+- .uart = uart_mux,
+- .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
+- .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
+- .wdt_reset = rt305x_wdt_reset,
+-};
+-
+ static unsigned long rt5350_get_mem_size(void)
+ {
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
+@@ -290,11 +263,14 @@ void prom_soc_init(struct ralink_soc_inf
+ soc_info->mem_base = RT305X_SDRAM_BASE;
+ if (soc_is_rt5350()) {
+ soc_info->mem_size = rt5350_get_mem_size();
++ rt2880_pinmux_data = rt5350_pinmux_data;
+ } else if (soc_is_rt305x() || soc_is_rt3350()) {
+ soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
+ soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
++ rt2880_pinmux_data = rt3050_pinmux_data;
+ } else if (soc_is_rt3352()) {
+ soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
+ soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
++ rt2880_pinmux_data = rt3352_pinmux_data;
+ }
+ }
+--- a/arch/mips/ralink/rt3883.c
++++ b/arch/mips/ralink/rt3883.c
+@@ -17,132 +17,50 @@
+ #include <asm/mipsregs.h>
+ #include <asm/mach-ralink/ralink_regs.h>
+ #include <asm/mach-ralink/rt3883.h>
++#include <asm/mach-ralink/pinmux.h>
+
+ #include "common.h"
+
+-static struct ralink_pinmux_grp mode_mux[] = {
+- {
+- .name = "i2c",
+- .mask = RT3883_GPIO_MODE_I2C,
+- .gpio_first = RT3883_GPIO_I2C_SD,
+- .gpio_last = RT3883_GPIO_I2C_SCLK,
+- }, {
+- .name = "spi",
+- .mask = RT3883_GPIO_MODE_SPI,
+- .gpio_first = RT3883_GPIO_SPI_CS0,
+- .gpio_last = RT3883_GPIO_SPI_MISO,
+- }, {
+- .name = "uartlite",
+- .mask = RT3883_GPIO_MODE_UART1,
+- .gpio_first = RT3883_GPIO_UART1_TXD,
+- .gpio_last = RT3883_GPIO_UART1_RXD,
+- }, {
+- .name = "jtag",
+- .mask = RT3883_GPIO_MODE_JTAG,
+- .gpio_first = RT3883_GPIO_JTAG_TDO,
+- .gpio_last = RT3883_GPIO_JTAG_TCLK,
+- }, {
+- .name = "mdio",
+- .mask = RT3883_GPIO_MODE_MDIO,
+- .gpio_first = RT3883_GPIO_MDIO_MDC,
+- .gpio_last = RT3883_GPIO_MDIO_MDIO,
+- }, {
+- .name = "ge1",
+- .mask = RT3883_GPIO_MODE_GE1,
+- .gpio_first = RT3883_GPIO_GE1_TXD0,
+- .gpio_last = RT3883_GPIO_GE1_RXCLK,
+- }, {
+- .name = "ge2",
+- .mask = RT3883_GPIO_MODE_GE2,
+- .gpio_first = RT3883_GPIO_GE2_TXD0,
+- .gpio_last = RT3883_GPIO_GE2_RXCLK,
+- }, {
+- .name = "pci",
+- .mask = RT3883_GPIO_MODE_PCI,
+- .gpio_first = RT3883_GPIO_PCI_AD0,
+- .gpio_last = RT3883_GPIO_PCI_AD31,
+- }, {
+- .name = "lna a",
+- .mask = RT3883_GPIO_MODE_LNA_A,
+- .gpio_first = RT3883_GPIO_LNA_PE_A0,
+- .gpio_last = RT3883_GPIO_LNA_PE_A2,
+- }, {
+- .name = "lna g",
+- .mask = RT3883_GPIO_MODE_LNA_G,
+- .gpio_first = RT3883_GPIO_LNA_PE_G0,
+- .gpio_last = RT3883_GPIO_LNA_PE_G2,
+- }, {0}
++static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
++static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
++static struct rt2880_pmx_func uartf_func[] = {
++ FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
++ FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
++ FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
++ FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
++ FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
++ FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
++ FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
+ };
+-
+-static struct ralink_pinmux_grp uart_mux[] = {
+- {
+- .name = "uartf",
+- .mask = RT3883_GPIO_MODE_UARTF,
+- .gpio_first = RT3883_GPIO_7,
+- .gpio_last = RT3883_GPIO_14,
+- }, {
+- .name = "pcm uartf",
+- .mask = RT3883_GPIO_MODE_PCM_UARTF,
+- .gpio_first = RT3883_GPIO_7,
+- .gpio_last = RT3883_GPIO_14,
+- }, {
+- .name = "pcm i2s",
+- .mask = RT3883_GPIO_MODE_PCM_I2S,
+- .gpio_first = RT3883_GPIO_7,
+- .gpio_last = RT3883_GPIO_14,
+- }, {
+- .name = "i2s uartf",
+- .mask = RT3883_GPIO_MODE_I2S_UARTF,
+- .gpio_first = RT3883_GPIO_7,
+- .gpio_last = RT3883_GPIO_14,
+- }, {
+- .name = "pcm gpio",
+- .mask = RT3883_GPIO_MODE_PCM_GPIO,
+- .gpio_first = RT3883_GPIO_11,
+- .gpio_last = RT3883_GPIO_14,
+- }, {
+- .name = "gpio uartf",
+- .mask = RT3883_GPIO_MODE_GPIO_UARTF,
+- .gpio_first = RT3883_GPIO_7,
+- .gpio_last = RT3883_GPIO_10,
+- }, {
+- .name = "gpio i2s",
+- .mask = RT3883_GPIO_MODE_GPIO_I2S,
+- .gpio_first = RT3883_GPIO_7,
+- .gpio_last = RT3883_GPIO_10,
+- }, {
+- .name = "gpio",
+- .mask = RT3883_GPIO_MODE_GPIO,
+- }, {0}
++static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
++static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
++static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
++static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
++static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
++static struct rt2880_pmx_func pci_func[] = {
++ FUNC("pci-dev", 0, 40, 32),
++ FUNC("pci-host2", 1, 40, 32),
++ FUNC("pci-host1", 2, 40, 32),
++ FUNC("pci-fnc", 3, 40, 32)
+ };
++static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
++static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
+
+-static struct ralink_pinmux_grp pci_mux[] = {
+- {
+- .name = "pci-dev",
+- .mask = 0,
+- .gpio_first = RT3883_GPIO_PCI_AD0,
+- .gpio_last = RT3883_GPIO_PCI_AD31,
+- }, {
+- .name = "pci-host2",
+- .mask = 1,
+- .gpio_first = RT3883_GPIO_PCI_AD0,
+- .gpio_last = RT3883_GPIO_PCI_AD31,
+- }, {
+- .name = "pci-host1",
+- .mask = 2,
+- .gpio_first = RT3883_GPIO_PCI_AD0,
+- .gpio_last = RT3883_GPIO_PCI_AD31,
+- }, {
+- .name = "pci-fnc",
+- .mask = 3,
+- .gpio_first = RT3883_GPIO_PCI_AD0,
+- .gpio_last = RT3883_GPIO_PCI_AD31,
+- }, {
+- .name = "pci-gpio",
+- .mask = 7,
+- .gpio_first = RT3883_GPIO_PCI_AD0,
+- .gpio_last = RT3883_GPIO_PCI_AD31,
+- }, {0}
++static struct rt2880_pmx_group rt3883_pinmux_data[] = {
++ GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
++ GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
++ GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
++ RT3883_GPIO_MODE_UART0_SHIFT),
++ GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
++ GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
++ GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
++ GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
++ GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
++ GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
++ RT3883_GPIO_MODE_PCI_SHIFT),
++ GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
++ GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
++ { 0 }
+ };
+
+ static void rt3883_wdt_reset(void)
+@@ -155,17 +73,6 @@ static void rt3883_wdt_reset(void)
+ rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
+ }
+
+-struct ralink_pinmux rt_gpio_pinmux = {
+- .mode = mode_mux,
+- .uart = uart_mux,
+- .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
+- .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
+- .wdt_reset = rt3883_wdt_reset,
+- .pci = pci_mux,
+- .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
+- .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
+-};
+-
+ void __init ralink_clk_init(void)
+ {
+ unsigned long cpu_rate, sys_rate;
+@@ -243,4 +150,6 @@ void prom_soc_init(struct ralink_soc_inf
+ soc_info->mem_base = RT3883_SDRAM_BASE;
+ soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
+ soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
+
-+ /* function 0 is gpio and needs special handling */
-+ if (func == 0) {
-+ int i;
++ rt2880_pinmux_data = rt3883_pinmux_data;
+ }
+--- a/drivers/pinctrl/Kconfig
++++ b/drivers/pinctrl/Kconfig
+@@ -114,6 +114,11 @@ config PINCTRL_LANTIQ
+ select PINMUX
+ select PINCONF
+
++config PINCTRL_RT2880
++ bool
++ depends on RALINK
++ select PINMUX
+
+ config PINCTRL_FALCON
+ bool
+ depends on SOC_FALCON
+--- a/drivers/pinctrl/Makefile
++++ b/drivers/pinctrl/Makefile
+@@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinc
+ obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
+ obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
+ obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
++obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
+
+ obj-$(CONFIG_PLAT_ORION) += mvebu/
+ obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
+--- /dev/null
++++ b/drivers/pinctrl/pinctrl-rt2880.c
+@@ -0,0 +1,467 @@
++/*
++ * linux/drivers/pinctrl/pinctrl-rt2880.c
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * publishhed by the Free Software Foundation.
++ *
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
+
-+ mode |= p->groups[group].gpio << p->groups[group].shift;
-+ /* mark the pins as gpio */
-+ for (i = 0; i < p->groups[group].func[0].pin_count; i++)
-+ p->gpio[p->groups[group].func[0].pins[i]] = 1;
-+ } else {
-+ mode |= p->func[func]->value << p->groups[group].shift;
-+ }
-+ rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/io.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/pinmux.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/pinctrl/machine.h>
+
++#include <asm/mach-ralink/ralink_regs.h>
++#include <asm/mach-ralink/pinmux.h>
++#include <asm/mach-ralink/mt7620.h>
+
-+ return 0;
-+}
++#include "core.h"
+
-+static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
-+ struct pinctrl_gpio_range *range,
-+ unsigned pin)
-+{
-+ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
++#define SYSC_REG_GPIO_MODE 0x60
+
-+ if (!p->gpio[pin]) {
-+ dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
-+ return -EINVAL;
-+ }
++struct rt2880_priv {
++ struct device *dev;
+
-+ return 0;
-+}
++ struct pinctrl_pin_desc *pads;
++ struct pinctrl_desc *desc;
+
-+static const struct pinmux_ops rt2880_pmx_group_ops = {
-+ .get_functions_count = rt2880_pmx_func_count,
-+ .get_function_name = rt2880_pmx_func_name,
-+ .get_function_groups = rt2880_pmx_group_get_groups,
-+ .enable = rt2880_pmx_group_enable,
-+ .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
-+};
++ struct rt2880_pmx_func **func;
++ int func_count;
+
-+static struct pinctrl_desc rt2880_pctrl_desc = {
-+ .owner = THIS_MODULE,
-+ .name = "rt2880-pinmux",
-+ .pctlops = &rt2880_pctrl_ops,
-+ .pmxops = &rt2880_pmx_group_ops,
-+};
++ struct rt2880_pmx_group *groups;
++ const char **group_names;
++ int group_count;
+
-+static struct rt2880_pmx_func gpio_func = {
-+ .name = "gpio",
++ uint8_t *gpio;
++ int max_pins;
+};
+
-+static int rt2880_pinmux_index(struct rt2880_priv *p)
++struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
++
++static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
+{
-+ struct rt2880_pmx_func **f;
-+ struct rt2880_pmx_group *mux = p->groups;
-+ int i, j, c = 0;
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
+
-+ /* count the mux functions */
-+ while (mux->name) {
-+ p->group_count++;
-+ mux++;
-+ }
++ return p->group_count;
++}
+
-+ /* allocate the group names array needed by the gpio function */
-+ p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
-+ if (!p->group_names)
-+ return -1;
++static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
++ unsigned group)
++{
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
+
-+ for (i = 0; i < p->group_count; i++) {
-+ p->group_names[i] = p->groups[i].name;
-+ p->func_count += p->groups[i].func_count;
-+ }
++ if (group >= p->group_count)
++ return NULL;
+
-+ /* we have a dummy function[0] for gpio */
-+ p->func_count++;
++ return p->group_names[group];
++}
+
-+ /* allocate our function and group mapping index buffers */
-+ f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
-+ gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
-+ if (!f || !gpio_func.groups)
-+ return -1;
++static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
++ unsigned group,
++ const unsigned **pins,
++ unsigned *num_pins)
++{
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
+
-+ /* add a backpointer to the function so it knows its group */
-+ gpio_func.group_count = p->group_count;
-+ for (i = 0; i < gpio_func.group_count; i++)
-+ gpio_func.groups[i] = i;
++ if (group >= p->group_count)
++ return -EINVAL;
+
-+ f[c] = &gpio_func;
-+ c++;
++ *pins = p->groups[group].func[0].pins;
++ *num_pins = p->groups[group].func[0].pin_count;
+
-+ /* add remaining functions */
-+ for (i = 0; i < p->group_count; i++) {
-+ for (j = 0; j < p->groups[i].func_count; j++) {
-+ f[c] = &p->groups[i].func[j];
-+ f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
-+ f[c]->groups[0] = i;
-+ f[c]->group_count = 1;
-+ c++;
-+ }
-+ }
+ return 0;
+}
+
-+static int rt2880_pinmux_pins(struct rt2880_priv *p)
++static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
++ struct pinctrl_map *map, unsigned num_maps)
+{
-+ int i, j;
-+
-+ /* loop over the functions and initialize the pins array. also work out the highest pin used */
-+ for (i = 0; i < p->func_count; i++) {
-+ int pin;
-+
-+ if (!p->func[i]->pin_count)
-+ continue;
-+
-+ p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
-+ for (j = 0; j < p->func[i]->pin_count; j++)
-+ p->func[i]->pins[j] = p->func[i]->pin_first + j;
++ int i;
+
-+ pin = p->func[i]->pin_first + p->func[i]->pin_count;
-+ if (pin > p->max_pins)
-+ p->max_pins = pin;
-+ }
++ for (i = 0; i < num_maps; i++)
++ if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
++ map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
++ kfree(map[i].data.configs.configs);
++ kfree(map);
++}
+
-+ /* the buffer that tells us which pins are gpio */
-+ p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
-+ GFP_KERNEL);
-+ /* the pads needed to tell pinctrl about our pins */
-+ p->pads = devm_kzalloc(p->dev,
-+ sizeof(struct pinctrl_pin_desc) * p->max_pins,
-+ GFP_KERNEL);
-+ if (!p->pads || !p->gpio ) {
-+ dev_err(p->dev, "Failed to allocate gpio data\n");
-+ return -ENOMEM;
-+ }
++static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
++ struct seq_file *s,
++ unsigned offset)
++{
++ seq_printf(s, "ralink pio");
++}
+
-+ memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins);
-+ for (i = 0; i < p->func_count; i++) {
-+ if (!p->func[i]->pin_count)
-+ continue;
++static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
++ struct device_node *np,
++ struct pinctrl_map **map)
++{
++ const char *function;
++ int func = of_property_read_string(np, "ralink,function", &function);
++ int grps = of_property_count_strings(np, "ralink,group");
++ int i;
+
-+ for (j = 0; j < p->func[i]->pin_count; j++)
-+ p->gpio[p->func[i]->pins[j]] = 0;
-+ }
++ if (func || !grps)
++ return;
+
-+ /* pin 0 is always a gpio */
-+ p->gpio[0] = 1;
++ for (i = 0; i < grps; i++) {
++ const char *group;
+
-+ /* set the pads */
-+ for (i = 0; i < p->max_pins; i++) {
-+ /* strlen("ioXY") + 1 = 5 */
-+ char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
++ of_property_read_string_index(np, "ralink,group", i, &group);
+
-+ if (!name) {
-+ dev_err(p->dev, "Failed to allocate pad name\n");
-+ return -ENOMEM;
-+ }
-+ snprintf(name, 5, "io%d", i);
-+ p->pads[i].number = i;
-+ p->pads[i].name = name;
++ (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
++ (*map)->name = function;
++ (*map)->data.mux.group = group;
++ (*map)->data.mux.function = function;
++ (*map)++;
+ }
-+ p->desc->pins = p->pads;
-+ p->desc->npins = p->max_pins;
-+
-+ return 0;
+}
+
-+static int rt2880_pinmux_probe(struct platform_device *pdev)
++static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
++ struct device_node *np_config,
++ struct pinctrl_map **map,
++ unsigned *num_maps)
+{
-+ struct rt2880_priv *p;
-+ struct pinctrl_dev *dev;
++ int max_maps = 0;
++ struct pinctrl_map *tmp;
+ struct device_node *np;
+
-+ if (!rt2880_pinmux_data)
-+ return -ENOSYS;
-+
-+ /* setup the private data */
-+ p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
-+ if (!p)
-+ return -ENOMEM;
-+
-+ p->dev = &pdev->dev;
-+ p->desc = &rt2880_pctrl_desc;
-+ p->groups = rt2880_pinmux_data;
-+ platform_set_drvdata(pdev, p);
++ for_each_child_of_node(np_config, np) {
++ int ret = of_property_count_strings(np, "ralink,group");
+
-+ /* init the device */
-+ if (rt2880_pinmux_index(p)) {
-+ dev_err(&pdev->dev, "failed to load index\n");
-+ return -EINVAL;
-+ }
-+ if (rt2880_pinmux_pins(p)) {
-+ dev_err(&pdev->dev, "failed to load pins\n");
-+ return -EINVAL;
++ if (ret >= 0)
++ max_maps += ret;
+ }
-+ dev = pinctrl_register(p->desc, &pdev->dev, p);
-+ if (IS_ERR(dev))
-+ return PTR_ERR(dev);
+
-+ /* finalize by adding gpio ranges for enables gpio controllers */
-+ for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
-+ const __be32 *ngpio, *gpiobase;
-+ struct pinctrl_gpio_range *range;
-+ char *name;
++ if (!max_maps)
++ return max_maps;
+
-+ if (!of_device_is_available(np))
-+ continue;
++ *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
++ if (!*map)
++ return -ENOMEM;
+
-+ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
-+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
-+ if (!ngpio || !gpiobase) {
-+ dev_err(&pdev->dev, "failed to load chip info\n");
-+ return -EINVAL;
-+ }
++ tmp = *map;
+
-+ range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
-+ range->name = name = (char *) &range[1];
-+ sprintf(name, "pio");
-+ range->npins = __be32_to_cpu(*ngpio);
-+ range->base = __be32_to_cpu(*gpiobase);
-+ range->pin_base = range->base;
-+ pinctrl_add_gpio_range(dev, range);
-+ }
++ for_each_child_of_node(np_config, np)
++ rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
++ *num_maps = max_maps;
+
+ return 0;
+}
+
-+static const struct of_device_id rt2880_pinmux_match[] = {
-+ { .compatible = "ralink,rt2880-pinmux" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
-+
-+static struct platform_driver rt2880_pinmux_driver = {
-+ .probe = rt2880_pinmux_probe,
-+ .driver = {
-+ .name = "rt2880-pinmux",
-+ .owner = THIS_MODULE,
-+ .of_match_table = rt2880_pinmux_match,
-+ },
++static const struct pinctrl_ops rt2880_pctrl_ops = {
++ .get_groups_count = rt2880_get_group_count,
++ .get_group_name = rt2880_get_group_name,
++ .get_group_pins = rt2880_get_group_pins,
++ .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
++ .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
++ .dt_free_map = rt2880_pinctrl_dt_free_map,
+};
+
-+int __init rt2880_pinmux_init(void)
++static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
+{
-+ return platform_driver_register(&rt2880_pinmux_driver);
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
++
++ return p->func_count;
+}
+
-+core_initcall_sync(rt2880_pinmux_init);
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/pinmux.h
-@@ -0,0 +1,53 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * publishhed by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
-+ */
++static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
++ unsigned func)
++{
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
+
-+#ifndef _RT288X_PINMUX_H__
-+#define _RT288X_PINMUX_H__
++ return p->func[func]->name;
++}
+
-+#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
-+#define GRP(_name, _func, _mask, _shift) \
-+ { .name = _name, .mask = _mask, .shift = _shift, \
-+ .func = _func, .gpio = _mask, \
-+ .func_count = ARRAY_SIZE(_func) }
++static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
++ unsigned func,
++ const char * const **groups,
++ unsigned * const num_groups)
++{
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
+
-+#define GRP_G(_name, _func, _mask, _gpio, _shift) \
-+ { .name = _name, .mask = _mask, .shift = _shift, \
-+ .func = _func, .gpio = _gpio, \
-+ .func_count = ARRAY_SIZE(_func) }
++ if (p->func[func]->group_count == 1)
++ *groups = &p->group_names[p->func[func]->groups[0]];
++ else
++ *groups = p->group_names;
+
-+struct rt2880_pmx_group;
++ *num_groups = p->func[func]->group_count;
+
-+struct rt2880_pmx_func {
-+ const char *name;
-+ const char value;
++ return 0;
++}
+
-+ int pin_first;
-+ int pin_count;
-+ int *pins;
++static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
++ unsigned func,
++ unsigned group)
++{
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
++ u32 mode = 0;
++ int i;
+
-+ int *groups;
-+ int group_count;
++ /* dont allow double use */
++ if (p->groups[group].enabled) {
++ dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
++ return -EBUSY;
++ }
+
-+ int enabled;
-+};
++ p->groups[group].enabled = 1;
++ p->func[func]->enabled = 1;
+
-+struct rt2880_pmx_group {
-+ const char *name;
-+ int enabled;
++ mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
++ mode &= ~(p->groups[group].mask << p->groups[group].shift);
+
-+ const u32 shift;
-+ const char mask;
-+ const char gpio;
++ /* mark the pins as gpio */
++ for (i = 0; i < p->groups[group].func[0].pin_count; i++)
++ p->gpio[p->groups[group].func[0].pins[i]] = 1;
+
-+ struct rt2880_pmx_func *func;
-+ int func_count;
-+};
++ /* function 0 is gpio and needs special handling */
++ if (func == 0) {
++ mode |= p->groups[group].gpio << p->groups[group].shift;
++ } else {
++ for (i = 0; i < p->func[func]->pin_count; i++)
++ p->gpio[p->func[func]->pins[i]] = 0;
++ mode |= p->func[func]->value << p->groups[group].shift;
++ }
++ rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
+
-+extern struct rt2880_pmx_group *rt2880_pinmux_data;
+
-+#endif
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -17,6 +17,7 @@
- #include <asm/mipsregs.h>
- #include <asm/mach-ralink/ralink_regs.h>
- #include <asm/mach-ralink/mt7620.h>
-+#include <asm/mach-ralink/pinmux.h>
-
- #include "common.h"
-
-@@ -48,118 +49,58 @@ static int dram_type;
- /* the pll dividers */
- static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
-
--static struct ralink_pinmux_grp mode_mux[] = {
-- {
-- .name = "i2c",
-- .mask = MT7620_GPIO_MODE_I2C,
-- .gpio_first = 1,
-- .gpio_last = 2,
-- }, {
-- .name = "spi",
-- .mask = MT7620_GPIO_MODE_SPI,
-- .gpio_first = 3,
-- .gpio_last = 6,
-- }, {
-- .name = "uartlite",
-- .mask = MT7620_GPIO_MODE_UART1,
-- .gpio_first = 15,
-- .gpio_last = 16,
-- }, {
-- .name = "wdt",
-- .mask = MT7620_GPIO_MODE_WDT,
-- .gpio_first = 17,
-- .gpio_last = 17,
-- }, {
-- .name = "mdio",
-- .mask = MT7620_GPIO_MODE_MDIO,
-- .gpio_first = 22,
-- .gpio_last = 23,
-- }, {
-- .name = "rgmii1",
-- .mask = MT7620_GPIO_MODE_RGMII1,
-- .gpio_first = 24,
-- .gpio_last = 35,
-- }, {
-- .name = "spi refclk",
-- .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
-- .gpio_first = 37,
-- .gpio_last = 39,
-- }, {
-- .name = "jtag",
-- .mask = MT7620_GPIO_MODE_JTAG,
-- .gpio_first = 40,
-- .gpio_last = 44,
-- }, {
-- /* shared lines with jtag */
-- .name = "ephy",
-- .mask = MT7620_GPIO_MODE_EPHY,
-- .gpio_first = 40,
-- .gpio_last = 44,
-- }, {
-- .name = "nand",
-- .mask = MT7620_GPIO_MODE_JTAG,
-- .gpio_first = 45,
-- .gpio_last = 59,
-- }, {
-- .name = "rgmii2",
-- .mask = MT7620_GPIO_MODE_RGMII2,
-- .gpio_first = 60,
-- .gpio_last = 71,
-- }, {
-- .name = "wled",
-- .mask = MT7620_GPIO_MODE_WLED,
-- .gpio_first = 72,
-- .gpio_last = 72,
-- }, {0}
-+static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
-+static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
-+static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
-+static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
-+static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
-+static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
-+static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
-+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
-+static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
-+static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
-+static struct rt2880_pmx_func uartf_grp[] = {
-+ FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
-+ FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
-+ FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
-+ FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
-+ FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
-+ FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
-+ FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
- };
--
--static struct ralink_pinmux_grp uart_mux[] = {
-- {
-- .name = "uartf",
-- .mask = MT7620_GPIO_MODE_UARTF,
-- .gpio_first = 7,
-- .gpio_last = 14,
-- }, {
-- .name = "pcm uartf",
-- .mask = MT7620_GPIO_MODE_PCM_UARTF,
-- .gpio_first = 7,
-- .gpio_last = 14,
-- }, {
-- .name = "pcm i2s",
-- .mask = MT7620_GPIO_MODE_PCM_I2S,
-- .gpio_first = 7,
-- .gpio_last = 14,
-- }, {
-- .name = "i2s uartf",
-- .mask = MT7620_GPIO_MODE_I2S_UARTF,
-- .gpio_first = 7,
-- .gpio_last = 14,
-- }, {
-- .name = "pcm gpio",
-- .mask = MT7620_GPIO_MODE_PCM_GPIO,
-- .gpio_first = 11,
-- .gpio_last = 14,
-- }, {
-- .name = "gpio uartf",
-- .mask = MT7620_GPIO_MODE_GPIO_UARTF,
-- .gpio_first = 7,
-- .gpio_last = 10,
-- }, {
-- .name = "gpio i2s",
-- .mask = MT7620_GPIO_MODE_GPIO_I2S,
-- .gpio_first = 7,
-- .gpio_last = 10,
-- }, {
-- .name = "gpio",
-- .mask = MT7620_GPIO_MODE_GPIO,
-- }, {0}
-+static struct rt2880_pmx_func wdt_grp[] = {
-+ FUNC("wdt rst", 0, 17, 1),
-+ FUNC("wdt refclk", 0, 17, 1),
-+ };
-+static struct rt2880_pmx_func pcie_rst_grp[] = {
-+ FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
-+ FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
++ return 0;
++}
++
++static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
++ struct pinctrl_gpio_range *range,
++ unsigned pin)
++{
++ struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
++
++ if (!p->gpio[pin]) {
++ dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static const struct pinmux_ops rt2880_pmx_group_ops = {
++ .get_functions_count = rt2880_pmx_func_count,
++ .get_function_name = rt2880_pmx_func_name,
++ .get_function_groups = rt2880_pmx_group_get_groups,
++ .enable = rt2880_pmx_group_enable,
++ .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
+};
-+static struct rt2880_pmx_func nd_sd_grp[] = {
-+ FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
-+ FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
- };
-
--struct ralink_pinmux rt_gpio_pinmux = {
-- .mode = mode_mux,
-- .uart = uart_mux,
-- .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
-- .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
-+static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
-+ GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
-+ GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
-+ MT7620_GPIO_MODE_UART0_SHIFT),
-+ GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
-+ GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
-+ GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
-+ MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
-+ GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
-+ GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
-+ GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
-+ GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
-+ MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
-+ GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
-+ MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
-+ GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
-+ GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
-+ GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
-+ GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
-+ { 0 }
- };
-
- void __init ralink_clk_init(void)
-@@ -281,4 +222,6 @@ void prom_soc_init(struct ralink_soc_inf
- (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
- pr_info("Digital PMU set to %s control\n",
- (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
+
-+ rt2880_pinmux_data = mt7620a_pinmux_data;
- }
---- a/arch/mips/ralink/rt305x.c
-+++ b/arch/mips/ralink/rt305x.c
-@@ -17,90 +17,71 @@
- #include <asm/mipsregs.h>
- #include <asm/mach-ralink/ralink_regs.h>
- #include <asm/mach-ralink/rt305x.h>
-+#include <asm/mach-ralink/pinmux.h>
-
- #include "common.h"
-
- enum rt305x_soc_type rt305x_soc;
-
--static struct ralink_pinmux_grp mode_mux[] = {
-- {
-- .name = "i2c",
-- .mask = RT305X_GPIO_MODE_I2C,
-- .gpio_first = RT305X_GPIO_I2C_SD,
-- .gpio_last = RT305X_GPIO_I2C_SCLK,
-- }, {
-- .name = "spi",
-- .mask = RT305X_GPIO_MODE_SPI,
-- .gpio_first = RT305X_GPIO_SPI_EN,
-- .gpio_last = RT305X_GPIO_SPI_CLK,
-- }, {
-- .name = "uartlite",
-- .mask = RT305X_GPIO_MODE_UART1,
-- .gpio_first = RT305X_GPIO_UART1_TXD,
-- .gpio_last = RT305X_GPIO_UART1_RXD,
-- }, {
-- .name = "jtag",
-- .mask = RT305X_GPIO_MODE_JTAG,
-- .gpio_first = RT305X_GPIO_JTAG_TDO,
-- .gpio_last = RT305X_GPIO_JTAG_TDI,
-- }, {
-- .name = "mdio",
-- .mask = RT305X_GPIO_MODE_MDIO,
-- .gpio_first = RT305X_GPIO_MDIO_MDC,
-- .gpio_last = RT305X_GPIO_MDIO_MDIO,
-- }, {
-- .name = "sdram",
-- .mask = RT305X_GPIO_MODE_SDRAM,
-- .gpio_first = RT305X_GPIO_SDRAM_MD16,
-- .gpio_last = RT305X_GPIO_SDRAM_MD31,
-- }, {
-- .name = "rgmii",
-- .mask = RT305X_GPIO_MODE_RGMII,
-- .gpio_first = RT305X_GPIO_GE0_TXD0,
-- .gpio_last = RT305X_GPIO_GE0_RXCLK,
-- }, {0}
-+static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
-+static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
-+static struct rt2880_pmx_func uartf_func[] = {
-+ FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
-+ FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
-+ FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
-+ FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
-+ FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
-+ FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
-+ FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
++static struct pinctrl_desc rt2880_pctrl_desc = {
++ .owner = THIS_MODULE,
++ .name = "rt2880-pinmux",
++ .pctlops = &rt2880_pctrl_ops,
++ .pmxops = &rt2880_pmx_group_ops,
+};
-+static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
-+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
-+static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
-+static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
-+static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
-+static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) };
-+static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
-+static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
-+static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
-+static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
+
-+static struct rt2880_pmx_group rt3050_pinmux_data[] = {
-+ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
-+ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
-+ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
-+ RT305X_GPIO_MODE_UART0_SHIFT),
-+ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
-+ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
-+ GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
-+ GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
-+ GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
-+ { 0 }
++static struct rt2880_pmx_func gpio_func = {
++ .name = "gpio",
+};
+
-+static struct rt2880_pmx_group rt3352_pinmux_data[] = {
-+ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
-+ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
-+ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
-+ RT305X_GPIO_MODE_UART0_SHIFT),
-+ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
-+ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
-+ GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
-+ GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
-+ GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
-+ GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
-+ GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
-+ { 0 }
- };
-
--static struct ralink_pinmux_grp uart_mux[] = {
-- {
-- .name = "uartf",
-- .mask = RT305X_GPIO_MODE_UARTF,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "pcm uartf",
-- .mask = RT305X_GPIO_MODE_PCM_UARTF,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "pcm i2s",
-- .mask = RT305X_GPIO_MODE_PCM_I2S,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "i2s uartf",
-- .mask = RT305X_GPIO_MODE_I2S_UARTF,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "pcm gpio",
-- .mask = RT305X_GPIO_MODE_PCM_GPIO,
-- .gpio_first = RT305X_GPIO_10,
-- .gpio_last = RT305X_GPIO_14,
-- }, {
-- .name = "gpio uartf",
-- .mask = RT305X_GPIO_MODE_GPIO_UARTF,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_10,
-- }, {
-- .name = "gpio i2s",
-- .mask = RT305X_GPIO_MODE_GPIO_I2S,
-- .gpio_first = RT305X_GPIO_7,
-- .gpio_last = RT305X_GPIO_10,
-- }, {
-- .name = "gpio",
-- .mask = RT305X_GPIO_MODE_GPIO,
-- }, {0}
-+static struct rt2880_pmx_group rt5350_pinmux_data[] = {
-+ GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
-+ GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
-+ GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
-+ RT305X_GPIO_MODE_UART0_SHIFT),
-+ GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
-+ GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
-+ GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
-+ { 0 }
- };
-
- static void rt305x_wdt_reset(void)
-@@ -114,14 +95,6 @@ static void rt305x_wdt_reset(void)
- rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
- }
-
--struct ralink_pinmux rt_gpio_pinmux = {
-- .mode = mode_mux,
-- .uart = uart_mux,
-- .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
-- .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
-- .wdt_reset = rt305x_wdt_reset,
--};
--
- static unsigned long rt5350_get_mem_size(void)
- {
- void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
-@@ -291,11 +264,14 @@ void prom_soc_init(struct ralink_soc_inf
- soc_info->mem_base = RT305X_SDRAM_BASE;
- if (soc_is_rt5350()) {
- soc_info->mem_size = rt5350_get_mem_size();
-+ rt2880_pinmux_data = rt5350_pinmux_data;
- } else if (soc_is_rt305x() || soc_is_rt3350()) {
- soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
- soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
-+ rt2880_pinmux_data = rt3050_pinmux_data;
- } else if (soc_is_rt3352()) {
- soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
- soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
-+ rt2880_pinmux_data = rt3352_pinmux_data;
- }
- }
---- a/arch/mips/include/asm/mach-ralink/rt305x.h
-+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
-@@ -125,24 +125,28 @@ static inline int soc_is_rt5350(void)
- #define RT305X_GPIO_GE0_TXD0 40
- #define RT305X_GPIO_GE0_RXCLK 51
-
--#define RT305X_GPIO_MODE_I2C BIT(0)
--#define RT305X_GPIO_MODE_SPI BIT(1)
- #define RT305X_GPIO_MODE_UART0_SHIFT 2
- #define RT305X_GPIO_MODE_UART0_MASK 0x7
- #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
--#define RT305X_GPIO_MODE_UARTF 0x0
--#define RT305X_GPIO_MODE_PCM_UARTF 0x1
--#define RT305X_GPIO_MODE_PCM_I2S 0x2
--#define RT305X_GPIO_MODE_I2S_UARTF 0x3
--#define RT305X_GPIO_MODE_PCM_GPIO 0x4
--#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
--#define RT305X_GPIO_MODE_GPIO_I2S 0x6
--#define RT305X_GPIO_MODE_GPIO 0x7
--#define RT305X_GPIO_MODE_UART1 BIT(5)
--#define RT305X_GPIO_MODE_JTAG BIT(6)
--#define RT305X_GPIO_MODE_MDIO BIT(7)
--#define RT305X_GPIO_MODE_SDRAM BIT(8)
--#define RT305X_GPIO_MODE_RGMII BIT(9)
-+#define RT305X_GPIO_MODE_UARTF 0
-+#define RT305X_GPIO_MODE_PCM_UARTF 1
-+#define RT305X_GPIO_MODE_PCM_I2S 2
-+#define RT305X_GPIO_MODE_I2S_UARTF 3
-+#define RT305X_GPIO_MODE_PCM_GPIO 4
-+#define RT305X_GPIO_MODE_GPIO_UARTF 5
-+#define RT305X_GPIO_MODE_GPIO_I2S 6
-+#define RT305X_GPIO_MODE_GPIO 7
++static int rt2880_pinmux_index(struct rt2880_priv *p)
++{
++ struct rt2880_pmx_func **f;
++ struct rt2880_pmx_group *mux = p->groups;
++ int i, j, c = 0;
++
++ /* count the mux functions */
++ while (mux->name) {
++ p->group_count++;
++ mux++;
++ }
++
++ /* allocate the group names array needed by the gpio function */
++ p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
++ if (!p->group_names)
++ return -1;
++
++ for (i = 0; i < p->group_count; i++) {
++ p->group_names[i] = p->groups[i].name;
++ p->func_count += p->groups[i].func_count;
++ }
++
++ /* we have a dummy function[0] for gpio */
++ p->func_count++;
++
++ /* allocate our function and group mapping index buffers */
++ f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
++ gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
++ if (!f || !gpio_func.groups)
++ return -1;
++
++ /* add a backpointer to the function so it knows its group */
++ gpio_func.group_count = p->group_count;
++ for (i = 0; i < gpio_func.group_count; i++)
++ gpio_func.groups[i] = i;
++
++ f[c] = &gpio_func;
++ c++;
++
++ /* add remaining functions */
++ for (i = 0; i < p->group_count; i++) {
++ for (j = 0; j < p->groups[i].func_count; j++) {
++ f[c] = &p->groups[i].func[j];
++ f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
++ f[c]->groups[0] = i;
++ f[c]->group_count = 1;
++ c++;
++ }
++ }
++ return 0;
++}
++
++static int rt2880_pinmux_pins(struct rt2880_priv *p)
++{
++ int i, j;
++
++ /* loop over the functions and initialize the pins array. also work out the highest pin used */
++ for (i = 0; i < p->func_count; i++) {
++ int pin;
++
++ if (!p->func[i]->pin_count)
++ continue;
++
++ p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
++ for (j = 0; j < p->func[i]->pin_count; j++)
++ p->func[i]->pins[j] = p->func[i]->pin_first + j;
++
++ pin = p->func[i]->pin_first + p->func[i]->pin_count;
++ if (pin > p->max_pins)
++ p->max_pins = pin;
++ }
++
++ /* the buffer that tells us which pins are gpio */
++ p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
++ GFP_KERNEL);
++ /* the pads needed to tell pinctrl about our pins */
++ p->pads = devm_kzalloc(p->dev,
++ sizeof(struct pinctrl_pin_desc) * p->max_pins,
++ GFP_KERNEL);
++ if (!p->pads || !p->gpio ) {
++ dev_err(p->dev, "Failed to allocate gpio data\n");
++ return -ENOMEM;
++ }
++
++ memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins);
++ for (i = 0; i < p->func_count; i++) {
++ if (!p->func[i]->pin_count)
++ continue;
++
++ for (j = 0; j < p->func[i]->pin_count; j++)
++ p->gpio[p->func[i]->pins[j]] = 0;
++ }
++
++ /* pin 0 is always a gpio */
++ p->gpio[0] = 1;
++
++ /* set the pads */
++ for (i = 0; i < p->max_pins; i++) {
++ /* strlen("ioXY") + 1 = 5 */
++ char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
++
++ if (!name) {
++ dev_err(p->dev, "Failed to allocate pad name\n");
++ return -ENOMEM;
++ }
++ snprintf(name, 5, "io%d", i);
++ p->pads[i].number = i;
++ p->pads[i].name = name;
++ }
++ p->desc->pins = p->pads;
++ p->desc->npins = p->max_pins;
++
++ return 0;
++}
++
++static int rt2880_pinmux_probe(struct platform_device *pdev)
++{
++ struct rt2880_priv *p;
++ struct pinctrl_dev *dev;
++ struct device_node *np;
++
++ if (!rt2880_pinmux_data)
++ return -ENOSYS;
+
-+#define RT305X_GPIO_MODE_I2C 0
-+#define RT305X_GPIO_MODE_SPI 1
-+#define RT305X_GPIO_MODE_UART1 5
-+#define RT305X_GPIO_MODE_JTAG 6
-+#define RT305X_GPIO_MODE_MDIO 7
-+#define RT305X_GPIO_MODE_SDRAM 8
-+#define RT305X_GPIO_MODE_RGMII 9
-+#define RT5350_GPIO_MODE_PHY_LED 14
-+#define RT3352_GPIO_MODE_LNA 18
-+#define RT3352_GPIO_MODE_PA 20
-
- #define RT3352_SYSC_REG_SYSCFG0 0x010
- #define RT3352_SYSC_REG_SYSCFG1 0x014
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -59,7 +59,6 @@
- #define MT7620_DDR2_SIZE_MIN 32
- #define MT7620_DDR2_SIZE_MAX 256
-
--#define MT7620_GPIO_MODE_I2C BIT(0)
- #define MT7620_GPIO_MODE_UART0_SHIFT 2
- #define MT7620_GPIO_MODE_UART0_MASK 0x7
- #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
-@@ -71,15 +70,35 @@
- #define MT7620_GPIO_MODE_GPIO_UARTF 0x5
- #define MT7620_GPIO_MODE_GPIO_I2S 0x6
- #define MT7620_GPIO_MODE_GPIO 0x7
--#define MT7620_GPIO_MODE_UART1 BIT(5)
--#define MT7620_GPIO_MODE_MDIO BIT(8)
--#define MT7620_GPIO_MODE_RGMII1 BIT(9)
--#define MT7620_GPIO_MODE_RGMII2 BIT(10)
--#define MT7620_GPIO_MODE_SPI BIT(11)
--#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
--#define MT7620_GPIO_MODE_WLED BIT(13)
--#define MT7620_GPIO_MODE_JTAG BIT(15)
--#define MT7620_GPIO_MODE_EPHY BIT(15)
--#define MT7620_GPIO_MODE_WDT BIT(22)
++ /* setup the private data */
++ p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
++ if (!p)
++ return -ENOMEM;
+
-+#define MT7620_GPIO_MODE_NAND 0
-+#define MT7620_GPIO_MODE_SD 1
-+#define MT7620_GPIO_MODE_ND_SD_GPIO 2
-+#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
-+#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
++ p->dev = &pdev->dev;
++ p->desc = &rt2880_pctrl_desc;
++ p->groups = rt2880_pinmux_data;
++ platform_set_drvdata(pdev, p);
+
-+#define MT7620_GPIO_MODE_PCIE_RST 0
-+#define MT7620_GPIO_MODE_PCIE_REF 1
-+#define MT7620_GPIO_MODE_PCIE_GPIO 2
-+#define MT7620_GPIO_MODE_PCIE_MASK 0x3
-+#define MT7620_GPIO_MODE_PCIE_SHIFT 16
++ /* init the device */
++ if (rt2880_pinmux_index(p)) {
++ dev_err(&pdev->dev, "failed to load index\n");
++ return -EINVAL;
++ }
++ if (rt2880_pinmux_pins(p)) {
++ dev_err(&pdev->dev, "failed to load pins\n");
++ return -EINVAL;
++ }
++ dev = pinctrl_register(p->desc, &pdev->dev, p);
++ if (IS_ERR(dev))
++ return PTR_ERR(dev);
+
-+#define MT7620_GPIO_MODE_WDT_RST 0
-+#define MT7620_GPIO_MODE_WDT_REF 1
-+#define MT7620_GPIO_MODE_WDT_GPIO 2
-+#define MT7620_GPIO_MODE_WDT_MASK 0x3
-+#define MT7620_GPIO_MODE_WDT_SHIFT 21
++ /* finalize by adding gpio ranges for enables gpio controllers */
++ for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
++ const __be32 *ngpio, *gpiobase;
++ struct pinctrl_gpio_range *range;
++ char *name;
+
-+#define MT7620_GPIO_MODE_I2C 0
-+#define MT7620_GPIO_MODE_UART1 5
-+#define MT7620_GPIO_MODE_MDIO 8
-+#define MT7620_GPIO_MODE_RGMII1 9
-+#define MT7620_GPIO_MODE_RGMII2 10
-+#define MT7620_GPIO_MODE_SPI 11
-+#define MT7620_GPIO_MODE_SPI_REF_CLK 12
-+#define MT7620_GPIO_MODE_WLED 13
-+#define MT7620_GPIO_MODE_JTAG 15
-+#define MT7620_GPIO_MODE_EPHY 15
-+#define MT7620_GPIO_MODE_PA 20
-
- #endif
---- a/arch/mips/include/asm/mach-ralink/rt3883.h
-+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
-@@ -112,8 +112,6 @@
- #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
- #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
-
--#define RT3883_GPIO_MODE_I2C BIT(0)
--#define RT3883_GPIO_MODE_SPI BIT(1)
- #define RT3883_GPIO_MODE_UART0_SHIFT 2
- #define RT3883_GPIO_MODE_UART0_MASK 0x7
- #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
-@@ -125,11 +123,15 @@
- #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
- #define RT3883_GPIO_MODE_GPIO_I2S 0x6
- #define RT3883_GPIO_MODE_GPIO 0x7
--#define RT3883_GPIO_MODE_UART1 BIT(5)
--#define RT3883_GPIO_MODE_JTAG BIT(6)
--#define RT3883_GPIO_MODE_MDIO BIT(7)
--#define RT3883_GPIO_MODE_GE1 BIT(9)
--#define RT3883_GPIO_MODE_GE2 BIT(10)
++ if (!of_device_is_available(np))
++ continue;
++
++ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
++ gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
++ if (!ngpio || !gpiobase) {
++ dev_err(&pdev->dev, "failed to load chip info\n");
++ return -EINVAL;
++ }
++
++ range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
++ range->name = name = (char *) &range[1];
++ sprintf(name, "pio");
++ range->npins = __be32_to_cpu(*ngpio);
++ range->base = __be32_to_cpu(*gpiobase);
++ range->pin_base = range->base;
++ pinctrl_add_gpio_range(dev, range);
++ }
++
++ return 0;
++}
+
-+#define RT3883_GPIO_MODE_I2C 0
-+#define RT3883_GPIO_MODE_SPI 1
-+#define RT3883_GPIO_MODE_UART1 5
-+#define RT3883_GPIO_MODE_JTAG 6
-+#define RT3883_GPIO_MODE_MDIO 7
-+#define RT3883_GPIO_MODE_GE1 9
-+#define RT3883_GPIO_MODE_GE2 10
++static const struct of_device_id rt2880_pinmux_match[] = {
++ { .compatible = "ralink,rt2880-pinmux" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
+
- #define RT3883_GPIO_MODE_PCI_SHIFT 11
- #define RT3883_GPIO_MODE_PCI_MASK 0x7
- #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
---- a/arch/mips/ralink/common.h
-+++ b/arch/mips/ralink/common.h
-@@ -11,25 +11,6 @@
-
- #define RAMIPS_SYS_TYPE_LEN 32
-
--struct ralink_pinmux_grp {
-- const char *name;
-- u32 mask;
-- int gpio_first;
-- int gpio_last;
--};
--
--struct ralink_pinmux {
-- struct ralink_pinmux_grp *mode;
-- struct ralink_pinmux_grp *uart;
-- int uart_shift;
-- u32 uart_mask;
-- void (*wdt_reset)(void);
-- struct ralink_pinmux_grp *pci;
-- int pci_shift;
-- u32 pci_mask;
--};
--extern struct ralink_pinmux rt_gpio_pinmux;
--
- struct ralink_soc_info {
- unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
- unsigned char *compatible;
---- a/arch/mips/ralink/rt3883.c
-+++ b/arch/mips/ralink/rt3883.c
-@@ -17,132 +17,50 @@
- #include <asm/mipsregs.h>
- #include <asm/mach-ralink/ralink_regs.h>
- #include <asm/mach-ralink/rt3883.h>
-+#include <asm/mach-ralink/pinmux.h>
-
- #include "common.h"
-
--static struct ralink_pinmux_grp mode_mux[] = {
-- {
-- .name = "i2c",
-- .mask = RT3883_GPIO_MODE_I2C,
-- .gpio_first = RT3883_GPIO_I2C_SD,
-- .gpio_last = RT3883_GPIO_I2C_SCLK,
-- }, {
-- .name = "spi",
-- .mask = RT3883_GPIO_MODE_SPI,
-- .gpio_first = RT3883_GPIO_SPI_CS0,
-- .gpio_last = RT3883_GPIO_SPI_MISO,
-- }, {
-- .name = "uartlite",
-- .mask = RT3883_GPIO_MODE_UART1,
-- .gpio_first = RT3883_GPIO_UART1_TXD,
-- .gpio_last = RT3883_GPIO_UART1_RXD,
-- }, {
-- .name = "jtag",
-- .mask = RT3883_GPIO_MODE_JTAG,
-- .gpio_first = RT3883_GPIO_JTAG_TDO,
-- .gpio_last = RT3883_GPIO_JTAG_TCLK,
-- }, {
-- .name = "mdio",
-- .mask = RT3883_GPIO_MODE_MDIO,
-- .gpio_first = RT3883_GPIO_MDIO_MDC,
-- .gpio_last = RT3883_GPIO_MDIO_MDIO,
-- }, {
-- .name = "ge1",
-- .mask = RT3883_GPIO_MODE_GE1,
-- .gpio_first = RT3883_GPIO_GE1_TXD0,
-- .gpio_last = RT3883_GPIO_GE1_RXCLK,
-- }, {
-- .name = "ge2",
-- .mask = RT3883_GPIO_MODE_GE2,
-- .gpio_first = RT3883_GPIO_GE2_TXD0,
-- .gpio_last = RT3883_GPIO_GE2_RXCLK,
-- }, {
-- .name = "pci",
-- .mask = RT3883_GPIO_MODE_PCI,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "lna a",
-- .mask = RT3883_GPIO_MODE_LNA_A,
-- .gpio_first = RT3883_GPIO_LNA_PE_A0,
-- .gpio_last = RT3883_GPIO_LNA_PE_A2,
-- }, {
-- .name = "lna g",
-- .mask = RT3883_GPIO_MODE_LNA_G,
-- .gpio_first = RT3883_GPIO_LNA_PE_G0,
-- .gpio_last = RT3883_GPIO_LNA_PE_G2,
-- }, {0}
-+static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
-+static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
-+static struct rt2880_pmx_func uartf_func[] = {
-+ FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
-+ FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
-+ FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
-+ FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
-+ FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
-+ FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
-+ FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
- };
--
--static struct ralink_pinmux_grp uart_mux[] = {
-- {
-- .name = "uartf",
-- .mask = RT3883_GPIO_MODE_UARTF,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "pcm uartf",
-- .mask = RT3883_GPIO_MODE_PCM_UARTF,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "pcm i2s",
-- .mask = RT3883_GPIO_MODE_PCM_I2S,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "i2s uartf",
-- .mask = RT3883_GPIO_MODE_I2S_UARTF,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "pcm gpio",
-- .mask = RT3883_GPIO_MODE_PCM_GPIO,
-- .gpio_first = RT3883_GPIO_11,
-- .gpio_last = RT3883_GPIO_14,
-- }, {
-- .name = "gpio uartf",
-- .mask = RT3883_GPIO_MODE_GPIO_UARTF,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_10,
-- }, {
-- .name = "gpio i2s",
-- .mask = RT3883_GPIO_MODE_GPIO_I2S,
-- .gpio_first = RT3883_GPIO_7,
-- .gpio_last = RT3883_GPIO_10,
-- }, {
-- .name = "gpio",
-- .mask = RT3883_GPIO_MODE_GPIO,
-- }, {0}
-+static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
-+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
-+static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
-+static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
-+static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
-+static struct rt2880_pmx_func pci_func[] = {
-+ FUNC("pci-dev", 0, 40, 32),
-+ FUNC("pci-host2", 1, 40, 32),
-+ FUNC("pci-host1", 2, 40, 32),
-+ FUNC("pci-fnc", 3, 40, 32)
- };
-+static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
-+static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
-
--static struct ralink_pinmux_grp pci_mux[] = {
-- {
-- .name = "pci-dev",
-- .mask = 0,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "pci-host2",
-- .mask = 1,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "pci-host1",
-- .mask = 2,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "pci-fnc",
-- .mask = 3,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {
-- .name = "pci-gpio",
-- .mask = 7,
-- .gpio_first = RT3883_GPIO_PCI_AD0,
-- .gpio_last = RT3883_GPIO_PCI_AD31,
-- }, {0}
-+static struct rt2880_pmx_group rt3883_pinmux_data[] = {
-+ GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
-+ GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
-+ GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
-+ RT3883_GPIO_MODE_UART0_SHIFT),
-+ GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
-+ GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
-+ GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
-+ GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
-+ GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
-+ GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
-+ RT3883_GPIO_MODE_PCI_SHIFT),
-+ GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
-+ GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
-+ { 0 }
- };
-
- static void rt3883_wdt_reset(void)
-@@ -155,17 +73,6 @@ static void rt3883_wdt_reset(void)
- rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
- }
-
--struct ralink_pinmux rt_gpio_pinmux = {
-- .mode = mode_mux,
-- .uart = uart_mux,
-- .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
-- .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
-- .wdt_reset = rt3883_wdt_reset,
-- .pci = pci_mux,
-- .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
-- .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
--};
--
- void __init ralink_clk_init(void)
- {
- unsigned long cpu_rate, sys_rate;
-@@ -243,4 +150,6 @@ void prom_soc_init(struct ralink_soc_inf
- soc_info->mem_base = RT3883_SDRAM_BASE;
- soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
- soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
++static struct platform_driver rt2880_pinmux_driver = {
++ .probe = rt2880_pinmux_probe,
++ .driver = {
++ .name = "rt2880-pinmux",
++ .owner = THIS_MODULE,
++ .of_match_table = rt2880_pinmux_match,
++ },
++};
+
-+ rt2880_pinmux_data = rt3883_pinmux_data;
- }
++int __init rt2880_pinmux_init(void)
++{
++ return platform_driver_register(&rt2880_pinmux_driver);
++}
++
++core_initcall_sync(rt2880_pinmux_init);
diff --git a/target/linux/ramips/patches-3.10/0107-PCI-MIPS-adds-rt2880-pci-support.patch b/target/linux/ramips/patches-3.10/0114-PCI-MIPS-adds-rt2880-pci-support.patch
similarity index 98%
rename from target/linux/ramips/patches-3.10/0107-PCI-MIPS-adds-rt2880-pci-support.patch
rename to target/linux/ramips/patches-3.10/0114-PCI-MIPS-adds-rt2880-pci-support.patch
index 7136f15852..521651f67a 100644
--- a/target/linux/ramips/patches-3.10/0107-PCI-MIPS-adds-rt2880-pci-support.patch
+++ b/target/linux/ramips/patches-3.10/0114-PCI-MIPS-adds-rt2880-pci-support.patch
@@ -1,7 +1,7 @@
-From 5d57ace094803c95230643941a47d749ff81d022 Mon Sep 17 00:00:00 2001
+From b7040c3ad7b8daf8309d083e9248cfa577075cfb Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 21 Mar 2013 18:27:29 +0100
-Subject: [PATCH 11/33] PCI: MIPS: adds rt2880 pci support
+Subject: [PATCH 114/133] PCI: MIPS: adds rt2880 pci support
Add support for the pci found on the rt2880 SoC.
diff --git a/target/linux/ramips/patches-3.10/0108-PCI-MIPS-adds-mt7620a-pcie-driver.patch b/target/linux/ramips/patches-3.10/0115-PCI-MIPS-adds-mt7620a-pcie-driver.patch
similarity index 98%
rename from target/linux/ramips/patches-3.10/0108-PCI-MIPS-adds-mt7620a-pcie-driver.patch
rename to target/linux/ramips/patches-3.10/0115-PCI-MIPS-adds-mt7620a-pcie-driver.patch
index 2f883b302d..cff4017a45 100644
--- a/target/linux/ramips/patches-3.10/0108-PCI-MIPS-adds-mt7620a-pcie-driver.patch
+++ b/target/linux/ramips/patches-3.10/0115-PCI-MIPS-adds-mt7620a-pcie-driver.patch
@@ -1,7 +1,7 @@
-From ded577553b06a85c12a89b8fbcfa2b51f30bc037 Mon Sep 17 00:00:00 2001
+From 686f5642c74323f7e7eafb93c2b85df589cbf66e Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sat, 18 May 2013 22:06:15 +0200
-Subject: [PATCH 13/33] PCI: MIPS: adds mt7620a pcie driver
+Subject: [PATCH 115/133] PCI: MIPS: adds mt7620a pcie driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---
@@ -11,6 +11,16 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
3 files changed, 365 insertions(+)
create mode 100644 arch/mips/pci/pci-mt7620a.c
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
+ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
+ obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
+ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
++obj-$(CONFIG_SOC_MT7620) += pci-mt7620a.o
+ obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
+ obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
--- /dev/null
+++ b/arch/mips/pci/pci-mt7620a.c
@@ -0,0 +1,363 @@
@@ -387,13 +397,3 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
endchoice
---- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
- obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
- obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
- obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
-+obj-$(CONFIG_SOC_MT7620) += pci-mt7620a.o
- obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
- obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
- obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
diff --git a/target/linux/ramips/patches-3.10/0109-NET-multi-phy-support.patch b/target/linux/ramips/patches-3.10/0116-NET-multi-phy-support.patch
similarity index 93%
rename from target/linux/ramips/patches-3.10/0109-NET-multi-phy-support.patch
rename to target/linux/ramips/patches-3.10/0116-NET-multi-phy-support.patch
index 345ee14434..218d0828dd 100644
--- a/target/linux/ramips/patches-3.10/0109-NET-multi-phy-support.patch
+++ b/target/linux/ramips/patches-3.10/0116-NET-multi-phy-support.patch
@@ -1,7 +1,7 @@
-From 7407b7d178e783074861a73da858b099f870270d Mon Sep 17 00:00:00 2001
+From bed88d4cb806d2738528cb7d368d6df79d9c1424 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sat, 11 May 2013 23:40:19 +0200
-Subject: [PATCH 14/33] NET: multi phy support
+Subject: [PATCH 116/133] NET: multi phy support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
diff --git a/target/linux/ramips/patches-3.10/0110-NET-add-of_get_mac_address_mtd.patch b/target/linux/ramips/patches-3.10/0117-NET-add-of_get_mac_address_mtd.patch
similarity index 94%
rename from target/linux/ramips/patches-3.10/0110-NET-add-of_get_mac_address_mtd.patch
rename to target/linux/ramips/patches-3.10/0117-NET-add-of_get_mac_address_mtd.patch
index 408326d40b..a48bd4b48d 100644
--- a/target/linux/ramips/patches-3.10/0110-NET-add-of_get_mac_address_mtd.patch
+++ b/target/linux/ramips/patches-3.10/0117-NET-add-of_get_mac_address_mtd.patch
@@ -1,7 +1,7 @@
-From 2a41724b2d0af9b4444572c4302570a3af377715 Mon Sep 17 00:00:00 2001
+From 1282a0da09e059288eb8b576998ea001680f6628 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 14 Jul 2013 23:26:15 +0200
-Subject: [PATCH 15/33] NET: add of_get_mac_address_mtd()
+Subject: [PATCH 117/133] NET: add of_get_mac_address_mtd()
Many embedded devices have information such as mac addresses stored inside mtd
devices. This patch allows us to add a property inside a node describing a
diff --git a/target/linux/ramips/patches-3.10/0111-NET-MIPS-add-ralink-SoC-ethernet-driver.patch b/target/linux/ramips/patches-3.10/0118-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
similarity index 99%
rename from target/linux/ramips/patches-3.10/0111-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
rename to target/linux/ramips/patches-3.10/0118-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
index 4d12424e91..103c8180f4 100644
--- a/target/linux/ramips/patches-3.10/0111-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
+++ b/target/linux/ramips/patches-3.10/0118-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
@@ -1,7 +1,7 @@
-From ad11aedcc16574c0b3d3f5e40c67227d1846b94e Mon Sep 17 00:00:00 2001
+From b7d9374aee4b47a76dadaf1fe7f6838087c9c62d Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 22 Apr 2013 23:20:03 +0200
-Subject: [PATCH 16/33] NET: MIPS: add ralink SoC ethernet driver
+Subject: [PATCH 118/133] NET: MIPS: add ralink SoC ethernet driver
Add support for Ralink FE and ESW.
@@ -11,23 +11,25 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
arch/mips/ralink/rt305x.c | 1 +
drivers/net/ethernet/Kconfig | 1 +
drivers/net/ethernet/Makefile | 1 +
- drivers/net/ethernet/ralink/Kconfig | 31 +
+ drivers/net/ethernet/ralink/Kconfig | 32 +
drivers/net/ethernet/ralink/Makefile | 18 +
drivers/net/ethernet/ralink/esw_rt3052.c | 1463 ++++++++++++++++++++
drivers/net/ethernet/ralink/esw_rt3052.h | 32 +
- drivers/net/ethernet/ralink/gsw_mt7620a.c | 1027 ++++++++++++++
- drivers/net/ethernet/ralink/gsw_mt7620a.h | 29 +
- drivers/net/ethernet/ralink/mdio.c | 245 ++++
+ drivers/net/ethernet/ralink/gsw_mt7620a.c | 566 ++++++++
+ drivers/net/ethernet/ralink/gsw_mt7620a.h | 30 +
+ drivers/net/ethernet/ralink/mdio.c | 244 ++++
drivers/net/ethernet/ralink/mdio.h | 29 +
drivers/net/ethernet/ralink/mdio_rt2880.c | 232 ++++
drivers/net/ethernet/ralink/mdio_rt2880.h | 26 +
- drivers/net/ethernet/ralink/ralink_soc_eth.c | 735 ++++++++++
- drivers/net/ethernet/ralink/ralink_soc_eth.h | 374 +++++
- drivers/net/ethernet/ralink/soc_mt7620.c | 111 ++
+ drivers/net/ethernet/ralink/mt7530.c | 467 +++++++
+ drivers/net/ethernet/ralink/mt7530.h | 20 +
+ drivers/net/ethernet/ralink/ralink_soc_eth.c | 845 +++++++++++
+ drivers/net/ethernet/ralink/ralink_soc_eth.h | 384 +++++
+ drivers/net/ethernet/ralink/soc_mt7620.c | 172 +++
drivers/net/ethernet/ralink/soc_rt2880.c | 51 +
drivers/net/ethernet/ralink/soc_rt305x.c | 113 ++
drivers/net/ethernet/ralink/soc_rt3883.c | 60 +
- 20 files changed, 4606 insertions(+)
+ 22 files changed, 4814 insertions(+)
create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
create mode 100644 drivers/net/ethernet/ralink/Kconfig
create mode 100644 drivers/net/ethernet/ralink/Makefile
@@ -39,6 +41,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
create mode 100644 drivers/net/ethernet/ralink/mdio.h
create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
+ create mode 100644 drivers/net/ethernet/ralink/mt7530.c
+ create mode 100644 drivers/net/ethernet/ralink/mt7530.h
create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
@@ -78,7 +82,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#endif /* _RT305X_ESW_PLATFORM_H */
--- a/arch/mips/ralink/rt305x.c
+++ b/arch/mips/ralink/rt305x.c
-@@ -221,6 +221,7 @@ void __init ralink_clk_init(void)
+@@ -194,6 +194,7 @@ void __init ralink_clk_init(void)
}
ralink_clk_add("cpu", cpu_rate);
@@ -2809,1419 +2813,1349 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+
+#endif
--- /dev/null
-+++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c
-@@ -0,0 +1,846 @@
++++ b/drivers/net/ethernet/ralink/mt7530.c
+@@ -0,0 +1,467 @@
+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
+ *
-+ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
++#include <linux/if.h>
+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/types.h>
-+#include <linux/dma-mapping.h>
+#include <linux/init.h>
++#include <linux/list.h>
++#include <linux/if_ether.h>
+#include <linux/skbuff.h>
++#include <linux/netdevice.h>
++#include <linux/netlink.h>
++#include <linux/bitops.h>
++#include <net/genetlink.h>
++#include <linux/switch.h>
++#include <linux/delay.h>
++#include <linux/phy.h>
++#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
-+#include <linux/ethtool.h>
-+#include <linux/platform_device.h>
++#include <linux/lockdep.h>
++#include <linux/workqueue.h>
+#include <linux/of_device.h>
-+#include <linux/clk.h>
-+#include <linux/of_net.h>
-+#include <linux/of_mdio.h>
-+#include <linux/if_vlan.h>
-+#include <linux/reset.h>
+
-+#include <asm/mach-ralink/ralink_regs.h>
++#include "mt7530.h"
+
-+#include "ralink_soc_eth.h"
-+#include "esw_rt3052.h"
-+#include "mdio.h"
++#define MT7530_CPU_PORT 6
++#define MT7530_NUM_PORTS 7
++#define MT7530_NUM_VLANS 16
++#define MT7530_NUM_VIDS 16
+
-+#define TX_TIMEOUT (2 * HZ)
-+#define MAX_RX_LENGTH 1536
-+#define DMA_DUMMY_DESC 0xffffffff
++#define REG_ESW_VLAN_VTCR 0x90
++#define REG_ESW_VLAN_VAWD1 0x94
++#define REG_ESW_VLAN_VAWD2 0x98
+
-+static const u32 fe_reg_table_default[FE_REG_COUNT] = {
-+ [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
-+ [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
-+ [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
-+ [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
-+ [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
-+ [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
-+ [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
-+ [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
-+ [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
-+ [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
-+ [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
++enum {
++ /* Global attributes. */
++ MT7530_ATTR_ENABLE_VLAN,
+};
+
-+static const u32 *fe_reg_table = fe_reg_table_default;
++struct mt7530_port {
++ u16 pvid;
++};
+
-+static void __iomem *fe_base = 0;
++struct mt7530_vlan {
++ u8 ports;
++};
+
-+void fe_w32(u32 val, unsigned reg)
-+{
-+ __raw_writel(val, fe_base + reg);
-+}
++struct mt7530_priv {
++ void __iomem *base;
++ struct mii_bus *bus;
++ struct switch_dev swdev;
+
-+u32 fe_r32(unsigned reg)
-+{
-+ return __raw_readl(fe_base + reg);
-+}
++ bool global_vlan_enable;
++ struct mt7530_vlan vlans[MT7530_NUM_VLANS];
++ struct mt7530_port ports[MT7530_NUM_PORTS];
++};
+
-+static inline void fe_reg_w32(u32 val, enum fe_reg reg)
-+{
-+ fe_w32(val, fe_reg_table[reg]);
-+}
++struct mt7530_mapping {
++ char *name;
++ u8 pvids[6];
++ u8 vlans[8];
++} mt7530_defaults[] = {
++ {
++ .name = "llllw",
++ .pvids = { 1, 1, 1, 1, 2, 1 },
++ .vlans = { 0, 0x6f, 0x50 },
++ }, {
++ .name = "wllll",
++ .pvids = { 2, 1, 1, 1, 1, 1 },
++ .vlans = { 0, 0x7e, 0x41 },
++ },
++};
+
-+static inline u32 fe_reg_r32(enum fe_reg reg)
++struct mt7530_mapping*
++mt7530_find_mapping(struct device_node *np)
+{
-+ return fe_r32(fe_reg_table[reg]);
-+}
++ const char *map;
++ int i;
+
-+static inline void fe_int_disable(u32 mask)
-+{
-+ fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
-+ FE_REG_FE_INT_ENABLE);
-+ /* flush write */
-+ fe_reg_r32(FE_REG_FE_INT_ENABLE);
++ if (of_property_read_string(np, "ralink,port-map", &map))
++ return NULL;
++
++ for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
++ if (!strcmp(map, mt7530_defaults[i].name))
++ return &mt7530_defaults[i];
++
++ return NULL;
+}
+
-+static inline void fe_int_enable(u32 mask)
++static void
++mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
+{
-+ fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
-+ FE_REG_FE_INT_ENABLE);
-+ /* flush write */
-+ fe_reg_r32(FE_REG_FE_INT_ENABLE);
++ int i = 0;
++
++ mt7530->global_vlan_enable = 1;
++
++ for (i = 0; i < 6; i++)
++ mt7530->ports[i].pvid = map->pvids[i];
++ for (i = 0; i < 8; i++)
++ mt7530->vlans[i].ports = map->vlans[i];
+}
+
-+static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
++static int
++mt7530_reset_switch(struct switch_dev *dev)
+{
-+ unsigned long flags;
++ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+
-+ spin_lock_irqsave(&priv->page_lock, flags);
-+ fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
-+ fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
-+ FE_GDMA1_MAC_ADRL);
-+ spin_unlock_irqrestore(&priv->page_lock, flags);
++ memset(priv->ports, 0, sizeof(priv->ports));
++ memset(priv->vlans, 0, sizeof(priv->vlans));
++
++ return 0;
+}
+
-+static int fe_set_mac_address(struct net_device *dev, void *p)
++static int
++mt7530_get_vlan_enable(struct switch_dev *dev,
++ const struct switch_attr *attr,
++ struct switch_val *val)
+{
-+ int ret = eth_mac_addr(dev, p);
-+
-+ if (!ret) {
-+ struct fe_priv *priv = netdev_priv(dev);
++ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+
-+ if (priv->soc->set_mac)
-+ priv->soc->set_mac(priv, dev->dev_addr);
-+ else
-+ fe_hw_set_macaddr(priv, p);
-+ }
++ val->value.i = priv->global_vlan_enable;
+
-+ return ret;
++ return 0;
+}
+
-+static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
++static int
++mt7530_set_vlan_enable(struct switch_dev *dev,
++ const struct switch_attr *attr,
++ struct switch_val *val)
+{
-+ struct sk_buff *skb;
-+
-+ skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
-+ if (!skb)
-+ return NULL;
++ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+
-+ skb_reserve(skb, NET_IP_ALIGN);
++ priv->global_vlan_enable = val->value.i != 0;
+
-+ return skb;
++ return 0;
+}
+
-+static int fe_alloc_rx(struct fe_priv *priv)
++static u32
++mt7530_r32(struct mt7530_priv *priv, u32 reg)
+{
-+ int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
-+ int i;
-+
-+ priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
-+ &priv->rx_phys, GFP_ATOMIC);
-+ if (!priv->rx_dma)
-+ return -ENOMEM;
++ if (priv->bus) {
++ u16 high, low;
+
-+ memset(priv->rx_dma, 0, size);
++ mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
++ low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
++ high = mdiobus_read(priv->bus, 0x1f, 0x10);
+
-+ for (i = 0; i < NUM_DMA_DESC; i++) {
-+ priv->rx_skb[i] = fe_alloc_skb(priv);
-+ if (!priv->rx_skb[i])
-+ return -ENOMEM;
++ return (high << 16) | (low & 0xffff);
+ }
+
-+ for (i = 0; i < NUM_DMA_DESC; i++) {
-+ dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
-+ priv->rx_skb[i]->data,
-+ MAX_RX_LENGTH,
-+ DMA_FROM_DEVICE);
-+ priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
++ return ioread32(priv->base + reg);
++}
+
-+ if (priv->soc->rx_dma)
-+ priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
-+ else
-+ priv->rx_dma[i].rxd2 = RX_DMA_LSO;
++static void
++mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
++{
++ if (priv->bus) {
++ mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
++ mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
++ mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
++ return;
+ }
-+ wmb();
-+
-+ fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
-+ fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
-+ fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
-+ fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
+
-+ return 0;
++ iowrite32(val, priv->base + reg);
+}
+
-+static int fe_alloc_tx(struct fe_priv *priv)
++static void
++mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
+{
-+ int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
+ int i;
+
-+ priv->tx_free_idx = 0;
-+
-+ priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
-+ &priv->tx_phys, GFP_ATOMIC);
-+ if (!priv->tx_dma)
-+ return -ENOMEM;
++ mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
+
-+ memset(priv->tx_dma, 0, size);
++ for (i = 0; i < 20; i++) {
++ u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
+
-+ for (i = 0; i < NUM_DMA_DESC; i++) {
-+ if (priv->soc->tx_dma) {
-+ priv->soc->tx_dma(priv, i, NULL);
-+ continue;
-+ }
++ if ((val & BIT(31)) == 0)
++ break;
+
-+ priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
-+ priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
++ udelay(1000);
+ }
++ if (i == 20)
++ printk("mt7530: vtcr timeout\n");
++}
+
-+ fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
-+ fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
-+ fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
-+ fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
++static int
++mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
++{
++ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
++
++ if (port >= MT7530_NUM_PORTS)
++ return -EINVAL;
++
++ *val = mt7530_r32(priv, 0x2014 + (0x100 * port));
++ *val &= 0xff;
+
+ return 0;
+}
+
-+static void fe_free_dma(struct fe_priv *priv)
++static int
++mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
++{
++ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
++
++ if (port >= MT7530_NUM_PORTS)
++ return -1;
++
++ priv->ports[port].pvid = pvid;
++
++ return 0;
++}
++
++static int
++mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
+{
++ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
++ u32 member;
+ int i;
+
-+ for (i = 0; i < NUM_DMA_DESC; i++) {
-+ if (priv->rx_skb[i]) {
-+ dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
-+ MAX_RX_LENGTH, DMA_FROM_DEVICE);
-+ dev_kfree_skb_any(priv->rx_skb[i]);
-+ priv->rx_skb[i] = NULL;
-+ }
++ val->len = 0;
+
-+ if (priv->tx_skb[i]) {
-+ dev_kfree_skb_any(priv->tx_skb[i]);
-+ priv->tx_skb[i] = NULL;
-+ }
-+ }
++ if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VIDS)
++ return -EINVAL;
+
-+ if (priv->rx_dma) {
-+ int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
-+ dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
-+ priv->rx_phys);
-+ }
++ mt7530_vtcr(priv, 0, val->port_vlan);
++ member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
++ member >>= 16;
++ member &= 0xff;
+
-+ if (priv->tx_dma) {
-+ int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
-+ dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
-+ priv->tx_phys);
++ for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ struct switch_port *p;
++ if (!(member & BIT(i)))
++ continue;
++
++ p = &val->value.ports[val->len++];
++ p->id = i;
++ p->flags = 0;
+ }
+
-+ netdev_reset_queue(priv->netdev);
++ return 0;
+}
+
-+static void fe_start_tso(struct sk_buff *skb, struct net_device *dev, unsigned int nr_frags, int idx)
++static int
++mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
+{
-+ struct fe_priv *priv = netdev_priv(dev);
-+ struct skb_frag_struct *frag;
++ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
++ int ports = 0;
+ int i;
+
-+ for (i = 0; i < nr_frags; i++) {
-+ dma_addr_t mapped_addr;
++ if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VIDS ||
++ val->len > MT7530_NUM_PORTS)
++ return -EINVAL;
+
-+ frag = &skb_shinfo(skb)->frags[i];
-+ mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0, skb_frag_size(frag), DMA_TO_DEVICE);
-+ if (i % 2) {
-+ idx = (idx + 1) % NUM_DMA_DESC;
-+ priv->tx_dma[idx].txd1 = mapped_addr;
-+ if (i == nr_frags - 1)
-+ priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(frag->size);
-+ else
-+ priv->tx_dma[idx].txd2 = TX_DMA_PLEN0(frag->size);
-+ } else {
-+ priv->tx_dma[idx].txd3 = mapped_addr;
-+ if (i == nr_frags - 1)
-+ priv->tx_dma[idx].txd2 |= TX_DMA_LS1 | TX_DMA_PLEN1(frag->size);
-+ else
-+ priv->tx_dma[idx].txd2 |= TX_DMA_PLEN1(frag->size);
-+ }
++ for (i = 0; i < val->len; i++) {
++ struct switch_port *p = &val->value.ports[i];
++
++ if (p->id >= MT7530_NUM_PORTS)
++ return -EINVAL;
++
++ ports |= BIT(p->id);
+ }
++ priv->vlans[val->port_vlan].ports = ports;
++
++ return 0;
+}
+
-+static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
++static int
++mt7530_apply_config(struct switch_dev *dev)
+{
-+ unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
-+ struct fe_priv *priv = netdev_priv(dev);
-+ dma_addr_t mapped_addr;
-+ u32 tx_next, tx, tx_num = 1;
++ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+ int i;
+
-+ if (priv->soc->min_pkt_len) {
-+ if (skb->len < priv->soc->min_pkt_len) {
-+ if (skb_padto(skb, priv->soc->min_pkt_len)) {
-+ printk(KERN_ERR
-+ "fe_eth: skb_padto failed\n");
-+ kfree_skb(skb);
-+ return 0;
-+ }
-+ skb_put(skb, priv->soc->min_pkt_len - skb->len);
-+ }
++ if (!priv->global_vlan_enable) {
++ mt7530_w32(priv, 0x2004, 0xff000);
++ mt7530_w32(priv, 0x2104, 0xff000);
++ mt7530_w32(priv, 0x2204, 0xff000);
++ mt7530_w32(priv, 0x2304, 0xff000);
++ mt7530_w32(priv, 0x2404, 0xff000);
++ mt7530_w32(priv, 0x2504, 0xff000);
++ mt7530_w32(priv, 0x2604, 0xff000);
++ mt7530_w32(priv, 0x2010, 0x810000c);
++ mt7530_w32(priv, 0x2110, 0x810000c);
++ mt7530_w32(priv, 0x2210, 0x810000c);
++ mt7530_w32(priv, 0x2310, 0x810000c);
++ mt7530_w32(priv, 0x2410, 0x810000c);
++ mt7530_w32(priv, 0x2510, 0x810000c);
++ mt7530_w32(priv, 0x2610, 0x810000c);
++ return 0;
+ }
+
-+ dev->trans_start = jiffies;
-+ mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
-+ skb->len, DMA_TO_DEVICE);
++ // LAN/WAN ports as security mode
++ mt7530_w32(priv, 0x2004, 0xff0003);
++ mt7530_w32(priv, 0x2104, 0xff0003);
++ mt7530_w32(priv, 0x2204, 0xff0003);
++ mt7530_w32(priv, 0x2304, 0xff0003);
++ mt7530_w32(priv, 0x2404, 0xff0003);
++ mt7530_w32(priv, 0x2504, 0xff0003);
++ // LAN/WAN ports as transparent port
++ mt7530_w32(priv, 0x2010, 0x810000c0);
++ mt7530_w32(priv, 0x2110, 0x810000c0);
++ mt7530_w32(priv, 0x2210, 0x810000c0);
++ mt7530_w32(priv, 0x2310, 0x810000c0);
++ mt7530_w32(priv, 0x2410, 0x810000c0);
++ mt7530_w32(priv, 0x2510, 0x810000c0);
+
-+ spin_lock(&priv->page_lock);
++ // set CPU/P7 port as user port
++ mt7530_w32(priv, 0x2610, 0x81000000);
++ mt7530_w32(priv, 0x2710, 0x81000000);
+
-+ tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
-+ if (priv->soc->tso && nr_frags)
-+ tx_num += nr_frags >> 1;
-+ tx_next = (tx + tx_num) % NUM_DMA_DESC;
-+ if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
-+ !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
-+ !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
-+ {
-+ spin_unlock(&priv->page_lock);
-+ dev->stats.tx_dropped++;
-+ kfree_skb(skb);
++ mt7530_w32(priv, 0x2604, 0x20ff0003);
++ mt7530_w32(priv, 0x2704, 0x20ff0003);
++ mt7530_w32(priv, 0x2610, 0x81000000);
+
-+ return NETDEV_TX_OK;
-+ }
++ for (i = 0; i < MT7530_NUM_VLANS; i++) {
++ u8 ports = priv->vlans[i].ports;
++ u32 val = mt7530_r32(priv, 0x100 + 4 * (i / 2));
+
-+ if (priv->soc->tso) {
-+ int t = tx_num;
++ if (i % 2 == 0) {
++ val &= 0xfff000;
++ val |= i;
++ } else {
++ val &= 0xfff;
++ val |= (i << 12);
++ }
++ mt7530_w32(priv, 0x100 + 4 * (i / 2), val);
+
-+ priv->tx_skb[(tx + t - 1) % NUM_DMA_DESC] = skb;
-+ while (--t)
-+ priv->tx_skb[(tx + t - 1) % NUM_DMA_DESC] = (struct sk_buff *) DMA_DUMMY_DESC;
-+ } else {
-+ priv->tx_skb[tx] = skb;
++ if (ports)
++ mt7530_w32(priv, REG_ESW_VLAN_VAWD1, BIT(30) | (ports << 16) | BIT(0));
++ else
++ mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
++
++ mt7530_vtcr(priv, 1, i);
+ }
-+ priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
-+ wmb();
+
-+ priv->tx_dma[tx].txd4 &= ~0x80;
-+ if (priv->soc->tx_dma)
-+ priv->soc->tx_dma(priv, tx, skb);
-+ else
-+ priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
++ for (i = 0; i < MT7530_NUM_PORTS; i++)
++ mt7530_w32(priv, 0x2014 + (0x100 * i), 0x10000 | priv->ports[i].pvid);
+
-+ if (skb->ip_summed == CHECKSUM_PARTIAL)
-+ priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
-+ else
-+ priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
++ return 0;
++}
+
-+ if (priv->soc->tso)
-+ fe_start_tso(skb, dev, nr_frags, tx);
++static int
++mt7530_get_port_link(struct switch_dev *dev, int port,
++ struct switch_port_link *link)
++{
++ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
++ u32 speed, pmsr;
+
-+ if (skb_shinfo(skb)->gso_segs > 1) {
-+ struct iphdr *iph = NULL;
-+ struct tcphdr *th = NULL;
-+ struct ipv6hdr *ip6h = NULL;
++ if (port < 0 || port >= MT7530_NUM_PORTS)
++ return -EINVAL;
+
-+ ip6h = (struct ipv6hdr *) skb_network_header(skb);
-+ iph = (struct iphdr *) skb_network_header(skb);
-+ if ((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
-+ th = (struct tcphdr *)skb_transport_header(skb);
-+ priv->tx_dma[tx].txd4 |= BIT(28);
-+ th->check = htons(skb_shinfo(skb)->gso_size);
-+ dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
-+ } else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) {
-+ th = (struct tcphdr *)skb_transport_header(skb);
-+ priv->tx_dma[tx].txd4 |= BIT(28);
-+ th->check = htons(skb_shinfo(skb)->gso_size);
-+ dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
-+ }
++ pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
++
++ link->link = pmsr & 1;
++ link->duplex = (pmsr >> 1) & 1;
++ speed = (pmsr >> 2) & 3;
++
++ switch (speed) {
++ case 0:
++ link->speed = SWITCH_PORT_SPEED_10;
++ break;
++ case 1:
++ link->speed = SWITCH_PORT_SPEED_100;
++ break;
++ case 2:
++ case 3: /* forced gige speed can be 2 or 3 */
++ link->speed = SWITCH_PORT_SPEED_1000;
++ break;
++ default:
++ link->speed = SWITCH_PORT_SPEED_UNKNOWN;
++ break;
+ }
+
-+ for (i = 0; i < tx_num; i++)
-+ dma_cache_sync(NULL, &priv->tx_dma[tx + i], sizeof(struct fe_tx_dma), DMA_TO_DEVICE);
++ return 0;
++}
+
-+ dev->stats.tx_packets++;
-+ dev->stats.tx_bytes += skb->len;
++static const struct switch_attr mt7530_global[] = {
++ {
++ .type = SWITCH_TYPE_INT,
++ .name = "enable_vlan",
++ .description = "VLAN mode (1:enabled)",
++ .max = 1,
++ .id = MT7530_ATTR_ENABLE_VLAN,
++ .get = mt7530_get_vlan_enable,
++ .set = mt7530_set_vlan_enable,
++ },
++};
+
-+ wmb();
-+ fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
-+ netdev_sent_queue(dev, skb->len);
++static const struct switch_attr mt7530_port[] = {
++};
+
-+ spin_unlock(&priv->page_lock);
++static const struct switch_attr mt7530_vlan[] = {
++};
+
-+ return NETDEV_TX_OK;
-+}
++static const struct switch_dev_ops mt7530_ops = {
++ .attr_global = {
++ .attr = mt7530_global,
++ .n_attr = ARRAY_SIZE(mt7530_global),
++ },
++ .attr_port = {
++ .attr = mt7530_port,
++ .n_attr = ARRAY_SIZE(mt7530_port),
++ },
++ .attr_vlan = {
++ .attr = mt7530_vlan,
++ .n_attr = ARRAY_SIZE(mt7530_vlan),
++ },
++ .get_vlan_ports = mt7530_get_vlan_ports,
++ .set_vlan_ports = mt7530_set_vlan_ports,
++ .get_port_pvid = mt7530_get_port_pvid,
++ .set_port_pvid = mt7530_set_port_pvid,
++ .get_port_link = mt7530_get_port_link,
++ .apply_config = mt7530_apply_config,
++ .reset_switch = mt7530_reset_switch,
++};
+
-+static int fe_poll_rx(struct napi_struct *napi, int budget)
++int
++mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus)
+{
-+ struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
-+ int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
-+ int complete = 0;
-+ int rx = 0;
++ struct switch_dev *swdev;
++ struct mt7530_priv *mt7530;
++ struct mt7530_mapping *map;
++ int ret;
+
-+ while ((rx < budget) && !complete) {
-+ idx = (idx + 1) % NUM_DMA_DESC;
++ if (bus && bus->phy_map[0x1f]->phy_id != 0x1beef)
++ return 0;
+
-+ if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
-+ struct sk_buff *new_skb = fe_alloc_skb(priv);
++ mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
++ if (!mt7530)
++ return -ENOMEM;
+
-+ if (new_skb) {
-+ int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
-+ dma_addr_t dma_addr;
++ mt7530->base = base;
++ mt7530->bus = bus;
++ mt7530->global_vlan_enable = 1;
+
-+ dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
-+ MAX_RX_LENGTH, DMA_FROM_DEVICE);
++ swdev = &mt7530->swdev;
++ swdev->name = "mt7530";
++ swdev->alias = "mt7530";
++ swdev->cpu_port = MT7530_CPU_PORT;
++ swdev->ports = MT7530_NUM_PORTS;
++ swdev->vlans = MT7530_NUM_VLANS;
++ swdev->ops = &mt7530_ops;
+
-+ skb_put(priv->rx_skb[idx], pktlen);
-+ priv->rx_skb[idx]->dev = priv->netdev;
-+ priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
-+ if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
-+ priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
-+ else
-+ priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
-+ priv->netdev->stats.rx_packets++;
-+ priv->netdev->stats.rx_bytes += pktlen;
++ ret = register_switch(swdev, NULL);
++ if (ret) {
++ dev_err(dev, "failed to register mt7530\n");
++ return ret;
++ }
+
-+#ifdef CONFIG_INET_LRO
-+ if (priv->soc->get_skb_header && priv->rx_skb[idx]->ip_summed == CHECKSUM_UNNECESSARY)
-+ lro_receive_skb(&priv->lro_mgr, priv->rx_skb[idx], NULL);
-+ else
-+#endif
-+ netif_receive_skb(priv->rx_skb[idx]);
++ dev_info(dev, "loaded mt7530 driver\n");
+
-+ priv->rx_skb[idx] = new_skb;
++ map = mt7530_find_mapping(dev->of_node);
++ if (map)
++ mt7530_apply_mapping(mt7530, map);
++ mt7530_apply_config(swdev);
+
-+ dma_addr = dma_map_single(&priv->netdev->dev,
-+ new_skb->data,
-+ MAX_RX_LENGTH,
-+ DMA_FROM_DEVICE);
-+ priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
-+ wmb();
-+ } else {
-+ priv->netdev->stats.rx_dropped++;
-+ }
++ return 0;
++}
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/mt7530.h
+@@ -0,0 +1,20 @@
++/*
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
+
-+ if (priv->soc->rx_dma)
-+ priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
-+ else
-+ priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
-+ fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
++#ifndef _MT7530_H__
++#define _MT7530_H__
+
-+ rx++;
-+ } else {
-+ complete = 1;
-+ }
-+ }
++int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus);
+
-+#ifdef CONFIG_INET_LRO
-+ if (priv->soc->get_skb_header)
-+ lro_flush_all(&priv->lro_mgr);
+#endif
-+ if (complete) {
-+ napi_complete(&priv->rx_napi);
-+ fe_int_enable(priv->soc->rx_dly_int);
-+ }
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c
+@@ -0,0 +1,845 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
+
-+ return rx;
-+}
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/dma-mapping.h>
++#include <linux/init.h>
++#include <linux/skbuff.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/platform_device.h>
++#include <linux/of_device.h>
++#include <linux/clk.h>
++#include <linux/of_net.h>
++#include <linux/of_mdio.h>
++#include <linux/if_vlan.h>
++#include <linux/reset.h>
+
-+static void fe_tx_housekeeping(unsigned long ptr)
-+{
-+ struct net_device *dev = (struct net_device*)ptr;
-+ struct fe_priv *priv = netdev_priv(dev);
-+ unsigned int bytes_compl = 0;
-+ unsigned int pkts_compl = 0;
++#include <asm/mach-ralink/ralink_regs.h>
+
-+ spin_lock(&priv->page_lock);
-+ while (1) {
-+ struct fe_tx_dma *txd;
++#include "ralink_soc_eth.h"
++#include "esw_rt3052.h"
++#include "mdio.h"
+
-+ txd = &priv->tx_dma[priv->tx_free_idx];
++#define TX_TIMEOUT (2 * HZ)
++#define MAX_RX_LENGTH 1536
++#define DMA_DUMMY_DESC 0xffffffff
+
-+ if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
-+ break;
++static const u32 fe_reg_table_default[FE_REG_COUNT] = {
++ [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
++ [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
++ [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
++ [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
++ [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
++ [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
++ [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
++ [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
++ [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
++ [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
++ [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
++};
+
-+ if (priv->tx_skb[priv->tx_free_idx] != (struct sk_buff *) DMA_DUMMY_DESC) {
-+ bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
-+ dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
-+ }
-+ pkts_compl++;
-+ priv->tx_skb[priv->tx_free_idx] = NULL;
-+ priv->tx_free_idx++;
-+ if (priv->tx_free_idx >= NUM_DMA_DESC)
-+ priv->tx_free_idx = 0;
-+ }
++static const u32 *fe_reg_table = fe_reg_table_default;
+
-+ netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
-+ spin_unlock(&priv->page_lock);
++static void __iomem *fe_base = 0;
+
-+ fe_int_enable(priv->soc->tx_dly_int);
++void fe_w32(u32 val, unsigned reg)
++{
++ __raw_writel(val, fe_base + reg);
+}
+
-+static void fe_tx_timeout(struct net_device *dev)
++u32 fe_r32(unsigned reg)
+{
-+ struct fe_priv *priv = netdev_priv(dev);
-+
-+ tasklet_schedule(&priv->tx_tasklet);
-+ priv->netdev->stats.tx_errors++;
-+ netdev_err(dev, "transmit timed out, waking up the queue\n");
-+ netif_wake_queue(dev);
++ return __raw_readl(fe_base + reg);
+}
+
-+static irqreturn_t fe_handle_irq(int irq, void *dev)
++static inline void fe_reg_w32(u32 val, enum fe_reg reg)
+{
-+ struct fe_priv *priv = netdev_priv(dev);
-+ unsigned int status;
-+ unsigned int mask;
-+
-+ status = fe_reg_r32(FE_REG_FE_INT_STATUS);
-+ mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
++ fe_w32(val, fe_reg_table[reg]);
++}
+
-+ if (!(status & mask))
-+ return IRQ_NONE;
++static inline u32 fe_reg_r32(enum fe_reg reg)
++{
++ return fe_r32(fe_reg_table[reg]);
++}
+
-+ if (status & priv->soc->rx_dly_int) {
-+ fe_int_disable(priv->soc->rx_dly_int);
-+ napi_schedule(&priv->rx_napi);
-+ }
++static inline void fe_int_disable(u32 mask)
++{
++ fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
++ FE_REG_FE_INT_ENABLE);
++ /* flush write */
++ fe_reg_r32(FE_REG_FE_INT_ENABLE);
++}
+
-+ if (status & priv->soc->tx_dly_int) {
-+ fe_int_disable(priv->soc->tx_dly_int);
-+ tasklet_schedule(&priv->tx_tasklet);
-+ }
++static inline void fe_int_enable(u32 mask)
++{
++ fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
++ FE_REG_FE_INT_ENABLE);
++ /* flush write */
++ fe_reg_r32(FE_REG_FE_INT_ENABLE);
++}
+
-+ fe_reg_w32(status, FE_REG_FE_INT_STATUS);
++static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
++{
++ unsigned long flags;
+
-+ return IRQ_HANDLED;
++ spin_lock_irqsave(&priv->page_lock, flags);
++ fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
++ fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
++ FE_GDMA1_MAC_ADRL);
++ spin_unlock_irqrestore(&priv->page_lock, flags);
+}
+
-+static int fe_hw_init(struct net_device *dev)
++static int fe_set_mac_address(struct net_device *dev, void *p)
+{
-+ struct fe_priv *priv = netdev_priv(dev);
-+ int err;
++ int ret = eth_mac_addr(dev, p);
+
-+ err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
-+ dev_name(priv->device), dev);
-+ if (err)
-+ return err;
++ if (!ret) {
++ struct fe_priv *priv = netdev_priv(dev);
+
-+ err = fe_alloc_rx(priv);
-+ if (!err)
-+ err = fe_alloc_tx(priv);
-+ if (err)
-+ return err;
++ if (priv->soc->set_mac)
++ priv->soc->set_mac(priv, dev->dev_addr);
++ else
++ fe_hw_set_macaddr(priv, p);
++ }
+
-+ if (priv->soc->set_mac)
-+ priv->soc->set_mac(priv, dev->dev_addr);
-+ else
-+ fe_hw_set_macaddr(priv, dev->dev_addr);
++ return ret;
++}
+
-+ fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
++static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
++{
++ struct sk_buff *skb;
+
-+ fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
++ skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
++ if (!skb)
++ return NULL;
+
-+ tasklet_init(&priv->tx_tasklet, fe_tx_housekeeping, (unsigned long)dev);
++ skb_reserve(skb, NET_IP_ALIGN);
+
-+ if (priv->soc->fwd_config) {
-+ priv->soc->fwd_config(priv);
-+ } else {
-+ unsigned long sysclk = priv->sysclk;
++ return skb;
++}
+
-+ if (!sysclk) {
-+ netdev_err(dev, "unable to get clock\n");
-+ return -EINVAL;
-+ }
++static int fe_alloc_rx(struct fe_priv *priv)
++{
++ int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
++ int i;
+
-+ sysclk /= FE_US_CYC_CNT_DIVISOR;
-+ sysclk <<= FE_US_CYC_CNT_SHIFT;
++ priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
++ &priv->rx_phys, GFP_ATOMIC);
++ if (!priv->rx_dma)
++ return -ENOMEM;
+
-+ fe_w32((fe_r32(FE_FE_GLO_CFG) &
-+ ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
-+ FE_FE_GLO_CFG);
++ memset(priv->rx_dma, 0, size);
+
-+ fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
-+ fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
-+ FE_GDMA1_FWD_CFG);
-+ fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
-+ FE_CDMA_CSG_CFG);
-+ fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
++ for (i = 0; i < NUM_DMA_DESC; i++) {
++ priv->rx_skb[i] = fe_alloc_skb(priv);
++ if (!priv->rx_skb[i])
++ return -ENOMEM;
+ }
+
-+ fe_w32(1, FE_FE_RST_GL);
-+ fe_w32(0, FE_FE_RST_GL);
++ for (i = 0; i < NUM_DMA_DESC; i++) {
++ dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
++ priv->rx_skb[i]->data,
++ MAX_RX_LENGTH,
++ DMA_FROM_DEVICE);
++ priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
++
++ if (priv->soc->rx_dma)
++ priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
++ else
++ priv->rx_dma[i].rxd2 = RX_DMA_LSO;
++ }
++ wmb();
++
++ fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
++ fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
++ fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
++ fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
+
+ return 0;
+}
+
-+static int fe_open(struct net_device *dev)
++static int fe_alloc_tx(struct fe_priv *priv)
+{
-+ struct fe_priv *priv = netdev_priv(dev);
-+ unsigned long flags;
-+ u32 val;
++ int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
++ int i;
+
-+ spin_lock_irqsave(&priv->page_lock, flags);
-+ napi_enable(&priv->rx_napi);
++ priv->tx_free_idx = 0;
+
-+ val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
-+ val |= priv->soc->pdma_glo_cfg;
-+ fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
++ priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
++ &priv->tx_phys, GFP_ATOMIC);
++ if (!priv->tx_dma)
++ return -ENOMEM;
+
-+ spin_unlock_irqrestore(&priv->page_lock, flags);
++ memset(priv->tx_dma, 0, size);
+
-+ if (priv->phy)
-+ priv->phy->start(priv);
++ for (i = 0; i < NUM_DMA_DESC; i++) {
++ if (priv->soc->tx_dma) {
++ priv->soc->tx_dma(priv, i, NULL);
++ continue;
++ }
+
-+ if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
-+ netif_carrier_on(dev);
++ priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
++ priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
++ }
+
-+ netif_start_queue(dev);
-+ fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
++ fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
++ fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
++ fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
++ fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
+
+ return 0;
+}
+
-+static int fe_stop(struct net_device *dev)
++static void fe_free_dma(struct fe_priv *priv)
+{
-+ struct fe_priv *priv = netdev_priv(dev);
-+ unsigned long flags;
-+
-+ fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
++ int i;
+
-+ netif_stop_queue(dev);
++ for (i = 0; i < NUM_DMA_DESC; i++) {
++ if (priv->rx_skb[i]) {
++ dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
++ MAX_RX_LENGTH, DMA_FROM_DEVICE);
++ dev_kfree_skb_any(priv->rx_skb[i]);
++ priv->rx_skb[i] = NULL;
++ }
+
-+ if (priv->phy)
-+ priv->phy->stop(priv);
++ if (priv->tx_skb[i]) {
++ dev_kfree_skb_any(priv->tx_skb[i]);
++ priv->tx_skb[i] = NULL;
++ }
++ }
+
-+ spin_lock_irqsave(&priv->page_lock, flags);
-+ napi_disable(&priv->rx_napi);
++ if (priv->rx_dma) {
++ int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
++ dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
++ priv->rx_phys);
++ }
+
-+ fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
-+ ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
-+ FE_REG_PDMA_GLO_CFG);
-+ spin_unlock_irqrestore(&priv->page_lock, flags);
++ if (priv->tx_dma) {
++ int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
++ dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
++ priv->tx_phys);
++ }
+
-+ return 0;
++ netdev_reset_queue(priv->netdev);
+}
+
-+static int __init fe_init(struct net_device *dev)
++static void fe_start_tso(struct sk_buff *skb, struct net_device *dev, unsigned int nr_frags, int idx)
+{
-+ struct fe_priv *priv = netdev_priv(dev);
-+ struct device_node *port;
-+ int err;
-+
-+ BUG_ON(!priv->soc->reset_fe);
-+ priv->soc->reset_fe();
++ struct fe_priv *priv = netdev_priv(dev);
++ struct skb_frag_struct *frag;
++ int i;
+
-+ if (priv->soc->switch_init)
-+ priv->soc->switch_init(priv);
++ for (i = 0; i < nr_frags; i++) {
++ dma_addr_t mapped_addr;
+
-+ net_srandom(jiffies);
-+ memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
-+ of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
++ frag = &skb_shinfo(skb)->frags[i];
++ mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0, skb_frag_size(frag), DMA_TO_DEVICE);
++ if (i % 2) {
++ idx = (idx + 1) % NUM_DMA_DESC;
++ priv->tx_dma[idx].txd1 = mapped_addr;
++ if (i == nr_frags - 1)
++ priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(frag->size);
++ else
++ priv->tx_dma[idx].txd2 = TX_DMA_PLEN0(frag->size);
++ } else {
++ priv->tx_dma[idx].txd3 = mapped_addr;
++ if (i == nr_frags - 1)
++ priv->tx_dma[idx].txd2 |= TX_DMA_LS1 | TX_DMA_PLEN1(frag->size);
++ else
++ priv->tx_dma[idx].txd2 |= TX_DMA_PLEN1(frag->size);
++ }
++ }
++}
+
-+ err = fe_mdio_init(priv);
-+ if (err)
-+ return err;
++static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
++{
++ unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
++ struct fe_priv *priv = netdev_priv(dev);
++ dma_addr_t mapped_addr;
++ u32 tx_next, tx, tx_num = 1;
++ int i;
+
-+ if (priv->phy) {
-+ err = priv->phy->connect(priv);
-+ if (err)
-+ goto err_mdio_cleanup;
++ if (priv->soc->min_pkt_len) {
++ if (skb->len < priv->soc->min_pkt_len) {
++ if (skb_padto(skb, priv->soc->min_pkt_len)) {
++ printk(KERN_ERR
++ "fe_eth: skb_padto failed\n");
++ kfree_skb(skb);
++ return 0;
++ }
++ skb_put(skb, priv->soc->min_pkt_len - skb->len);
++ }
+ }
+
-+ if (priv->soc->port_init)
-+ for_each_child_of_node(priv->device->of_node, port)
-+ if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
-+ priv->soc->port_init(priv, port);
++ dev->trans_start = jiffies;
++ mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
++ skb->len, DMA_TO_DEVICE);
+
-+ err = fe_hw_init(dev);
-+ if (err)
-+ goto err_phy_disconnect;
++ spin_lock(&priv->page_lock);
+
-+ if (priv->soc->switch_config)
-+ priv->soc->switch_config(priv);
++ tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
++ if (priv->soc->tso && nr_frags)
++ tx_num += nr_frags >> 1;
++ tx_next = (tx + tx_num) % NUM_DMA_DESC;
++ if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
++ !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
++ !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
++ {
++ spin_unlock(&priv->page_lock);
++ dev->stats.tx_dropped++;
++ kfree_skb(skb);
+
-+ return 0;
++ return NETDEV_TX_OK;
++ }
+
-+err_phy_disconnect:
-+ if (priv->phy)
-+ priv->phy->disconnect(priv);
-+err_mdio_cleanup:
-+ fe_mdio_cleanup(priv);
++ if (priv->soc->tso) {
++ int t = tx_num;
+
-+ return err;
-+}
++ priv->tx_skb[(tx + t - 1) % NUM_DMA_DESC] = skb;
++ while (--t)
++ priv->tx_skb[(tx + t - 1) % NUM_DMA_DESC] = (struct sk_buff *) DMA_DUMMY_DESC;
++ } else {
++ priv->tx_skb[tx] = skb;
++ }
++ priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
++ wmb();
+
-+static void fe_uninit(struct net_device *dev)
-+{
-+ struct fe_priv *priv = netdev_priv(dev);
++ priv->tx_dma[tx].txd4 &= ~0x80;
++ if (priv->soc->tx_dma)
++ priv->soc->tx_dma(priv, tx, skb);
++ else
++ priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
+
-+ tasklet_kill(&priv->tx_tasklet);
++ if (skb->ip_summed == CHECKSUM_PARTIAL)
++ priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
++ else
++ priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
+
-+ if (priv->phy)
-+ priv->phy->disconnect(priv);
-+ fe_mdio_cleanup(priv);
++ if (priv->soc->tso)
++ fe_start_tso(skb, dev, nr_frags, tx);
+
-+ fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
-+ free_irq(dev->irq, dev);
++ if (priv->soc->tso && (skb_shinfo(skb)->gso_segs > 1)) {
++ struct iphdr *iph = NULL;
++ struct tcphdr *th = NULL;
++ struct ipv6hdr *ip6h = NULL;
+
-+ fe_free_dma(priv);
-+}
++ ip6h = (struct ipv6hdr *) skb_network_header(skb);
++ iph = (struct iphdr *) skb_network_header(skb);
++ if ((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
++ th = (struct tcphdr *)skb_transport_header(skb);
++ priv->tx_dma[tx].txd4 |= BIT(28);
++ th->check = htons(skb_shinfo(skb)->gso_size);
++ dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
++ } else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) {
++ th = (struct tcphdr *)skb_transport_header(skb);
++ priv->tx_dma[tx].txd4 |= BIT(28);
++ th->check = htons(skb_shinfo(skb)->gso_size);
++ dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
++ }
++ }
+
-+static const struct net_device_ops fe_netdev_ops = {
-+ .ndo_init = fe_init,
-+ .ndo_uninit = fe_uninit,
-+ .ndo_open = fe_open,
-+ .ndo_stop = fe_stop,
-+ .ndo_start_xmit = fe_start_xmit,
-+ .ndo_tx_timeout = fe_tx_timeout,
-+ .ndo_set_mac_address = fe_set_mac_address,
-+ .ndo_change_mtu = eth_change_mtu,
-+ .ndo_validate_addr = eth_validate_addr,
-+};
++ for (i = 0; i < tx_num; i++)
++ dma_cache_sync(NULL, &priv->tx_dma[tx + i], sizeof(struct fe_tx_dma), DMA_TO_DEVICE);
+
-+static int fe_probe(struct platform_device *pdev)
-+{
-+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ const struct of_device_id *match;
-+ struct fe_soc_data *soc = NULL;
-+ struct net_device *netdev;
-+ struct fe_priv *priv;
-+ struct clk *sysclk;
-+ int err;
++ dev->stats.tx_packets++;
++ dev->stats.tx_bytes += skb->len;
+
-+ device_reset(&pdev->dev);
++ wmb();
++ fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
++ netdev_sent_queue(dev, skb->len);
+
-+ match = of_match_device(of_fe_match, &pdev->dev);
-+ soc = (struct fe_soc_data *) match->data;
++ spin_unlock(&priv->page_lock);
+
-+ if (soc->init_data)
-+ soc->init_data(soc);
-+ if (soc->reg_table)
-+ fe_reg_table = soc->reg_table;
++ return NETDEV_TX_OK;
++}
+
-+ fe_base = devm_request_and_ioremap(&pdev->dev, res);
-+ if (!fe_base)
-+ return -ENOMEM;
++static int fe_poll_rx(struct napi_struct *napi, int budget)
++{
++ struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
++ int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
++ int complete = 0;
++ int rx = 0;
+
-+ netdev = alloc_etherdev(sizeof(struct fe_priv));
-+ if (!netdev) {
-+ dev_err(&pdev->dev, "alloc_etherdev failed\n");
-+ return -ENOMEM;
-+ }
++ while ((rx < budget) && !complete) {
++ idx = (idx + 1) % NUM_DMA_DESC;
+
-+ strcpy(netdev->name, "eth%d");
-+ netdev->netdev_ops = &fe_netdev_ops;
-+ netdev->base_addr = (unsigned long) fe_base;
-+ netdev->watchdog_timeo = TX_TIMEOUT;
-+ netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
++ if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
++ struct sk_buff *new_skb = fe_alloc_skb(priv);
+
-+ if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
-+ netdev->features |= NETIF_F_HW_VLAN_CTAG_TX;
++ if (new_skb) {
++ int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
++ dma_addr_t dma_addr;
+
-+ if (soc->tso) {
-+ dev_info(&pdev->dev, "Enabling TSO\n");
-+ netdev->features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
-+ }
++ dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
++ MAX_RX_LENGTH, DMA_FROM_DEVICE);
+
-+ netdev->hw_features = netdev->vlan_features = netdev->features;
++ skb_put(priv->rx_skb[idx], pktlen);
++ priv->rx_skb[idx]->dev = priv->netdev;
++ priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
++ if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
++ priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
++ else
++ priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
++ priv->netdev->stats.rx_packets++;
++ priv->netdev->stats.rx_bytes += pktlen;
+
-+ netdev->irq = platform_get_irq(pdev, 0);
-+ if (netdev->irq < 0) {
-+ dev_err(&pdev->dev, "no IRQ resource found\n");
-+ kfree(netdev);
-+ return -ENXIO;
-+ }
++#ifdef CONFIG_INET_LRO
++ if (priv->soc->get_skb_header && priv->rx_skb[idx]->ip_summed == CHECKSUM_UNNECESSARY)
++ lro_receive_skb(&priv->lro_mgr, priv->rx_skb[idx], NULL);
++ else
++#endif
++ netif_receive_skb(priv->rx_skb[idx]);
+
-+ priv = netdev_priv(netdev);
-+ memset(priv, 0, sizeof(struct fe_priv));
-+ spin_lock_init(&priv->page_lock);
++ priv->rx_skb[idx] = new_skb;
+
-+ sysclk = devm_clk_get(&pdev->dev, NULL);
-+ if (!IS_ERR(sysclk))
-+ priv->sysclk = clk_get_rate(sysclk);
++ dma_addr = dma_map_single(&priv->netdev->dev,
++ new_skb->data,
++ MAX_RX_LENGTH,
++ DMA_FROM_DEVICE);
++ priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
++ wmb();
++ } else {
++ priv->netdev->stats.rx_dropped++;
++ }
+
-+ priv->netdev = netdev;
-+ priv->device = &pdev->dev;
-+ priv->soc = soc;
++ if (priv->soc->rx_dma)
++ priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
++ else
++ priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
++ fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
+
-+ err = register_netdev(netdev);
-+ if (err) {
-+ dev_err(&pdev->dev, "error bringing up device\n");
-+ kfree(netdev);
-+ return err;
++ rx++;
++ } else {
++ complete = 1;
++ }
+ }
-+ netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
+
+#ifdef CONFIG_INET_LRO
-+ if (priv->soc->get_skb_header) {
-+ priv->lro_mgr.dev = netdev;
-+ memset(&priv->lro_mgr.stats, 0, sizeof(priv->lro_mgr.stats));
-+ priv->lro_mgr.features = LRO_F_NAPI;
-+ priv->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
-+ priv->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
-+ priv->lro_mgr.max_desc = ARRAY_SIZE(priv->lro_arr);
-+ priv->lro_mgr.max_aggr = 64;
-+ priv->lro_mgr.frag_align_pad = 0;
-+ priv->lro_mgr.lro_arr = priv->lro_arr;
-+ priv->lro_mgr.get_skb_header = priv->soc->get_skb_header;
-+ }
++ if (priv->soc->get_skb_header)
++ lro_flush_all(&priv->lro_mgr);
+#endif
++ if (complete) {
++ napi_complete(&priv->rx_napi);
++ fe_int_enable(priv->soc->rx_dly_int);
++ }
+
-+ platform_set_drvdata(pdev, netdev);
-+
-+ netdev_info(netdev, "done loading\n");
-+
-+ return 0;
++ return rx;
+}
+
-+static int fe_remove(struct platform_device *pdev)
++static void fe_tx_housekeeping(unsigned long ptr)
+{
-+ struct net_device *dev = platform_get_drvdata(pdev);
++ struct net_device *dev = (struct net_device*)ptr;
+ struct fe_priv *priv = netdev_priv(dev);
++ unsigned int bytes_compl = 0;
++ unsigned int pkts_compl = 0;
+
-+ netif_stop_queue(dev);
-+ netif_napi_del(&priv->rx_napi);
-+
-+ unregister_netdev(dev);
-+ free_netdev(dev);
-+
-+ return 0;
-+}
++ spin_lock(&priv->page_lock);
++ while (1) {
++ struct fe_tx_dma *txd;
+
-+static struct platform_driver fe_driver = {
-+ .probe = fe_probe,
-+ .remove = fe_remove,
-+ .driver = {
-+ .name = "ralink_soc_eth",
-+ .owner = THIS_MODULE,
-+ .of_match_table = of_fe_match,
-+ },
-+};
++ txd = &priv->tx_dma[priv->tx_free_idx];
+
-+static int __init init_rtfe(void)
-+{
-+ int ret;
++ if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
++ break;
+
-+ ret = rtesw_init();
-+ if (ret)
-+ return ret;
++ if (priv->tx_skb[priv->tx_free_idx] != (struct sk_buff *) DMA_DUMMY_DESC) {
++ bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
++ dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
++ }
++ pkts_compl++;
++ priv->tx_skb[priv->tx_free_idx] = NULL;
++ priv->tx_free_idx++;
++ if (priv->tx_free_idx >= NUM_DMA_DESC)
++ priv->tx_free_idx = 0;
++ }
+
-+ ret = platform_driver_register(&fe_driver);
-+ if (ret)
-+ rtesw_exit();
++ netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
++ spin_unlock(&priv->page_lock);
+
-+ return ret;
++ fe_int_enable(priv->soc->tx_dly_int);
+}
+
-+static void __exit exit_rtfe(void)
++static void fe_tx_timeout(struct net_device *dev)
+{
-+ platform_driver_unregister(&fe_driver);
-+ rtesw_exit();
++ struct fe_priv *priv = netdev_priv(dev);
++
++ tasklet_schedule(&priv->tx_tasklet);
++ priv->netdev->stats.tx_errors++;
++ netdev_err(dev, "transmit timed out, waking up the queue\n");
++ netif_wake_queue(dev);
+}
+
-+module_init(init_rtfe);
-+module_exit(exit_rtfe);
++static irqreturn_t fe_handle_irq(int irq, void *dev)
++{
++ struct fe_priv *priv = netdev_priv(dev);
++ unsigned int status;
++ unsigned int mask;
+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-+MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
---- /dev/null
-+++ b/drivers/net/ethernet/ralink/ralink_soc_eth.h
-@@ -0,0 +1,384 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ * based on Ralink SDK3.3
-+ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
-+ */
++ status = fe_reg_r32(FE_REG_FE_INT_STATUS);
++ mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
+
-+#ifndef FE_ETH_H
-+#define FE_ETH_H
++ if (!(status & mask))
++ return IRQ_NONE;
+
-+#include <linux/mii.h>
-+#include <linux/interrupt.h>
-+#include <linux/netdevice.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/phy.h>
-+#include <linux/inet_lro.h>
++ if (status & priv->soc->rx_dly_int) {
++ fe_int_disable(priv->soc->rx_dly_int);
++ napi_schedule(&priv->rx_napi);
++ }
+
++ if (status & priv->soc->tx_dly_int) {
++ fe_int_disable(priv->soc->tx_dly_int);
++ tasklet_schedule(&priv->tx_tasklet);
++ }
+
-+enum fe_reg {
-+ FE_REG_PDMA_GLO_CFG = 0,
-+ FE_REG_PDMA_RST_CFG,
-+ FE_REG_DLY_INT_CFG,
-+ FE_REG_TX_BASE_PTR0,
-+ FE_REG_TX_MAX_CNT0,
-+ FE_REG_TX_CTX_IDX0,
-+ FE_REG_RX_BASE_PTR0,
-+ FE_REG_RX_MAX_CNT0,
-+ FE_REG_RX_CALC_IDX0,
-+ FE_REG_FE_INT_ENABLE,
-+ FE_REG_FE_INT_STATUS,
-+ FE_REG_FE_DMA_VID_BASE,
-+ FE_REG_COUNT
-+};
++ fe_reg_w32(status, FE_REG_FE_INT_STATUS);
+
-+#define NUM_DMA_DESC 0x100
++ return IRQ_HANDLED;
++}
+
-+#define FE_DELAY_EN_INT 0x80
-+#define FE_DELAY_MAX_INT 0x04
-+#define FE_DELAY_MAX_TOUT 0x04
-+#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
-+#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
-+#define FE_PSE_FQFC_CFG_INIT 0x80504000
++static int fe_hw_init(struct net_device *dev)
++{
++ struct fe_priv *priv = netdev_priv(dev);
++ int err;
+
-+/* interrupt bits */
-+#define FE_CNT_PPE_AF BIT(31)
-+#define FE_CNT_GDM_AF BIT(29)
-+#define FE_PSE_P2_FC BIT(26)
-+#define FE_PSE_BUF_DROP BIT(24)
-+#define FE_GDM_OTHER_DROP BIT(23)
-+#define FE_PSE_P1_FC BIT(22)
-+#define FE_PSE_P0_FC BIT(21)
-+#define FE_PSE_FQ_EMPTY BIT(20)
-+#define FE_GE1_STA_CHG BIT(18)
-+#define FE_TX_COHERENT BIT(17)
-+#define FE_RX_COHERENT BIT(16)
-+#define FE_TX_DONE_INT3 BIT(11)
-+#define FE_TX_DONE_INT2 BIT(10)
-+#define FE_TX_DONE_INT1 BIT(9)
-+#define FE_TX_DONE_INT0 BIT(8)
-+#define FE_RX_DONE_INT0 BIT(2)
-+#define FE_TX_DLY_INT BIT(1)
-+#define FE_RX_DLY_INT BIT(0)
++ err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
++ dev_name(priv->device), dev);
++ if (err)
++ return err;
+
-+#define RT5350_RX_DLY_INT BIT(30)
-+#define RT5350_TX_DLY_INT BIT(28)
++ err = fe_alloc_rx(priv);
++ if (!err)
++ err = fe_alloc_tx(priv);
++ if (err)
++ return err;
+
-+/* registers */
-+#define FE_FE_OFFSET 0x0000
-+#define FE_GDMA_OFFSET 0x0020
-+#define FE_PSE_OFFSET 0x0040
-+#define FE_GDMA2_OFFSET 0x0060
-+#define FE_CDMA_OFFSET 0x0080
-+#define FE_DMA_VID0 0x00a8
-+#define FE_PDMA_OFFSET 0x0100
-+#define FE_PPE_OFFSET 0x0200
-+#define FE_CMTABLE_OFFSET 0x0400
-+#define FE_POLICYTABLE_OFFSET 0x1000
++ if (priv->soc->set_mac)
++ priv->soc->set_mac(priv, dev->dev_addr);
++ else
++ fe_hw_set_macaddr(priv, dev->dev_addr);
+
-+#define RT5350_PDMA_OFFSET 0x0800
-+#define RT5350_SDM_OFFSET 0x0c00
++ fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
+
-+#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
-+#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
-+#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
-+#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
-+#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
-+#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
-+#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
-+#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
++ fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
+
-+#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
-+#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
-+#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
-+#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
-+#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
++ tasklet_init(&priv->tx_tasklet, fe_tx_housekeeping, (unsigned long)dev);
+
-+#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
-+#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
-+#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
-+#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
-+#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
++ if (priv->soc->fwd_config) {
++ priv->soc->fwd_config(priv);
++ } else {
++ unsigned long sysclk = priv->sysclk;
+
-+#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
-+#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
-+#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
-+#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
++ if (!sysclk) {
++ netdev_err(dev, "unable to get clock\n");
++ return -EINVAL;
++ }
+
-+#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
-+#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
++ sysclk /= FE_US_CYC_CNT_DIVISOR;
++ sysclk <<= FE_US_CYC_CNT_SHIFT;
+
-+#define MT7620A_GDMA_OFFSET 0x0600
-+#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
-+#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
-+#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
-+#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
-+#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
++ fe_w32((fe_r32(FE_FE_GLO_CFG) &
++ ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
++ FE_FE_GLO_CFG);
+
-+#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
-+#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
-+#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
-+#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
-+#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
-+#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
-+#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
-+#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
-+#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
-+#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
-+#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
-+#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
-+#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
-+#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
-+#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
-+#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
-+#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
-+#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
-+#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
-+#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
-+#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
-+#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
-+#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
-+#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
-+#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
-+#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
-+#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
-+#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
-+#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
-+#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
-+
-+#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
-+#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
-+#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
-+#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
-+#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
-+#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
-+#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
-+#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
-+#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
-+#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
-+#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
-+#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
-+#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
-+#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
-+#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
-+#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
-+#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
-+#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
-+#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
-+#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
-+#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
-+#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
-+#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
-+#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
-+#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
-+#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
-+#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
-+#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
++ fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
++ fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
++ FE_GDMA1_FWD_CFG);
++ fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
++ FE_CDMA_CSG_CFG);
++ fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
++ }
+
-+#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
-+#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
-+#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
-+#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
-+#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
-+#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
-+#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
-+#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
-+#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
-+#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
++ fe_w32(1, FE_FE_RST_GL);
++ fe_w32(0, FE_FE_RST_GL);
+
-+#define RT5350_SDM_ICS_EN BIT(16)
-+#define RT5350_SDM_TCS_EN BIT(17)
-+#define RT5350_SDM_UCS_EN BIT(18)
++ return 0;
++}
+
++static int fe_open(struct net_device *dev)
++{
++ struct fe_priv *priv = netdev_priv(dev);
++ unsigned long flags;
++ u32 val;
+
-+/* MDIO_CFG register bits */
-+#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
-+#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
-+#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
-+#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
-+#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
-+#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
-+#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
-+#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
-+#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
-+#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
-+#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
-+#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
-+#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
-+#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
-+#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
-+#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
-+#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
-+#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
-+#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
-+#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
-+#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
-+#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
-+#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
-+#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
-+#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
++ spin_lock_irqsave(&priv->page_lock, flags);
++ napi_enable(&priv->rx_napi);
+
-+/* uni-cast port */
-+#define FE_GDM1_ICS_EN BIT(22)
-+#define FE_GDM1_TCS_EN BIT(21)
-+#define FE_GDM1_UCS_EN BIT(20)
-+#define FE_GDM1_JMB_EN BIT(19)
-+#define FE_GDM1_STRPCRC BIT(16)
-+#define FE_GDM1_UFRC_P_CPU (0 << 12)
-+#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
-+#define FE_GDM1_UFRC_P_PPE (6 << 12)
++ val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
++ val |= priv->soc->pdma_glo_cfg;
++ fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
+
-+/* checksums */
-+#define FE_ICS_GEN_EN BIT(2)
-+#define FE_UCS_GEN_EN BIT(1)
-+#define FE_TCS_GEN_EN BIT(0)
++ spin_unlock_irqrestore(&priv->page_lock, flags);
+
-+/* dma ring */
-+#define FE_PST_DRX_IDX0 BIT(16)
-+#define FE_PST_DTX_IDX3 BIT(3)
-+#define FE_PST_DTX_IDX2 BIT(2)
-+#define FE_PST_DTX_IDX1 BIT(1)
-+#define FE_PST_DTX_IDX0 BIT(0)
++ if (priv->phy)
++ priv->phy->start(priv);
+
-+#define FE_TX_WB_DDONE BIT(6)
-+#define FE_RX_DMA_BUSY BIT(3)
-+#define FE_TX_DMA_BUSY BIT(1)
-+#define FE_RX_DMA_EN BIT(2)
-+#define FE_TX_DMA_EN BIT(0)
++ if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
++ netif_carrier_on(dev);
+
-+#define FE_PDMA_SIZE_4DWORDS (0 << 4)
-+#define FE_PDMA_SIZE_8DWORDS (1 << 4)
-+#define FE_PDMA_SIZE_16DWORDS (2 << 4)
++ netif_start_queue(dev);
++ fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
+
-+#define FE_US_CYC_CNT_MASK 0xff
-+#define FE_US_CYC_CNT_SHIFT 0x8
-+#define FE_US_CYC_CNT_DIVISOR 1000000
++ return 0;
++}
+
-+#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
-+#define RX_DMA_LSO BIT(30)
-+#define RX_DMA_DONE BIT(31)
-+#define RX_DMA_L4VALID BIT(30)
++static int fe_stop(struct net_device *dev)
++{
++ struct fe_priv *priv = netdev_priv(dev);
++ unsigned long flags;
+
-+struct fe_rx_dma {
-+ unsigned int rxd1;
-+ unsigned int rxd2;
-+ unsigned int rxd3;
-+ unsigned int rxd4;
-+} __packed __aligned(4);
++ fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
+
-+#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
-+#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
-+#define TX_DMA_PLEN1(_x) ((_x) & 0x3fff)
-+#define TX_DMA_LS1 BIT(14)
-+#define TX_DMA_LSO BIT(30)
-+#define TX_DMA_DONE BIT(31)
-+#define TX_DMA_QN(_x) ((_x) << 16)
-+#define TX_DMA_PN(_x) ((_x) << 24)
-+#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
-+#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
-+#define TX_DMA_CHKSUM (0x7 << 29)
++ netif_stop_queue(dev);
+
-+struct fe_tx_dma {
-+ unsigned int txd1;
-+ unsigned int txd2;
-+ unsigned int txd3;
-+ unsigned int txd4;
-+} __packed __aligned(4);
++ if (priv->phy)
++ priv->phy->stop(priv);
+
-+struct fe_priv;
++ spin_lock_irqsave(&priv->page_lock, flags);
++ napi_disable(&priv->rx_napi);
+
-+struct fe_phy {
-+ struct phy_device *phy[8];
-+ struct device_node *phy_node[8];
-+ const __be32 *phy_fixed[8];
-+ int duplex[8];
-+ int speed[8];
-+ int tx_fc[8];
-+ int rx_fc[8];
-+ spinlock_t lock;
++ fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
++ ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
++ FE_REG_PDMA_GLO_CFG);
++ spin_unlock_irqrestore(&priv->page_lock, flags);
+
-+ int (*connect)(struct fe_priv *priv);
-+ void (*disconnect)(struct fe_priv *priv);
-+ void (*start)(struct fe_priv *priv);
-+ void (*stop)(struct fe_priv *priv);
-+};
++ return 0;
++}
+
-+struct fe_soc_data
++static int __init fe_init(struct net_device *dev)
+{
-+ unsigned char mac[6];
-+ const u32 *reg_table;
++ struct fe_priv *priv = netdev_priv(dev);
++ struct device_node *port;
++ int err;
+
-+ void (*init_data)(struct fe_soc_data *data);
-+ void (*reset_fe)(void);
-+ void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
-+ void (*fwd_config)(struct fe_priv *priv);
-+ void (*tx_dma)(struct fe_priv *priv, int idx, struct sk_buff *skb);
-+ void (*rx_dma)(struct fe_priv *priv, int idx, int len);
-+ int (*switch_init)(struct fe_priv *priv);
-+ int (*switch_config)(struct fe_priv *priv);
-+ void (*port_init)(struct fe_priv *priv, struct device_node *port);
-+ int (*has_carrier)(struct fe_priv *priv);
-+ int (*mdio_init)(struct fe_priv *priv);
-+ void (*mdio_cleanup)(struct fe_priv *priv);
-+ int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
-+ int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
-+ void (*mdio_adjust_link)(struct fe_priv *priv, int port);
-+ int (*get_skb_header)(struct sk_buff *skb, void **iphdr, void **tcph, u64 *hdr_flags, void *priv);
++ BUG_ON(!priv->soc->reset_fe);
++ priv->soc->reset_fe();
+
-+ void *swpriv;
-+ u32 pdma_glo_cfg;
-+ u32 rx_dly_int;
-+ u32 tx_dly_int;
-+ u32 checksum_bit;
-+ u32 tso;
++ if (priv->soc->switch_init)
++ priv->soc->switch_init(priv);
++
++ net_srandom(jiffies);
++ memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
++ of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
++
++ err = fe_mdio_init(priv);
++ if (err)
++ return err;
++
++ if (priv->phy) {
++ err = priv->phy->connect(priv);
++ if (err)
++ goto err_mdio_cleanup;
++ }
++
++ if (priv->soc->port_init)
++ for_each_child_of_node(priv->device->of_node, port)
++ if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
++ priv->soc->port_init(priv, port);
++
++ err = fe_hw_init(dev);
++ if (err)
++ goto err_phy_disconnect;
++
++ if (priv->soc->switch_config)
++ priv->soc->switch_config(priv);
++
++ return 0;
++
++err_phy_disconnect:
++ if (priv->phy)
++ priv->phy->disconnect(priv);
++err_mdio_cleanup:
++ fe_mdio_cleanup(priv);
+
-+ int min_pkt_len;
-+};
++ return err;
++}
+
-+struct fe_priv
++static void fe_uninit(struct net_device *dev)
+{
-+ spinlock_t page_lock;
-+
-+ struct fe_soc_data *soc;
-+ struct net_device *netdev;
-+ struct device *device;
-+ unsigned long sysclk;
++ struct fe_priv *priv = netdev_priv(dev);
+
-+ struct fe_rx_dma *rx_dma;
-+ struct napi_struct rx_napi;
-+ struct sk_buff *rx_skb[NUM_DMA_DESC];
-+ dma_addr_t rx_phys;
++ tasklet_kill(&priv->tx_tasklet);
+
-+ struct fe_tx_dma *tx_dma;
-+ struct tasklet_struct tx_tasklet;
-+ struct sk_buff *tx_skb[NUM_DMA_DESC];
-+ dma_addr_t tx_phys;
-+ unsigned int tx_free_idx;
++ if (priv->phy)
++ priv->phy->disconnect(priv);
++ fe_mdio_cleanup(priv);
+
-+ struct fe_phy *phy;
-+ struct mii_bus *mii_bus;
-+ int mii_irq[PHY_MAX_ADDR];
++ fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
++ free_irq(dev->irq, dev);
+
-+ int link[8];
++ fe_free_dma(priv);
++}
+
-+ struct net_lro_mgr lro_mgr;
-+ struct net_lro_desc lro_arr[8];
++static const struct net_device_ops fe_netdev_ops = {
++ .ndo_init = fe_init,
++ .ndo_uninit = fe_uninit,
++ .ndo_open = fe_open,
++ .ndo_stop = fe_stop,
++ .ndo_start_xmit = fe_start_xmit,
++ .ndo_tx_timeout = fe_tx_timeout,
++ .ndo_set_mac_address = fe_set_mac_address,
++ .ndo_change_mtu = eth_change_mtu,
++ .ndo_validate_addr = eth_validate_addr,
+};
+
-+extern const struct of_device_id of_fe_match[];
++static int fe_probe(struct platform_device *pdev)
++{
++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ const struct of_device_id *match;
++ struct fe_soc_data *soc = NULL;
++ struct net_device *netdev;
++ struct fe_priv *priv;
++ struct clk *sysclk;
++ int err;
+
-+void fe_w32(u32 val, unsigned reg);
-+u32 fe_r32(unsigned reg);
++ device_reset(&pdev->dev);
+
-+#endif /* FE_ETH_H */
---- /dev/null
-+++ b/drivers/net/ethernet/ralink/soc_mt7620.c
-@@ -0,0 +1,172 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
-+ */
++ match = of_match_device(of_fe_match, &pdev->dev);
++ soc = (struct fe_soc_data *) match->data;
+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/if_vlan.h>
++ if (soc->init_data)
++ soc->init_data(soc);
++ if (soc->reg_table)
++ fe_reg_table = soc->reg_table;
+
-+#include <asm/mach-ralink/ralink_regs.h>
++ fe_base = devm_request_and_ioremap(&pdev->dev, res);
++ if (!fe_base)
++ return -ENOMEM;
+
-+#include <mt7620.h>
-+#include "ralink_soc_eth.h"
-+#include "gsw_mt7620a.h"
++ netdev = alloc_etherdev(sizeof(struct fe_priv));
++ if (!netdev) {
++ dev_err(&pdev->dev, "alloc_etherdev failed\n");
++ return -ENOMEM;
++ }
+
-+#define MT7620A_CDMA_CSG_CFG 0x400
-+#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
-+#define MT7620A_DMA_2B_OFFSET BIT(31)
-+#define MT7620A_RESET_FE BIT(21)
-+#define MT7620A_RESET_ESW BIT(23)
-+#define MT7620_L4_VALID BIT(23)
++ strcpy(netdev->name, "eth%d");
++ netdev->netdev_ops = &fe_netdev_ops;
++ netdev->base_addr = (unsigned long) fe_base;
++ netdev->watchdog_timeo = TX_TIMEOUT;
++ netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
+
-+#define SYSC_REG_RESET_CTRL 0x34
-+#define MAX_RX_LENGTH 1536
++ if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
++ netdev->features |= NETIF_F_HW_VLAN_CTAG_TX;
+
-+#define CDMA_ICS_EN BIT(2)
-+#define CDMA_UCS_EN BIT(1)
-+#define CDMA_TCS_EN BIT(0)
++ if (soc->tso) {
++ dev_info(&pdev->dev, "Enabling TSO\n");
++ netdev->features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
++ }
++ netdev->hw_features = netdev->features;
+
-+#define GDMA_ICS_EN BIT(22)
-+#define GDMA_TCS_EN BIT(21)
-+#define GDMA_UCS_EN BIT(20)
++ netdev->irq = platform_get_irq(pdev, 0);
++ if (netdev->irq < 0) {
++ dev_err(&pdev->dev, "no IRQ resource found\n");
++ kfree(netdev);
++ return -ENXIO;
++ }
+
-+static const u32 rt5350_reg_table[FE_REG_COUNT] = {
-+ [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
-+ [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
-+ [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
-+ [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
-+ [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
-+ [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
-+ [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
-+ [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
-+ [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
-+ [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
-+ [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
-+ [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
-+};
++ priv = netdev_priv(netdev);
++ memset(priv, 0, sizeof(struct fe_priv));
++ spin_lock_init(&priv->page_lock);
+
-+static void mt7620_fe_reset(void)
-+{
-+ rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
-+ rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
-+}
++ sysclk = devm_clk_get(&pdev->dev, NULL);
++ if (!IS_ERR(sysclk))
++ priv->sysclk = clk_get_rate(sysclk);
+
-+static void mt7620_fwd_config(struct fe_priv *priv)
-+{
-+ int i;
++ priv->netdev = netdev;
++ priv->device = &pdev->dev;
++ priv->soc = soc;
+
-+ /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
-+ for (i = 0; i < 16; i += 2)
-+ fe_w32(((i + 1) << 16) + i, MT7620_DMA_VID + (i * 2));
++ err = register_netdev(netdev);
++ if (err) {
++ dev_err(&pdev->dev, "error bringing up device\n");
++ kfree(netdev);
++ return err;
++ }
++ netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
+
-+ fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
-+ fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG);
-+ fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG);
++#ifdef CONFIG_INET_LRO
++ if (priv->soc->get_skb_header) {
++ priv->lro_mgr.dev = netdev;
++ memset(&priv->lro_mgr.stats, 0, sizeof(priv->lro_mgr.stats));
++ priv->lro_mgr.features = LRO_F_NAPI;
++ priv->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
++ priv->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
++ priv->lro_mgr.max_desc = ARRAY_SIZE(priv->lro_arr);
++ priv->lro_mgr.max_aggr = 64;
++ priv->lro_mgr.frag_align_pad = 0;
++ priv->lro_mgr.lro_arr = priv->lro_arr;
++ priv->lro_mgr.get_skb_header = priv->soc->get_skb_header;
++ }
++#endif
++
++ platform_set_drvdata(pdev, netdev);
++
++ netdev_info(netdev, "done loading\n");
++
++ return 0;
+}
+
-+static void mt7620_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
++static int fe_remove(struct platform_device *pdev)
+{
-+ unsigned int nr_frags = 0;
-+ unsigned int len = 0;
++ struct net_device *dev = platform_get_drvdata(pdev);
++ struct fe_priv *priv = netdev_priv(dev);
+
-+ if (skb) {
-+ nr_frags = skb_shinfo(skb)->nr_frags;
-+ len = skb->len - skb->data_len;
-+ }
++ netif_stop_queue(dev);
++ netif_napi_del(&priv->rx_napi);
+
-+ if (!skb)
-+ priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE;
-+ else if (!nr_frags)
-+ priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(len);
-+ else
-+ priv->tx_dma[idx].txd2 = TX_DMA_PLEN0(len);
++ unregister_netdev(dev);
++ free_netdev(dev);
+
-+ if(skb && vlan_tx_tag_present(skb))
-+ priv->tx_dma[idx].txd4 = 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF);
-+ else
-+ priv->tx_dma[idx].txd4 = 0;
++ return 0;
+}
+
-+static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
-+{
-+ priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
-+}
++static struct platform_driver fe_driver = {
++ .probe = fe_probe,
++ .remove = fe_remove,
++ .driver = {
++ .name = "ralink_soc_eth",
++ .owner = THIS_MODULE,
++ .of_match_table = of_fe_match,
++ },
++};
+
-+#ifdef CONFIG_INET_LRO
-+static int
-+mt7620_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
-+ u64 *hdr_flags, void *_priv)
++static int __init init_rtfe(void)
+{
-+ struct iphdr *iph = NULL;
-+ int vhdr_len = 0;
-+
-+ /*
-+ * Make sure that this packet is Ethernet II, is not VLAN
-+ * tagged, is IPv4, has a valid IP header, and is TCP.
-+ */
-+ if (skb->protocol == 0x0081)
-+ vhdr_len = VLAN_HLEN;
++ int ret;
+
-+ iph = (struct iphdr *)(skb->data + vhdr_len);
-+ if(iph->protocol != IPPROTO_TCP)
-+ return -1;
++ ret = rtesw_init();
++ if (ret)
++ return ret;
+
-+ *iphdr = iph;
-+ *tcph = skb->data + (iph->ihl << 2) + vhdr_len;
-+ *hdr_flags = LRO_IPV4 | LRO_TCP;
++ ret = platform_driver_register(&fe_driver);
++ if (ret)
++ rtesw_exit();
+
-+ return 0;
++ return ret;
+}
-+#endif
+
-+static void mt7620_init_data(struct fe_soc_data *data)
++static void __exit exit_rtfe(void)
+{
-+ if (mt7620_get_eco() >= 5)
-+ data->tso = 1;
++ platform_driver_unregister(&fe_driver);
++ rtesw_exit();
+}
+
-+static struct fe_soc_data mt7620_data = {
-+ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
-+ .init_data = mt7620_init_data,
-+ .reset_fe = mt7620_fe_reset,
-+ .set_mac = mt7620_set_mac,
-+ .fwd_config = mt7620_fwd_config,
-+ .tx_dma = mt7620_tx_dma,
-+ .rx_dma = mt7620_rx_dma,
-+ .switch_init = mt7620_gsw_probe,
-+ .switch_config = mt7620_gsw_config,
-+ .port_init = mt7620_port_init,
-+ .min_pkt_len = 0,
-+ .reg_table = rt5350_reg_table,
-+ .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
-+ .rx_dly_int = RT5350_RX_DLY_INT,
-+ .tx_dly_int = RT5350_TX_DLY_INT,
-+ .checksum_bit = MT7620_L4_VALID,
-+ .has_carrier = mt7620a_has_carrier,
-+ .mdio_read = mt7620_mdio_read,
-+ .mdio_write = mt7620_mdio_write,
-+ .mdio_adjust_link = mt7620_mdio_link_adjust,
-+#ifdef CONFIG_INET_LRO
-+ .get_skb_header = mt7620_get_skb_header,
-+#endif
-+};
-+
-+const struct of_device_id of_fe_match[] = {
-+ { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
-+ {},
-+};
++module_init(init_rtfe);
++module_exit(exit_rtfe);
+
-+MODULE_DEVICE_TABLE(of, of_fe_match);
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
++MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
--- /dev/null
-+++ b/drivers/net/ethernet/ralink/soc_rt2880.c
-@@ -0,0 +1,51 @@
++++ b/drivers/net/ethernet/ralink/ralink_soc_eth.h
+@@ -0,0 +1,384 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
@@ -4236,162 +4170,379 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
++ * based on Ralink SDK3.3
+ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
+ */
+
-+#include <linux/module.h>
++#ifndef FE_ETH_H
++#define FE_ETH_H
++
++#include <linux/mii.h>
++#include <linux/interrupt.h>
++#include <linux/netdevice.h>
++#include <linux/dma-mapping.h>
++#include <linux/phy.h>
++#include <linux/inet_lro.h>
++
++
++enum fe_reg {
++ FE_REG_PDMA_GLO_CFG = 0,
++ FE_REG_PDMA_RST_CFG,
++ FE_REG_DLY_INT_CFG,
++ FE_REG_TX_BASE_PTR0,
++ FE_REG_TX_MAX_CNT0,
++ FE_REG_TX_CTX_IDX0,
++ FE_REG_RX_BASE_PTR0,
++ FE_REG_RX_MAX_CNT0,
++ FE_REG_RX_CALC_IDX0,
++ FE_REG_FE_INT_ENABLE,
++ FE_REG_FE_INT_STATUS,
++ FE_REG_FE_DMA_VID_BASE,
++ FE_REG_COUNT
++};
++
++#define NUM_DMA_DESC 0x100
++
++#define FE_DELAY_EN_INT 0x80
++#define FE_DELAY_MAX_INT 0x04
++#define FE_DELAY_MAX_TOUT 0x04
++#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
++#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
++#define FE_PSE_FQFC_CFG_INIT 0x80504000
++
++/* interrupt bits */
++#define FE_CNT_PPE_AF BIT(31)
++#define FE_CNT_GDM_AF BIT(29)
++#define FE_PSE_P2_FC BIT(26)
++#define FE_PSE_BUF_DROP BIT(24)
++#define FE_GDM_OTHER_DROP BIT(23)
++#define FE_PSE_P1_FC BIT(22)
++#define FE_PSE_P0_FC BIT(21)
++#define FE_PSE_FQ_EMPTY BIT(20)
++#define FE_GE1_STA_CHG BIT(18)
++#define FE_TX_COHERENT BIT(17)
++#define FE_RX_COHERENT BIT(16)
++#define FE_TX_DONE_INT3 BIT(11)
++#define FE_TX_DONE_INT2 BIT(10)
++#define FE_TX_DONE_INT1 BIT(9)
++#define FE_TX_DONE_INT0 BIT(8)
++#define FE_RX_DONE_INT0 BIT(2)
++#define FE_TX_DLY_INT BIT(1)
++#define FE_RX_DLY_INT BIT(0)
++
++#define RT5350_RX_DLY_INT BIT(30)
++#define RT5350_TX_DLY_INT BIT(28)
++
++/* registers */
++#define FE_FE_OFFSET 0x0000
++#define FE_GDMA_OFFSET 0x0020
++#define FE_PSE_OFFSET 0x0040
++#define FE_GDMA2_OFFSET 0x0060
++#define FE_CDMA_OFFSET 0x0080
++#define FE_DMA_VID0 0x00a8
++#define FE_PDMA_OFFSET 0x0100
++#define FE_PPE_OFFSET 0x0200
++#define FE_CMTABLE_OFFSET 0x0400
++#define FE_POLICYTABLE_OFFSET 0x1000
++
++#define RT5350_PDMA_OFFSET 0x0800
++#define RT5350_SDM_OFFSET 0x0c00
++
++#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
++#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
++#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
++#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
++#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
++#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
++#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
++#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
++
++#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
++#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
++#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
++#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
++#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
++
++#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
++#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
++#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
++#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
++#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
++
++#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
++#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
++#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
++#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
++
++#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
++#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
++
++#define MT7620A_GDMA_OFFSET 0x0600
++#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
++#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
++#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
++#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
++#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
++
++#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
++#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
++#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
++#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
++#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
++#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
++#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
++#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
++#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
++#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
++#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
++#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
++#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
++#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
++#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
++#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
++#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
++#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
++#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
++#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
++#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
++#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
++#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
++#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
++#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
++#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
++#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
++#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
++#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
++#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
++
++#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
++#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
++#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
++#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
++#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
++#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
++#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
++#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
++#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
++#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
++#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
++#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
++#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
++#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
++#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
++#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
++#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
++#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
++#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
++#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
++#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
++#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
++#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
++#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
++#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
++#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
++#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
++#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
++
++#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
++#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
++#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
++#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
++#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
++#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
++#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
++#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
++#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
++#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
++
++#define RT5350_SDM_ICS_EN BIT(16)
++#define RT5350_SDM_TCS_EN BIT(17)
++#define RT5350_SDM_UCS_EN BIT(18)
++
++
++/* MDIO_CFG register bits */
++#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
++#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
++#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
++#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
++#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
++#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
++#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
++#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
++#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
++#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
++#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
++#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
++#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
++#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
++#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
++#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
++#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
++#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
++#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
++#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
++#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
++#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
++#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
++#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
++#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
++
++/* uni-cast port */
++#define FE_GDM1_ICS_EN BIT(22)
++#define FE_GDM1_TCS_EN BIT(21)
++#define FE_GDM1_UCS_EN BIT(20)
++#define FE_GDM1_JMB_EN BIT(19)
++#define FE_GDM1_STRPCRC BIT(16)
++#define FE_GDM1_UFRC_P_CPU (0 << 12)
++#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
++#define FE_GDM1_UFRC_P_PPE (6 << 12)
+
-+#include <asm/mach-ralink/ralink_regs.h>
++/* checksums */
++#define FE_ICS_GEN_EN BIT(2)
++#define FE_UCS_GEN_EN BIT(1)
++#define FE_TCS_GEN_EN BIT(0)
+
-+#include "ralink_soc_eth.h"
-+#include "mdio_rt2880.h"
++/* dma ring */
++#define FE_PST_DRX_IDX0 BIT(16)
++#define FE_PST_DTX_IDX3 BIT(3)
++#define FE_PST_DTX_IDX2 BIT(2)
++#define FE_PST_DTX_IDX1 BIT(1)
++#define FE_PST_DTX_IDX0 BIT(0)
+
-+#define SYSC_REG_RESET_CTRL 0x034
-+#define RT2880_RESET_FE BIT(18)
++#define FE_TX_WB_DDONE BIT(6)
++#define FE_RX_DMA_BUSY BIT(3)
++#define FE_TX_DMA_BUSY BIT(1)
++#define FE_RX_DMA_EN BIT(2)
++#define FE_TX_DMA_EN BIT(0)
+
-+void rt2880_fe_reset(void)
-+{
-+ rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
-+}
++#define FE_PDMA_SIZE_4DWORDS (0 << 4)
++#define FE_PDMA_SIZE_8DWORDS (1 << 4)
++#define FE_PDMA_SIZE_16DWORDS (2 << 4)
+
-+struct fe_soc_data rt2880_data = {
-+ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
-+ .reset_fe = rt2880_fe_reset,
-+ .min_pkt_len = 64,
-+ .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
-+ .checksum_bit = RX_DMA_L4VALID,
-+ .rx_dly_int = FE_RX_DLY_INT,
-+ .tx_dly_int = FE_TX_DLY_INT,
-+ .mdio_read = rt2880_mdio_read,
-+ .mdio_write = rt2880_mdio_write,
-+ .mdio_adjust_link = rt2880_mdio_link_adjust,
-+};
++#define FE_US_CYC_CNT_MASK 0xff
++#define FE_US_CYC_CNT_SHIFT 0x8
++#define FE_US_CYC_CNT_DIVISOR 1000000
+
-+const struct of_device_id of_fe_match[] = {
-+ { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
-+ {},
-+};
++#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
++#define RX_DMA_LSO BIT(30)
++#define RX_DMA_DONE BIT(31)
++#define RX_DMA_L4VALID BIT(30)
+
-+MODULE_DEVICE_TABLE(of, of_fe_match);
---- /dev/null
-+++ b/drivers/net/ethernet/ralink/soc_rt305x.c
-@@ -0,0 +1,113 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
-+ */
++struct fe_rx_dma {
++ unsigned int rxd1;
++ unsigned int rxd2;
++ unsigned int rxd3;
++ unsigned int rxd4;
++} __packed __aligned(4);
+
-+#include <linux/module.h>
++#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
++#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
++#define TX_DMA_PLEN1(_x) ((_x) & 0x3fff)
++#define TX_DMA_LS1 BIT(14)
++#define TX_DMA_LSO BIT(30)
++#define TX_DMA_DONE BIT(31)
++#define TX_DMA_QN(_x) ((_x) << 16)
++#define TX_DMA_PN(_x) ((_x) << 24)
++#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
++#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
++#define TX_DMA_CHKSUM (0x7 << 29)
+
-+#include <asm/mach-ralink/ralink_regs.h>
++struct fe_tx_dma {
++ unsigned int txd1;
++ unsigned int txd2;
++ unsigned int txd3;
++ unsigned int txd4;
++} __packed __aligned(4);
+
-+#include "ralink_soc_eth.h"
++struct fe_priv;
+
-+#define RT305X_RESET_FE BIT(21)
-+#define RT305X_RESET_ESW BIT(23)
-+#define SYSC_REG_RESET_CTRL 0x034
++struct fe_phy {
++ struct phy_device *phy[8];
++ struct device_node *phy_node[8];
++ const __be32 *phy_fixed[8];
++ int duplex[8];
++ int speed[8];
++ int tx_fc[8];
++ int rx_fc[8];
++ spinlock_t lock;
+
-+static const u32 rt5350_reg_table[FE_REG_COUNT] = {
-+ [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
-+ [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
-+ [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
-+ [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
-+ [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
-+ [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
-+ [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
-+ [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
-+ [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
-+ [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
-+ [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
-+ [FE_REG_FE_DMA_VID_BASE] = 0,
++ int (*connect)(struct fe_priv *priv);
++ void (*disconnect)(struct fe_priv *priv);
++ void (*start)(struct fe_priv *priv);
++ void (*stop)(struct fe_priv *priv);
+};
+
-+static void rt305x_fe_reset(void)
++struct fe_soc_data
+{
-+ rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
-+ rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
-+}
++ unsigned char mac[6];
++ const u32 *reg_table;
+
-+static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
-+{
-+ unsigned long flags;
++ void (*init_data)(struct fe_soc_data *data);
++ void (*reset_fe)(void);
++ void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
++ void (*fwd_config)(struct fe_priv *priv);
++ void (*tx_dma)(struct fe_priv *priv, int idx, struct sk_buff *skb);
++ void (*rx_dma)(struct fe_priv *priv, int idx, int len);
++ int (*switch_init)(struct fe_priv *priv);
++ int (*switch_config)(struct fe_priv *priv);
++ void (*port_init)(struct fe_priv *priv, struct device_node *port);
++ int (*has_carrier)(struct fe_priv *priv);
++ int (*mdio_init)(struct fe_priv *priv);
++ void (*mdio_cleanup)(struct fe_priv *priv);
++ int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
++ int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
++ void (*mdio_adjust_link)(struct fe_priv *priv, int port);
++ int (*get_skb_header)(struct sk_buff *skb, void **iphdr, void **tcph, u64 *hdr_flags, void *priv);
+
-+ spin_lock_irqsave(&priv->page_lock, flags);
-+ fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
-+ fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
-+ RT5350_SDM_MAC_ADRL);
-+ spin_unlock_irqrestore(&priv->page_lock, flags);
-+}
++ void *swpriv;
++ u32 pdma_glo_cfg;
++ u32 rx_dly_int;
++ u32 tx_dly_int;
++ u32 checksum_bit;
++ u32 tso;
+
-+static void rt5350_fwd_config(struct fe_priv *priv)
-+{
-+ unsigned long sysclk = priv->sysclk;
++ int min_pkt_len;
++};
+
-+ if (sysclk) {
-+ sysclk /= FE_US_CYC_CNT_DIVISOR;
-+ sysclk <<= FE_US_CYC_CNT_SHIFT;
++struct fe_priv
++{
++ spinlock_t page_lock;
+
-+ fe_w32((fe_r32(FE_FE_GLO_CFG) &
-+ ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
-+ FE_FE_GLO_CFG);
-+ }
++ struct fe_soc_data *soc;
++ struct net_device *netdev;
++ struct device *device;
++ unsigned long sysclk;
+
-+ fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG);
-+ fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN,
-+ RT5350_SDM_CFG);
-+}
++ struct fe_rx_dma *rx_dma;
++ struct napi_struct rx_napi;
++ struct sk_buff *rx_skb[NUM_DMA_DESC];
++ dma_addr_t rx_phys;
+
-+static void rt5350_fe_reset(void)
-+{
-+ rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
-+ rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
-+}
++ struct fe_tx_dma *tx_dma;
++ struct tasklet_struct tx_tasklet;
++ struct sk_buff *tx_skb[NUM_DMA_DESC];
++ dma_addr_t tx_phys;
++ unsigned int tx_free_idx;
+
-+static struct fe_soc_data rt3050_data = {
-+ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
-+ .reset_fe = rt305x_fe_reset,
-+ .min_pkt_len = 64,
-+ .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
-+ .checksum_bit = RX_DMA_L4VALID,
-+ .rx_dly_int = FE_RX_DLY_INT,
-+ .tx_dly_int = FE_TX_DLY_INT,
-+};
++ struct fe_phy *phy;
++ struct mii_bus *mii_bus;
++ int mii_irq[PHY_MAX_ADDR];
+
-+static struct fe_soc_data rt5350_data = {
-+ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
-+ .reg_table = rt5350_reg_table,
-+ .reset_fe = rt5350_fe_reset,
-+ .set_mac = rt5350_set_mac,
-+ .fwd_config = rt5350_fwd_config,
-+ .min_pkt_len = 64,
-+ .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
-+ .checksum_bit = RX_DMA_L4VALID,
-+ .rx_dly_int = RT5350_RX_DLY_INT,
-+ .tx_dly_int = RT5350_TX_DLY_INT,
-+};
++ int link[8];
+
-+const struct of_device_id of_fe_match[] = {
-+ { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
-+ { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
-+ {},
++ struct net_lro_mgr lro_mgr;
++ struct net_lro_desc lro_arr[8];
+};
+
-+MODULE_DEVICE_TABLE(of, of_fe_match);
++extern const struct of_device_id of_fe_match[];
++
++void fe_w32(u32 val, unsigned reg);
++u32 fe_r32(unsigned reg);
++
++#endif /* FE_ETH_H */
--- /dev/null
-+++ b/drivers/net/ethernet/ralink/soc_rt3883.c
-@@ -0,0 +1,60 @@
++++ b/drivers/net/ethernet/ralink/soc_mt7620.c
+@@ -0,0 +1,172 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
@@ -4410,538 +4561,390 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/if_vlan.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
++#include <mt7620.h>
+#include "ralink_soc_eth.h"
-+#include "mdio_rt2880.h"
-+
-+#define RT3883_SYSC_REG_RSTCTRL 0x34
-+#define RT3883_RSTCTRL_FE BIT(21)
-+
-+static void rt3883_fe_reset(void)
-+{
-+ u32 t;
-+
-+ t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
-+ t |= RT3883_RSTCTRL_FE;
-+ rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
-+
-+ t &= ~RT3883_RSTCTRL_FE;
-+ rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
-+}
-+
-+static struct fe_soc_data rt3883_data = {
-+ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
-+ .reset_fe = rt3883_fe_reset,
-+ .min_pkt_len = 64,
-+ .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
-+ .rx_dly_int = FE_RX_DLY_INT,
-+ .tx_dly_int = FE_TX_DLY_INT,
-+ .checksum_bit = RX_DMA_L4VALID,
-+ .mdio_read = rt2880_mdio_read,
-+ .mdio_write = rt2880_mdio_write,
-+ .mdio_adjust_link = rt2880_mdio_link_adjust,
-+ .port_init = rt2880_port_init,
-+};
-+
-+const struct of_device_id of_fe_match[] = {
-+ { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
-+ {},
-+};
-+
-+MODULE_DEVICE_TABLE(of, of_fe_match);
-+
---- /dev/null
-+++ b/drivers/net/ethernet/ralink/mt7530.c
-@@ -0,0 +1,467 @@
-+/*
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/if.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/list.h>
-+#include <linux/if_ether.h>
-+#include <linux/skbuff.h>
-+#include <linux/netdevice.h>
-+#include <linux/netlink.h>
-+#include <linux/bitops.h>
-+#include <net/genetlink.h>
-+#include <linux/switch.h>
-+#include <linux/delay.h>
-+#include <linux/phy.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/lockdep.h>
-+#include <linux/workqueue.h>
-+#include <linux/of_device.h>
-+
-+#include "mt7530.h"
-+
-+#define MT7530_CPU_PORT 6
-+#define MT7530_NUM_PORTS 7
-+#define MT7530_NUM_VLANS 16
-+#define MT7530_NUM_VIDS 16
-+
-+#define REG_ESW_VLAN_VTCR 0x90
-+#define REG_ESW_VLAN_VAWD1 0x94
-+#define REG_ESW_VLAN_VAWD2 0x98
-+
-+enum {
-+ /* Global attributes. */
-+ MT7530_ATTR_ENABLE_VLAN,
-+};
++#include "gsw_mt7620a.h"
+
-+struct mt7530_port {
-+ u16 pvid;
-+};
++#define MT7620A_CDMA_CSG_CFG 0x400
++#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
++#define MT7620A_DMA_2B_OFFSET BIT(31)
++#define MT7620A_RESET_FE BIT(21)
++#define MT7620A_RESET_ESW BIT(23)
++#define MT7620_L4_VALID BIT(23)
+
-+struct mt7530_vlan {
-+ u8 ports;
-+};
++#define SYSC_REG_RESET_CTRL 0x34
++#define MAX_RX_LENGTH 1536
+
-+struct mt7530_priv {
-+ void __iomem *base;
-+ struct mii_bus *bus;
-+ struct switch_dev swdev;
++#define CDMA_ICS_EN BIT(2)
++#define CDMA_UCS_EN BIT(1)
++#define CDMA_TCS_EN BIT(0)
+
-+ bool global_vlan_enable;
-+ struct mt7530_vlan vlans[MT7530_NUM_VLANS];
-+ struct mt7530_port ports[MT7530_NUM_PORTS];
-+};
++#define GDMA_ICS_EN BIT(22)
++#define GDMA_TCS_EN BIT(21)
++#define GDMA_UCS_EN BIT(20)
+
-+struct mt7530_mapping {
-+ char *name;
-+ u8 pvids[6];
-+ u8 vlans[8];
-+} mt7530_defaults[] = {
-+ {
-+ .name = "llllw",
-+ .pvids = { 1, 1, 1, 1, 2, 1 },
-+ .vlans = { 0, 0x6f, 0x50 },
-+ }, {
-+ .name = "wllll",
-+ .pvids = { 2, 1, 1, 1, 1, 1 },
-+ .vlans = { 0, 0x7e, 0x41 },
-+ },
++static const u32 rt5350_reg_table[FE_REG_COUNT] = {
++ [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
++ [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
++ [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
++ [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
++ [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
++ [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
++ [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
++ [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
++ [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
++ [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
++ [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
++ [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
+};
+
-+struct mt7530_mapping*
-+mt7530_find_mapping(struct device_node *np)
-+{
-+ const char *map;
-+ int i;
-+
-+ if (of_property_read_string(np, "ralink,port-map", &map))
-+ return NULL;
-+
-+ for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
-+ if (!strcmp(map, mt7530_defaults[i].name))
-+ return &mt7530_defaults[i];
-+
-+ return NULL;
-+}
-+
-+static void
-+mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
-+{
-+ int i = 0;
-+
-+ mt7530->global_vlan_enable = 1;
-+
-+ for (i = 0; i < 6; i++)
-+ mt7530->ports[i].pvid = map->pvids[i];
-+ for (i = 0; i < 8; i++)
-+ mt7530->vlans[i].ports = map->vlans[i];
-+}
-+
-+static int
-+mt7530_reset_switch(struct switch_dev *dev)
-+{
-+ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
-+
-+ memset(priv->ports, 0, sizeof(priv->ports));
-+ memset(priv->vlans, 0, sizeof(priv->vlans));
-+
-+ return 0;
-+}
-+
-+static int
-+mt7530_get_vlan_enable(struct switch_dev *dev,
-+ const struct switch_attr *attr,
-+ struct switch_val *val)
-+{
-+ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
-+
-+ val->value.i = priv->global_vlan_enable;
-+
-+ return 0;
-+}
-+
-+static int
-+mt7530_set_vlan_enable(struct switch_dev *dev,
-+ const struct switch_attr *attr,
-+ struct switch_val *val)
-+{
-+ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
-+
-+ priv->global_vlan_enable = val->value.i != 0;
-+
-+ return 0;
-+}
-+
-+static u32
-+mt7530_r32(struct mt7530_priv *priv, u32 reg)
-+{
-+ if (priv->bus) {
-+ u16 high, low;
-+
-+ mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
-+ low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
-+ high = mdiobus_read(priv->bus, 0x1f, 0x10);
-+
-+ return (high << 16) | (low & 0xffff);
-+ }
-+
-+ return ioread32(priv->base + reg);
-+}
-+
-+static void
-+mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
++static void mt7620_fe_reset(void)
+{
-+ if (priv->bus) {
-+ mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
-+ mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
-+ mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
-+ return;
-+ }
-+
-+ iowrite32(val, priv->base + reg);
++ rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
++ rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
+}
-+
-+static void
-+mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
++
++static void mt7620_fwd_config(struct fe_priv *priv)
+{
+ int i;
+
-+ mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
-+
-+ for (i = 0; i < 20; i++) {
-+ u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
-+
-+ if ((val & BIT(31)) == 0)
-+ break;
++ /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
++ for (i = 0; i < 16; i += 2)
++ fe_w32(((i + 1) << 16) + i, MT7620_DMA_VID + (i * 2));
+
-+ udelay(1000);
-+ }
-+ if (i == 20)
-+ printk("mt7530: vtcr timeout\n");
++ fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
++ fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG);
++ fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG);
+}
+
-+static int
-+mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
++static void mt7620_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
+{
-+ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
++ unsigned int nr_frags = 0;
++ unsigned int len = 0;
+
-+ if (port >= MT7530_NUM_PORTS)
-+ return -EINVAL;
++ if (skb) {
++ nr_frags = skb_shinfo(skb)->nr_frags;
++ len = skb->len - skb->data_len;
++ }
+
-+ *val = mt7530_r32(priv, 0x2014 + (0x100 * port));
-+ *val &= 0xff;
++ if (!skb)
++ priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE;
++ else if (!nr_frags)
++ priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(len);
++ else
++ priv->tx_dma[idx].txd2 = TX_DMA_PLEN0(len);
+
-+ return 0;
++ if(skb && vlan_tx_tag_present(skb))
++ priv->tx_dma[idx].txd4 = 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF);
++ else
++ priv->tx_dma[idx].txd4 = 0;
+}
+
-+static int
-+mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
++static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
+{
-+ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
-+
-+ if (port >= MT7530_NUM_PORTS)
-+ return -1;
-+
-+ priv->ports[port].pvid = pvid;
-+
-+ return 0;
++ priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
+}
+
++#ifdef CONFIG_INET_LRO
+static int
-+mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
++mt7620_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
++ u64 *hdr_flags, void *_priv)
+{
-+ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
-+ u32 member;
-+ int i;
-+
-+ val->len = 0;
-+
-+ if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VIDS)
-+ return -EINVAL;
++ struct iphdr *iph = NULL;
++ int vhdr_len = 0;
+
-+ mt7530_vtcr(priv, 0, val->port_vlan);
-+ member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
-+ member >>= 16;
-+ member &= 0xff;
++ /*
++ * Make sure that this packet is Ethernet II, is not VLAN
++ * tagged, is IPv4, has a valid IP header, and is TCP.
++ */
++ if (skb->protocol == 0x0081)
++ vhdr_len = VLAN_HLEN;
+
-+ for (i = 0; i < MT7530_NUM_PORTS; i++) {
-+ struct switch_port *p;
-+ if (!(member & BIT(i)))
-+ continue;
++ iph = (struct iphdr *)(skb->data + vhdr_len);
++ if(iph->protocol != IPPROTO_TCP)
++ return -1;
+
-+ p = &val->value.ports[val->len++];
-+ p->id = i;
-+ p->flags = 0;
-+ }
++ *iphdr = iph;
++ *tcph = skb->data + (iph->ihl << 2) + vhdr_len;
++ *hdr_flags = LRO_IPV4 | LRO_TCP;
+
+ return 0;
+}
++#endif
+
-+static int
-+mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
++static void mt7620_init_data(struct fe_soc_data *data)
+{
-+ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
-+ int ports = 0;
-+ int i;
++ if (mt7620_get_eco() >= 5)
++ data->tso = 1;
++}
+
-+ if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VIDS ||
-+ val->len > MT7530_NUM_PORTS)
-+ return -EINVAL;
++static struct fe_soc_data mt7620_data = {
++ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
++ .init_data = mt7620_init_data,
++ .reset_fe = mt7620_fe_reset,
++ .set_mac = mt7620_set_mac,
++ .fwd_config = mt7620_fwd_config,
++ .tx_dma = mt7620_tx_dma,
++ .rx_dma = mt7620_rx_dma,
++ .switch_init = mt7620_gsw_probe,
++ .switch_config = mt7620_gsw_config,
++ .port_init = mt7620_port_init,
++ .min_pkt_len = 0,
++ .reg_table = rt5350_reg_table,
++ .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
++ .rx_dly_int = RT5350_RX_DLY_INT,
++ .tx_dly_int = RT5350_TX_DLY_INT,
++ .checksum_bit = MT7620_L4_VALID,
++ .has_carrier = mt7620a_has_carrier,
++ .mdio_read = mt7620_mdio_read,
++ .mdio_write = mt7620_mdio_write,
++ .mdio_adjust_link = mt7620_mdio_link_adjust,
++#ifdef CONFIG_INET_LRO
++ .get_skb_header = mt7620_get_skb_header,
++#endif
++};
+
-+ for (i = 0; i < val->len; i++) {
-+ struct switch_port *p = &val->value.ports[i];
++const struct of_device_id of_fe_match[] = {
++ { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
++ {},
++};
+
-+ if (p->id >= MT7530_NUM_PORTS)
-+ return -EINVAL;
++MODULE_DEVICE_TABLE(of, of_fe_match);
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/soc_rt2880.c
+@@ -0,0 +1,51 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
+
-+ ports |= BIT(p->id);
-+ }
-+ priv->vlans[val->port_vlan].ports = ports;
++#include <linux/module.h>
+
-+ return 0;
-+}
++#include <asm/mach-ralink/ralink_regs.h>
+
-+static int
-+mt7530_apply_config(struct switch_dev *dev)
-+{
-+ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
-+ int i;
++#include "ralink_soc_eth.h"
++#include "mdio_rt2880.h"
+
-+ if (!priv->global_vlan_enable) {
-+ mt7530_w32(priv, 0x2004, 0xff000);
-+ mt7530_w32(priv, 0x2104, 0xff000);
-+ mt7530_w32(priv, 0x2204, 0xff000);
-+ mt7530_w32(priv, 0x2304, 0xff000);
-+ mt7530_w32(priv, 0x2404, 0xff000);
-+ mt7530_w32(priv, 0x2504, 0xff000);
-+ mt7530_w32(priv, 0x2604, 0xff000);
-+ mt7530_w32(priv, 0x2010, 0x810000c);
-+ mt7530_w32(priv, 0x2110, 0x810000c);
-+ mt7530_w32(priv, 0x2210, 0x810000c);
-+ mt7530_w32(priv, 0x2310, 0x810000c);
-+ mt7530_w32(priv, 0x2410, 0x810000c);
-+ mt7530_w32(priv, 0x2510, 0x810000c);
-+ mt7530_w32(priv, 0x2610, 0x810000c);
-+ return 0;
-+ }
++#define SYSC_REG_RESET_CTRL 0x034
++#define RT2880_RESET_FE BIT(18)
+
-+ // LAN/WAN ports as security mode
-+ mt7530_w32(priv, 0x2004, 0xff0003);
-+ mt7530_w32(priv, 0x2104, 0xff0003);
-+ mt7530_w32(priv, 0x2204, 0xff0003);
-+ mt7530_w32(priv, 0x2304, 0xff0003);
-+ mt7530_w32(priv, 0x2404, 0xff0003);
-+ mt7530_w32(priv, 0x2504, 0xff0003);
-+ // LAN/WAN ports as transparent port
-+ mt7530_w32(priv, 0x2010, 0x810000c0);
-+ mt7530_w32(priv, 0x2110, 0x810000c0);
-+ mt7530_w32(priv, 0x2210, 0x810000c0);
-+ mt7530_w32(priv, 0x2310, 0x810000c0);
-+ mt7530_w32(priv, 0x2410, 0x810000c0);
-+ mt7530_w32(priv, 0x2510, 0x810000c0);
++void rt2880_fe_reset(void)
++{
++ rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
++}
+
-+ // set CPU/P7 port as user port
-+ mt7530_w32(priv, 0x2610, 0x81000000);
-+ mt7530_w32(priv, 0x2710, 0x81000000);
++struct fe_soc_data rt2880_data = {
++ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
++ .reset_fe = rt2880_fe_reset,
++ .min_pkt_len = 64,
++ .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
++ .checksum_bit = RX_DMA_L4VALID,
++ .rx_dly_int = FE_RX_DLY_INT,
++ .tx_dly_int = FE_TX_DLY_INT,
++ .mdio_read = rt2880_mdio_read,
++ .mdio_write = rt2880_mdio_write,
++ .mdio_adjust_link = rt2880_mdio_link_adjust,
++};
+
-+ mt7530_w32(priv, 0x2604, 0x20ff0003);
-+ mt7530_w32(priv, 0x2704, 0x20ff0003);
-+ mt7530_w32(priv, 0x2610, 0x81000000);
++const struct of_device_id of_fe_match[] = {
++ { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
++ {},
++};
+
-+ for (i = 0; i < MT7530_NUM_VLANS; i++) {
-+ u8 ports = priv->vlans[i].ports;
-+ u32 val = mt7530_r32(priv, 0x100 + 4 * (i / 2));
++MODULE_DEVICE_TABLE(of, of_fe_match);
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/soc_rt305x.c
+@@ -0,0 +1,113 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
+
-+ if (i % 2 == 0) {
-+ val &= 0xfff000;
-+ val |= i;
-+ } else {
-+ val &= 0xfff;
-+ val |= (i << 12);
-+ }
-+ mt7530_w32(priv, 0x100 + 4 * (i / 2), val);
++#include <linux/module.h>
+
-+ if (ports)
-+ mt7530_w32(priv, REG_ESW_VLAN_VAWD1, BIT(30) | (ports << 16) | BIT(0));
-+ else
-+ mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
++#include <asm/mach-ralink/ralink_regs.h>
+
-+ mt7530_vtcr(priv, 1, i);
-+ }
++#include "ralink_soc_eth.h"
+
-+ for (i = 0; i < MT7530_NUM_PORTS; i++)
-+ mt7530_w32(priv, 0x2014 + (0x100 * i), 0x10000 | priv->ports[i].pvid);
++#define RT305X_RESET_FE BIT(21)
++#define RT305X_RESET_ESW BIT(23)
++#define SYSC_REG_RESET_CTRL 0x034
+
-+ return 0;
++static const u32 rt5350_reg_table[FE_REG_COUNT] = {
++ [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
++ [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
++ [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
++ [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
++ [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
++ [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
++ [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
++ [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
++ [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
++ [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
++ [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
++ [FE_REG_FE_DMA_VID_BASE] = 0,
++};
++
++static void rt305x_fe_reset(void)
++{
++ rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
++ rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
+}
+
-+static int
-+mt7530_get_port_link(struct switch_dev *dev, int port,
-+ struct switch_port_link *link)
++static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
+{
-+ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
-+ u32 speed, pmsr;
++ unsigned long flags;
+
-+ if (port < 0 || port >= MT7530_NUM_PORTS)
-+ return -EINVAL;
++ spin_lock_irqsave(&priv->page_lock, flags);
++ fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
++ fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
++ RT5350_SDM_MAC_ADRL);
++ spin_unlock_irqrestore(&priv->page_lock, flags);
++}
+
-+ pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
++static void rt5350_fwd_config(struct fe_priv *priv)
++{
++ unsigned long sysclk = priv->sysclk;
+
-+ link->link = pmsr & 1;
-+ link->duplex = (pmsr >> 1) & 1;
-+ speed = (pmsr >> 2) & 3;
++ if (sysclk) {
++ sysclk /= FE_US_CYC_CNT_DIVISOR;
++ sysclk <<= FE_US_CYC_CNT_SHIFT;
+
-+ switch (speed) {
-+ case 0:
-+ link->speed = SWITCH_PORT_SPEED_10;
-+ break;
-+ case 1:
-+ link->speed = SWITCH_PORT_SPEED_100;
-+ break;
-+ case 2:
-+ case 3: /* forced gige speed can be 2 or 3 */
-+ link->speed = SWITCH_PORT_SPEED_1000;
-+ break;
-+ default:
-+ link->speed = SWITCH_PORT_SPEED_UNKNOWN;
-+ break;
++ fe_w32((fe_r32(FE_FE_GLO_CFG) &
++ ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
++ FE_FE_GLO_CFG);
+ }
+
-+ return 0;
++ fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG);
++ fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN,
++ RT5350_SDM_CFG);
+}
+
-+static const struct switch_attr mt7530_global[] = {
-+ {
-+ .type = SWITCH_TYPE_INT,
-+ .name = "enable_vlan",
-+ .description = "VLAN mode (1:enabled)",
-+ .max = 1,
-+ .id = MT7530_ATTR_ENABLE_VLAN,
-+ .get = mt7530_get_vlan_enable,
-+ .set = mt7530_set_vlan_enable,
-+ },
-+};
++static void rt5350_fe_reset(void)
++{
++ rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
++ rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
++}
+
-+static const struct switch_attr mt7530_port[] = {
++static struct fe_soc_data rt3050_data = {
++ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
++ .reset_fe = rt305x_fe_reset,
++ .min_pkt_len = 64,
++ .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
++ .checksum_bit = RX_DMA_L4VALID,
++ .rx_dly_int = FE_RX_DLY_INT,
++ .tx_dly_int = FE_TX_DLY_INT,
+};
+
-+static const struct switch_attr mt7530_vlan[] = {
++static struct fe_soc_data rt5350_data = {
++ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
++ .reg_table = rt5350_reg_table,
++ .reset_fe = rt5350_fe_reset,
++ .set_mac = rt5350_set_mac,
++ .fwd_config = rt5350_fwd_config,
++ .min_pkt_len = 64,
++ .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
++ .checksum_bit = RX_DMA_L4VALID,
++ .rx_dly_int = RT5350_RX_DLY_INT,
++ .tx_dly_int = RT5350_TX_DLY_INT,
+};
+
-+static const struct switch_dev_ops mt7530_ops = {
-+ .attr_global = {
-+ .attr = mt7530_global,
-+ .n_attr = ARRAY_SIZE(mt7530_global),
-+ },
-+ .attr_port = {
-+ .attr = mt7530_port,
-+ .n_attr = ARRAY_SIZE(mt7530_port),
-+ },
-+ .attr_vlan = {
-+ .attr = mt7530_vlan,
-+ .n_attr = ARRAY_SIZE(mt7530_vlan),
-+ },
-+ .get_vlan_ports = mt7530_get_vlan_ports,
-+ .set_vlan_ports = mt7530_set_vlan_ports,
-+ .get_port_pvid = mt7530_get_port_pvid,
-+ .set_port_pvid = mt7530_set_port_pvid,
-+ .get_port_link = mt7530_get_port_link,
-+ .apply_config = mt7530_apply_config,
-+ .reset_switch = mt7530_reset_switch,
++const struct of_device_id of_fe_match[] = {
++ { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
++ { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
++ {},
+};
+
-+int
-+mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus)
-+{
-+ struct switch_dev *swdev;
-+ struct mt7530_priv *mt7530;
-+ struct mt7530_mapping *map;
-+ int ret;
-+
-+ if (bus && bus->phy_map[0x1f]->phy_id != 0x1beef)
-+ return 0;
++MODULE_DEVICE_TABLE(of, of_fe_match);
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/soc_rt3883.c
+@@ -0,0 +1,60 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
+
-+ mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
-+ if (!mt7530)
-+ return -ENOMEM;
++#include <linux/module.h>
+
-+ mt7530->base = base;
-+ mt7530->bus = bus;
-+ mt7530->global_vlan_enable = 1;
++#include <asm/mach-ralink/ralink_regs.h>
+
-+ swdev = &mt7530->swdev;
-+ swdev->name = "mt7530";
-+ swdev->alias = "mt7530";
-+ swdev->cpu_port = MT7530_CPU_PORT;
-+ swdev->ports = MT7530_NUM_PORTS;
-+ swdev->vlans = MT7530_NUM_VLANS;
-+ swdev->ops = &mt7530_ops;
++#include "ralink_soc_eth.h"
++#include "mdio_rt2880.h"
+
-+ ret = register_switch(swdev, NULL);
-+ if (ret) {
-+ dev_err(dev, "failed to register mt7530\n");
-+ return ret;
-+ }
++#define RT3883_SYSC_REG_RSTCTRL 0x34
++#define RT3883_RSTCTRL_FE BIT(21)
+
-+ dev_info(dev, "loaded mt7530 driver\n");
++static void rt3883_fe_reset(void)
++{
++ u32 t;
+
-+ map = mt7530_find_mapping(dev->of_node);
-+ if (map)
-+ mt7530_apply_mapping(mt7530, map);
-+ mt7530_apply_config(swdev);
++ t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
++ t |= RT3883_RSTCTRL_FE;
++ rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
+
-+ return 0;
++ t &= ~RT3883_RSTCTRL_FE;
++ rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
+}
---- /dev/null
-+++ b/drivers/net/ethernet/ralink/mt7530.h
-@@ -0,0 +1,20 @@
-+/*
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
+
-+#ifndef _MT7530_H__
-+#define _MT7530_H__
++static struct fe_soc_data rt3883_data = {
++ .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
++ .reset_fe = rt3883_fe_reset,
++ .min_pkt_len = 64,
++ .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
++ .rx_dly_int = FE_RX_DLY_INT,
++ .tx_dly_int = FE_TX_DLY_INT,
++ .checksum_bit = RX_DMA_L4VALID,
++ .mdio_read = rt2880_mdio_read,
++ .mdio_write = rt2880_mdio_write,
++ .mdio_adjust_link = rt2880_mdio_link_adjust,
++ .port_init = rt2880_port_init,
++};
+
-+int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus);
++const struct of_device_id of_fe_match[] = {
++ { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
++ {},
++};
++
++MODULE_DEVICE_TABLE(of, of_fe_match);
+
-+#endif
diff --git a/target/linux/ramips/patches-3.10/0112-USB-phy-add-ralink-SoC-driver.patch b/target/linux/ramips/patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch
similarity index 98%
rename from target/linux/ramips/patches-3.10/0112-USB-phy-add-ralink-SoC-driver.patch
rename to target/linux/ramips/patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch
index ddfc856687..fbec32cacb 100644
--- a/target/linux/ramips/patches-3.10/0112-USB-phy-add-ralink-SoC-driver.patch
+++ b/target/linux/ramips/patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch
@@ -1,7 +1,7 @@
-From c5f51197b13fd312324ac0486a46e530e163eade Mon Sep 17 00:00:00 2001
+From 71e09658d3544143e46ae76e76da8a322cd73e1d Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 14 Jul 2013 23:31:19 +0200
-Subject: [PATCH 18/33] USB: phy: add ralink SoC driver
+Subject: [PATCH 119/133] USB: phy: add ralink SoC driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---
diff --git a/target/linux/ramips/patches-3.10/0113-USB-add-OHCI-EHCI-OF-binding.patch b/target/linux/ramips/patches-3.10/0120-USB-add-OHCI-EHCI-OF-binding.patch
similarity index 94%
rename from target/linux/ramips/patches-3.10/0113-USB-add-OHCI-EHCI-OF-binding.patch
rename to target/linux/ramips/patches-3.10/0120-USB-add-OHCI-EHCI-OF-binding.patch
index f963139a2a..6d18894b62 100644
--- a/target/linux/ramips/patches-3.10/0113-USB-add-OHCI-EHCI-OF-binding.patch
+++ b/target/linux/ramips/patches-3.10/0120-USB-add-OHCI-EHCI-OF-binding.patch
@@ -1,17 +1,16 @@
-From 40b9d3026ed0b3bcd59f90391195df5b2adabad2 Mon Sep 17 00:00:00 2001
+From 08d438b69f3023f16b044b07eebee6b9c2302f60 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 14 Jul 2013 23:34:53 +0200
-Subject: [PATCH 19/33] USB: add OHCI/EHCI OF binding
+Subject: [PATCH 120/133] USB: add OHCI/EHCI OF binding
based on f3bc64d6d1f21c1b92d75f233a37b75d77af6963
Signed-off-by: John Crispin <blogic@openwrt.org>
---
- arch/mips/ralink/Kconfig | 2 ++
drivers/usb/Makefile | 3 ++-
- drivers/usb/host/ehci-platform.c | 19 +++++++++++++++----
+ drivers/usb/host/ehci-platform.c | 21 +++++++++++++++++----
drivers/usb/host/ohci-platform.c | 37 ++++++++++++++++++++++++++++++++-----
- 4 files changed, 51 insertions(+), 10 deletions(-)
+ 3 files changed, 51 insertions(+), 10 deletions(-)
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
diff --git a/target/linux/ramips/patches-3.10/0202-owrt-USB-adds-dwc_otg.patch b/target/linux/ramips/patches-3.10/0121-USB-adds-dwc_otg.patch
similarity index 99%
rename from target/linux/ramips/patches-3.10/0202-owrt-USB-adds-dwc_otg.patch
rename to target/linux/ramips/patches-3.10/0121-USB-adds-dwc_otg.patch
index 5c17a665fa..8267452c0d 100644
--- a/target/linux/ramips/patches-3.10/0202-owrt-USB-adds-dwc_otg.patch
+++ b/target/linux/ramips/patches-3.10/0121-USB-adds-dwc_otg.patch
@@ -1,7 +1,7 @@
-From 1a44a003bdaf917193114d0d40534496c39644ba Mon Sep 17 00:00:00 2001
+From b74db0e9bae6bbe14e9f725db855621db22e9984 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 15 Mar 2013 20:58:18 +0100
-Subject: [PATCH 202/208] owrt: USB: adds dwc_otg
+Subject: [PATCH 121/133] USB: adds dwc_otg
Signed-off-by: John Crispin <blogic@openwrt.org>
---
diff --git a/target/linux/ramips/patches-3.10/0114-serial-ralink-adds-mt7620-serial.patch b/target/linux/ramips/patches-3.10/0122-serial-ralink-adds-mt7620-serial.patch
similarity index 86%
rename from target/linux/ramips/patches-3.10/0114-serial-ralink-adds-mt7620-serial.patch
rename to target/linux/ramips/patches-3.10/0122-serial-ralink-adds-mt7620-serial.patch
index 2772aef738..f0b2e66b97 100644
--- a/target/linux/ramips/patches-3.10/0114-serial-ralink-adds-mt7620-serial.patch
+++ b/target/linux/ramips/patches-3.10/0122-serial-ralink-adds-mt7620-serial.patch
@@ -1,7 +1,7 @@
-From 629a2ca61e0fbf331f88692038391d22f21b7c70 Mon Sep 17 00:00:00 2001
+From 16f476a7528eefade4bd4ebee12d5aa2052bba8c Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 15 Mar 2013 18:16:01 +0100
-Subject: [PATCH 20/33] serial: ralink: adds mt7620 serial
+Subject: [PATCH 122/133] serial: ralink: adds mt7620 serial
Add the config symbol for Mediatek7620 SoC to SERIAL_8250_RT288X
diff --git a/target/linux/ramips/patches-3.10/0123-serial-ralink-the-core-has-a-size-of-0x100-and-not-0.patch b/target/linux/ramips/patches-3.10/0123-serial-ralink-the-core-has-a-size-of-0x100-and-not-0.patch
new file mode 100644
index 0000000000..b7c9987807
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0123-serial-ralink-the-core-has-a-size-of-0x100-and-not-0.patch
@@ -0,0 +1,22 @@
+From 304c4f060cfa6b44370ad3fe6a16963cac35b10a Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 04:52:01 +0000
+Subject: [PATCH 123/133] serial: ralink: the core has a size of 0x100 and not
+ 0x1000
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/tty/serial/8250/8250_core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/tty/serial/8250/8250_core.c
++++ b/drivers/tty/serial/8250/8250_core.c
+@@ -2499,7 +2499,7 @@ serial8250_pm(struct uart_port *port, un
+ static unsigned int serial8250_port_size(struct uart_8250_port *pt)
+ {
+ if (pt->port.iotype == UPIO_AU)
+- return 0x1000;
++ return 0x100;
+ if (is_omap1_8250(pt))
+ return 0x16 << pt->port.regshift;
+
diff --git a/target/linux/ramips/patches-3.10/0115-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch b/target/linux/ramips/patches-3.10/0124-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch
similarity index 84%
rename from target/linux/ramips/patches-3.10/0115-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch
rename to target/linux/ramips/patches-3.10/0124-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch
index b12817e000..8bd00e93d9 100644
--- a/target/linux/ramips/patches-3.10/0115-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch
+++ b/target/linux/ramips/patches-3.10/0124-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch
@@ -1,7 +1,7 @@
-From 53b934f796611b9a27b698429f1aaec0fe678693 Mon Sep 17 00:00:00 2001
+From 3f70be332048f6a903dc35f73ff5381be3b8f12b Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 14 Jul 2013 23:18:57 +0200
-Subject: [PATCH 21/33] serial: of: allow au1x00 and rt288x to load from OF
+Subject: [PATCH 124/133] serial: of: allow au1x00 and rt288x to load from OF
In order to make serial_8250 loadable via OF on Au1x00 and Ralink WiSoC we need
to default the iotype to UPIO_AU.
diff --git a/target/linux/ramips/patches-3.10/0116-i2c-MIPS-adds-ralink-I2C-driver.patch b/target/linux/ramips/patches-3.10/0125-i2c-MIPS-adds-ralink-I2C-driver.patch
similarity index 98%
rename from target/linux/ramips/patches-3.10/0116-i2c-MIPS-adds-ralink-I2C-driver.patch
rename to target/linux/ramips/patches-3.10/0125-i2c-MIPS-adds-ralink-I2C-driver.patch
index f8f86c00ff..bb5f492bde 100644
--- a/target/linux/ramips/patches-3.10/0116-i2c-MIPS-adds-ralink-I2C-driver.patch
+++ b/target/linux/ramips/patches-3.10/0125-i2c-MIPS-adds-ralink-I2C-driver.patch
@@ -1,7 +1,7 @@
-From 4596818bca07e0928168970839e08875cf51b4cc Mon Sep 17 00:00:00 2001
+From 701cd2fb0513d17f248048b3a6f2c7d1ea294681 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 29 Apr 2013 14:40:43 +0200
-Subject: [PATCH 26/33] i2c: MIPS: adds ralink I2C driver
+Subject: [PATCH 125/133] i2c: MIPS: adds ralink I2C driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---
diff --git a/target/linux/ramips/patches-3.10/0120-spi-introduce-macros-to-set-bits_per_word_mask.patch b/target/linux/ramips/patches-3.10/0126-spi-introduce-macros-to-set-bits_per_word_mask.patch
similarity index 87%
rename from target/linux/ramips/patches-3.10/0120-spi-introduce-macros-to-set-bits_per_word_mask.patch
rename to target/linux/ramips/patches-3.10/0126-spi-introduce-macros-to-set-bits_per_word_mask.patch
index a163d497f8..1dcba05078 100644
--- a/target/linux/ramips/patches-3.10/0120-spi-introduce-macros-to-set-bits_per_word_mask.patch
+++ b/target/linux/ramips/patches-3.10/0126-spi-introduce-macros-to-set-bits_per_word_mask.patch
@@ -1,7 +1,7 @@
-From 2922a8de996956893bb98e4aa91be9774c958336 Mon Sep 17 00:00:00 2001
+From b07600f50efe84d7e3b431e6d10fe774bb00d573 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@wwwdotorg.org>
Date: Tue, 21 May 2013 20:36:34 -0600
-Subject: [PATCH] spi: introduce macros to set bits_per_word_mask
+Subject: [PATCH 126/133] spi: introduce macros to set bits_per_word_mask
Introduce two macros to make setting up spi_master.bits_per_word_mask
easier, and avoid mistakes like writing BIT(n) instead of BIT(n - 1).
diff --git a/target/linux/ramips/patches-3.10/0117-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch b/target/linux/ramips/patches-3.10/0127-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
similarity index 99%
rename from target/linux/ramips/patches-3.10/0117-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
rename to target/linux/ramips/patches-3.10/0127-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
index 4950a701fb..3985718dc6 100644
--- a/target/linux/ramips/patches-3.10/0117-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
+++ b/target/linux/ramips/patches-3.10/0127-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
@@ -1,7 +1,7 @@
-From de1defdad7554d6ba885a6d3dc55105e01e9a07e Mon Sep 17 00:00:00 2001
+From 759e011e67792898799fb54340ba5bad944274a1 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 2 May 2013 14:59:01 +0200
-Subject: [PATCH 27/33] mmc: MIPS: ralink: add sdhci for mt7620a SoC
+Subject: [PATCH 127/133] mmc: MIPS: ralink: add sdhci for mt7620a SoC
Signed-off-by: John Crispin <blogic@openwrt.org>
---
diff --git a/target/linux/ramips/patches-3.10/0118-mtd-fix-cfi-cmdset-0002-erase-status-check.patch b/target/linux/ramips/patches-3.10/0128-mtd-fix-cfi-cmdset-0002-erase-status-check.patch
similarity index 84%
rename from target/linux/ramips/patches-3.10/0118-mtd-fix-cfi-cmdset-0002-erase-status-check.patch
rename to target/linux/ramips/patches-3.10/0128-mtd-fix-cfi-cmdset-0002-erase-status-check.patch
index 709d1d8271..18ba4cc6b2 100644
--- a/target/linux/ramips/patches-3.10/0118-mtd-fix-cfi-cmdset-0002-erase-status-check.patch
+++ b/target/linux/ramips/patches-3.10/0128-mtd-fix-cfi-cmdset-0002-erase-status-check.patch
@@ -1,7 +1,7 @@
-From 413b2ed67d8e4dc1242edb9286ea3f634d10a6ba Mon Sep 17 00:00:00 2001
+From 543f839e6fbeb325e6fa201e205ab18a46e37424 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 15 Jul 2013 00:38:51 +0200
-Subject: [PATCH 32/33] mtd: fix cfi cmdset 0002 erase status check
+Subject: [PATCH 128/133] mtd: fix cfi cmdset 0002 erase status check
---
drivers/mtd/chips/cfi_cmdset_0002.c | 4 ++--
diff --git a/target/linux/ramips/patches-3.10/0119-mtd-cfi-cmdset-0002-force-word-write.patch b/target/linux/ramips/patches-3.10/0129-mtd-cfi-cmdset-0002-force-word-write.patch
similarity index 94%
rename from target/linux/ramips/patches-3.10/0119-mtd-cfi-cmdset-0002-force-word-write.patch
rename to target/linux/ramips/patches-3.10/0129-mtd-cfi-cmdset-0002-force-word-write.patch
index 73edcb470e..28274ee579 100644
--- a/target/linux/ramips/patches-3.10/0119-mtd-cfi-cmdset-0002-force-word-write.patch
+++ b/target/linux/ramips/patches-3.10/0129-mtd-cfi-cmdset-0002-force-word-write.patch
@@ -1,7 +1,7 @@
-From d5b094ea6d435817d295d554d652a97a5014c64f Mon Sep 17 00:00:00 2001
+From 0ffe6cdf77793536a77b5c85cf41deb27cfc7632 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 15 Jul 2013 00:39:21 +0200
-Subject: [PATCH 33/33] mtd: cfi cmdset 0002 force word write
+Subject: [PATCH 129/133] mtd: cfi cmdset 0002 force word write
---
drivers/mtd/chips/cfi_cmdset_0002.c | 9 +++++++--
diff --git a/target/linux/ramips/patches-3.10/0250-nand-7620.patch b/target/linux/ramips/patches-3.10/0130-mtd-ralink-add-mt7620-nand-driver.patch
similarity index 99%
rename from target/linux/ramips/patches-3.10/0250-nand-7620.patch
rename to target/linux/ramips/patches-3.10/0130-mtd-ralink-add-mt7620-nand-driver.patch
index 248e82c29e..45e4632839 100644
--- a/target/linux/ramips/patches-3.10/0250-nand-7620.patch
+++ b/target/linux/ramips/patches-3.10/0130-mtd-ralink-add-mt7620-nand-driver.patch
@@ -1,7 +1,7 @@
-From a5fc495c8dc199ffa997d43331693a5b7ee07270 Mon Sep 17 00:00:00 2001
+From bea6f4b28443b7603e25b2404ad787a97f80fc59 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 17 Nov 2013 17:41:46 +0100
-Subject: [PATCH] ralink: add mt7620 nand driver
+Subject: [PATCH 130/133] mtd: ralink: add mt7620 nand driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---
@@ -9,8 +9,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
drivers/mtd/maps/Makefile | 2 +
drivers/mtd/maps/ralink_nand.c | 2136 ++++++++++++++++++++++++++++++++++++++++
drivers/mtd/maps/ralink_nand.h | 232 +++++
- drivers/mtd/nand/Makefile | 2 +-
- 5 files changed, 2375 insertions(+), 1 deletion(-)
+ 4 files changed, 2374 insertions(+)
create mode 100644 drivers/mtd/maps/ralink_nand.c
create mode 100644 drivers/mtd/maps/ralink_nand.h
diff --git a/target/linux/ramips/patches-3.10/0206-MTD-add-chunked-read-io-to-m25p80.patch b/target/linux/ramips/patches-3.10/0131-mtd-add-chunked-read-io-to-m25p80.patch
similarity index 96%
rename from target/linux/ramips/patches-3.10/0206-MTD-add-chunked-read-io-to-m25p80.patch
rename to target/linux/ramips/patches-3.10/0131-mtd-add-chunked-read-io-to-m25p80.patch
index b4d64ea50c..6a4f8abf35 100644
--- a/target/linux/ramips/patches-3.10/0206-MTD-add-chunked-read-io-to-m25p80.patch
+++ b/target/linux/ramips/patches-3.10/0131-mtd-add-chunked-read-io-to-m25p80.patch
@@ -1,7 +1,7 @@
-From 926ae0ca5017a421709ab0478582683c29988b05 Mon Sep 17 00:00:00 2001
+From f85e6dacdb7d7a9bc37f33cf8770006ab64286f7 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 27 Nov 2013 20:58:16 +0100
-Subject: [PATCH 10/20] MTD: add chunked read io to m25p80
+Subject: [PATCH 131/133] mtd: add chunked read io to m25p80
Signed-off-by: John Crispin <blogic@openwrt.org>
---
diff --git a/target/linux/ramips/patches-3.10/0200-owrt-GPIO-add-gpio_export_with_name.patch b/target/linux/ramips/patches-3.10/0132-GPIO-add-gpio_export_with_name.patch
similarity index 98%
rename from target/linux/ramips/patches-3.10/0200-owrt-GPIO-add-gpio_export_with_name.patch
rename to target/linux/ramips/patches-3.10/0132-GPIO-add-gpio_export_with_name.patch
index 6ba536a893..c6ad7f4788 100644
--- a/target/linux/ramips/patches-3.10/0200-owrt-GPIO-add-gpio_export_with_name.patch
+++ b/target/linux/ramips/patches-3.10/0132-GPIO-add-gpio_export_with_name.patch
@@ -1,7 +1,7 @@
-From 8f3ed1fffa35d18c2b20ebb866c71a22cc0589ff Mon Sep 17 00:00:00 2001
+From def7e226d3e5c501180bdc2fc644ff924b5a275e Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 23 Jun 2013 00:16:22 +0200
-Subject: [PATCH 29/33] owrt: GPIO: add gpio_export_with_name
+Subject: [PATCH 132/133] GPIO: add gpio_export_with_name
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-November/133856.html
diff --git a/target/linux/ramips/patches-3.10/0205-uvc-add-iPassion-iP2970-support.patch b/target/linux/ramips/patches-3.10/0133-uvc-add-iPassion-iP2970-support.patch
similarity index 93%
rename from target/linux/ramips/patches-3.10/0205-uvc-add-iPassion-iP2970-support.patch
rename to target/linux/ramips/patches-3.10/0133-uvc-add-iPassion-iP2970-support.patch
index 5e3484e9e1..099671adf9 100644
--- a/target/linux/ramips/patches-3.10/0205-uvc-add-iPassion-iP2970-support.patch
+++ b/target/linux/ramips/patches-3.10/0133-uvc-add-iPassion-iP2970-support.patch
@@ -1,16 +1,15 @@
-From be8d5b55f93b8ccb3a6b5cfb1e858a59aeca2d6c Mon Sep 17 00:00:00 2001
+From 935815cd3b9690b86e70a18fb755f70becb57cc6 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 19 Sep 2013 01:50:59 +0200
-Subject: [PATCH] uvc: add iPassion iP2970 support
+Subject: [PATCH 133/133] uvc: add iPassion iP2970 support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
- drivers/media/usb/uvc/uvc_driver.c | 12 +++++++++
- drivers/media/usb/uvc/uvc_status.c | 2 ++
- drivers/media/usb/uvc/uvc_v4l2.c | 1 +
- drivers/media/usb/uvc/uvc_video.c | 50 +++++++++++++++++++++++++++++++-----
- drivers/media/usb/uvc/uvcvideo.h | 3 +++
- 5 files changed, 61 insertions(+), 7 deletions(-)
+ drivers/media/usb/uvc/uvc_driver.c | 14 ++++
+ drivers/media/usb/uvc/uvc_status.c | 2 +
+ drivers/media/usb/uvc/uvc_video.c | 147 ++++++++++++++++++++++++++++++++++++
+ drivers/media/usb/uvc/uvcvideo.h | 3 +
+ 4 files changed, 166 insertions(+)
--- a/drivers/media/usb/uvc/uvc_driver.c
+++ b/drivers/media/usb/uvc/uvc_driver.c
diff --git a/target/linux/ramips/patches-3.10/0204-owrt-mtd-split-remove-padding.patch b/target/linux/ramips/patches-3.10/0134-mtd-split-remove-padding.patch
similarity index 100%
rename from target/linux/ramips/patches-3.10/0204-owrt-mtd-split-remove-padding.patch
rename to target/linux/ramips/patches-3.10/0134-mtd-split-remove-padding.patch
diff --git a/target/linux/ramips/patches-3.10/0200-MIPS-Fix-TLBR-use-hazards-for-R2-cores-in-the-TLB-re.patch b/target/linux/ramips/patches-3.10/0200-MIPS-Fix-TLBR-use-hazards-for-R2-cores-in-the-TLB-re.patch
new file mode 100644
index 0000000000..e358e622b2
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0200-MIPS-Fix-TLBR-use-hazards-for-R2-cores-in-the-TLB-re.patch
@@ -0,0 +1,60 @@
+From f281fdccbb3e762d293e6eef7f291a33b84e0f6a Mon Sep 17 00:00:00 2001
+From: Ralf Baechle <ralf@linux-mips.org>
+Date: Thu, 20 Jun 2013 14:56:17 +0200
+Subject: [PATCH 200/215] MIPS: Fix TLBR-use hazards for R2 cores in the TLB
+ reload handlers
+
+MIPS R2 documents state that an execution hazard barrier is needed
+after a TLBR before reading EntryLo.
+
+Original patch by Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>.
+
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+Patchwork: https://patchwork.linux-mips.org/patch/5526/
+(cherry picked from commit 73acc7df534ff458a81435178dab3ea037ed6d78)
+---
+ arch/mips/mm/tlbex.c | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -1935,6 +1935,19 @@ static void __cpuinit build_r4000_tlb_lo
+ uasm_i_nop(&p);
+
+ uasm_i_tlbr(&p);
++
++ switch (current_cpu_type()) {
++ default:
++ if (cpu_has_mips_r2) {
++ uasm_i_ehb(&p);
++
++ case CPU_CAVIUM_OCTEON:
++ case CPU_CAVIUM_OCTEON_PLUS:
++ case CPU_CAVIUM_OCTEON2:
++ break;
++ }
++ }
++
+ /* Examine entrylo 0 or 1 based on ptr. */
+ if (use_bbit_insns()) {
+ uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
+@@ -1989,6 +2002,19 @@ static void __cpuinit build_r4000_tlb_lo
+ uasm_i_nop(&p);
+
+ uasm_i_tlbr(&p);
++
++ switch (current_cpu_type()) {
++ default:
++ if (cpu_has_mips_r2) {
++ uasm_i_ehb(&p);
++
++ case CPU_CAVIUM_OCTEON:
++ case CPU_CAVIUM_OCTEON_PLUS:
++ case CPU_CAVIUM_OCTEON2:
++ break;
++ }
++ }
++
+ /* Examine entrylo 0 or 1 based on ptr. */
+ if (use_bbit_insns()) {
+ uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
diff --git a/target/linux/ramips/patches-3.10/0508-MIPS-GIC-Fix-gic_set_affinity-infinite-loop.patch b/target/linux/ramips/patches-3.10/0201-MIPS-GIC-Fix-gic_set_affinity-infinite-loop.patch
similarity index 91%
rename from target/linux/ramips/patches-3.10/0508-MIPS-GIC-Fix-gic_set_affinity-infinite-loop.patch
rename to target/linux/ramips/patches-3.10/0201-MIPS-GIC-Fix-gic_set_affinity-infinite-loop.patch
index c089e5aa7f..f1898ba073 100644
--- a/target/linux/ramips/patches-3.10/0508-MIPS-GIC-Fix-gic_set_affinity-infinite-loop.patch
+++ b/target/linux/ramips/patches-3.10/0201-MIPS-GIC-Fix-gic_set_affinity-infinite-loop.patch
@@ -1,7 +1,7 @@
-From 553ddf4f3f20c28ab03f87ac8c3cde5edf714675 Mon Sep 17 00:00:00 2001
+From cde59bef2f155fc38413e470ff0e4672623cdbec Mon Sep 17 00:00:00 2001
From: Tony Wu <tung7970@gmail.com>
Date: Fri, 21 Jun 2013 10:13:08 +0000
-Subject: [PATCH 022/105] MIPS: GIC: Fix gic_set_affinity infinite loop
+Subject: [PATCH 201/215] MIPS: GIC: Fix gic_set_affinity infinite loop
There is an infinite loop in gic_set_affinity. When irq_set_affinity
gets called on gic controller, it blocks forever.
diff --git a/target/linux/ramips/patches-3.10/0510-MIPS-Fix-SMP-core-calculations-when-using-MT-support.patch b/target/linux/ramips/patches-3.10/0202-MIPS-Fix-SMP-core-calculations-when-using-MT-support.patch
similarity index 93%
rename from target/linux/ramips/patches-3.10/0510-MIPS-Fix-SMP-core-calculations-when-using-MT-support.patch
rename to target/linux/ramips/patches-3.10/0202-MIPS-Fix-SMP-core-calculations-when-using-MT-support.patch
index e297876ab0..e3a2cabf27 100644
--- a/target/linux/ramips/patches-3.10/0510-MIPS-Fix-SMP-core-calculations-when-using-MT-support.patch
+++ b/target/linux/ramips/patches-3.10/0202-MIPS-Fix-SMP-core-calculations-when-using-MT-support.patch
@@ -1,7 +1,7 @@
-From c4d621e75e865fa5374946515ad0c5e060b9c446 Mon Sep 17 00:00:00 2001
+From 46b62174f655edf6a4befae7f9871c431146b1b6 Mon Sep 17 00:00:00 2001
From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Date: Wed, 11 Sep 2013 14:17:47 -0500
-Subject: [PATCH 056/105] MIPS: Fix SMP core calculations when using MT
+Subject: [PATCH 202/215] MIPS: Fix SMP core calculations when using MT
support.
The TCBIND register is only available if the core has MT support. It
diff --git a/target/linux/ramips/patches-3.10/0203-MIPS-Fix-accessing-to-per-cpu-data-when-flushing-the.patch b/target/linux/ramips/patches-3.10/0203-MIPS-Fix-accessing-to-per-cpu-data-when-flushing-the.patch
new file mode 100644
index 0000000000..fc853fa1bd
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0203-MIPS-Fix-accessing-to-per-cpu-data-when-flushing-the.patch
@@ -0,0 +1,84 @@
+From 871d1be8c3ce46b8ef395b56cd0e37cede10e76a Mon Sep 17 00:00:00 2001
+From: Ralf Baechle <ralf@linux-mips.org>
+Date: Tue, 17 Sep 2013 12:44:31 +0200
+Subject: [PATCH 203/215] MIPS: Fix accessing to per-cpu data when flushing
+ the cache
+
+This fixes the following issue
+
+BUG: using smp_processor_id() in preemptible [00000000] code: kjournald/1761
+caller is blast_dcache32+0x30/0x254
+Call Trace:
+[<8047f02c>] dump_stack+0x8/0x34
+[<802e7e40>] debug_smp_processor_id+0xe0/0xf0
+[<80114d94>] blast_dcache32+0x30/0x254
+[<80118484>] r4k_dma_cache_wback_inv+0x200/0x288
+[<80110ff0>] mips_dma_map_sg+0x108/0x180
+[<80355098>] ide_dma_prepare+0xf0/0x1b8
+[<8034eaa4>] do_rw_taskfile+0x1e8/0x33c
+[<8035951c>] ide_do_rw_disk+0x298/0x3e4
+[<8034a3c4>] do_ide_request+0x2e0/0x704
+[<802bb0dc>] __blk_run_queue+0x44/0x64
+[<802be000>] queue_unplugged.isra.36+0x1c/0x54
+[<802beb94>] blk_flush_plug_list+0x18c/0x24c
+[<802bec6c>] blk_finish_plug+0x18/0x48
+[<8026554c>] journal_commit_transaction+0x3b8/0x151c
+[<80269648>] kjournald+0xec/0x238
+[<8014ac00>] kthread+0xb8/0xc0
+[<8010268c>] ret_from_kernel_thread+0x14/0x1c
+
+Caches in most systems are identical - but not always, so we can't avoid
+the use of smp_call_function() by just looking at the boot CPU's data,
+have to fiddle with preemption instead.
+
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+Cc: Markos Chandras <markos.chandras@imgtec.com>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/5835
+(cherry picked from commit ff522058bd717506b2fa066fa564657f2b86477e)
+---
+ arch/mips/mm/c-r4k.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -12,6 +12,7 @@
+ #include <linux/highmem.h>
+ #include <linux/kernel.h>
+ #include <linux/linkage.h>
++#include <linux/preempt.h>
+ #include <linux/sched.h>
+ #include <linux/smp.h>
+ #include <linux/mm.h>
+@@ -601,6 +602,7 @@ static void r4k_dma_cache_wback_inv(unsi
+ /* Catch bad driver code */
+ BUG_ON(size == 0);
+
++ preempt_disable();
+ if (cpu_has_inclusive_pcaches) {
+ if (size >= scache_size)
+ r4k_blast_scache();
+@@ -621,6 +623,7 @@ static void r4k_dma_cache_wback_inv(unsi
+ R4600_HIT_CACHEOP_WAR_IMPL;
+ blast_dcache_range(addr, addr + size);
+ }
++ preempt_enable();
+
+ bc_wback_inv(addr, size);
+ __sync();
+@@ -631,6 +634,7 @@ static void r4k_dma_cache_inv(unsigned l
+ /* Catch bad driver code */
+ BUG_ON(size == 0);
+
++ preempt_disable();
+ if (cpu_has_inclusive_pcaches) {
+ if (size >= scache_size)
+ r4k_blast_scache();
+@@ -655,6 +659,7 @@ static void r4k_dma_cache_inv(unsigned l
+ R4600_HIT_CACHEOP_WAR_IMPL;
+ blast_inv_dcache_range(addr, addr + size);
+ }
++ preempt_enable();
+
+ bc_inv(addr, size);
+ __sync();
diff --git a/target/linux/ramips/patches-3.10/0203-serial-rt5350-fix-enable-uartf-kernel-panic.patch b/target/linux/ramips/patches-3.10/0203-serial-rt5350-fix-enable-uartf-kernel-panic.patch
deleted file mode 100644
index a687caabee..0000000000
--- a/target/linux/ramips/patches-3.10/0203-serial-rt5350-fix-enable-uartf-kernel-panic.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/drivers/tty/serial/8250/8250_core.c
-+++ b/drivers/tty/serial/8250/8250_core.c
-@@ -2499,7 +2499,7 @@ serial8250_pm(struct uart_port *port, un
- static unsigned int serial8250_port_size(struct uart_8250_port *pt)
- {
- if (pt->port.iotype == UPIO_AU)
-- return 0x1000;
-+ return 0x100;
- if (is_omap1_8250(pt))
- return 0x16 << pt->port.regshift;
-
diff --git a/target/linux/ramips/patches-3.10/0204-MIPS-74K-1074K-Correct-erratum-workaround.patch b/target/linux/ramips/patches-3.10/0204-MIPS-74K-1074K-Correct-erratum-workaround.patch
new file mode 100644
index 0000000000..0a80ea5f79
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0204-MIPS-74K-1074K-Correct-erratum-workaround.patch
@@ -0,0 +1,60 @@
+From 3da3528448850ccde412d52fb939575641ada80d Mon Sep 17 00:00:00 2001
+From: "Maciej W. Rozycki" <macro@linux-mips.org>
+Date: Wed, 18 Sep 2013 19:08:15 +0100
+Subject: [PATCH 204/215] MIPS: 74K/1074K: Correct erratum workaround.
+
+Make sure 74K revision numbers are not applied to the 1074K. Also catch
+invalid usage.
+
+Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
+Cc: Steven J. Hill <Steven.Hill@imgtec.com>
+Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/5857/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+(cherry picked from commit 9213ad77070ea75fc3a5e43e3d9e9c4146e4930a)
+---
+ arch/mips/mm/c-r4k.c | 26 ++++++++++++++++++--------
+ 1 file changed, 18 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -785,20 +785,30 @@ static inline void rm7k_erratum31(void)
+
+ static inline void alias_74k_erratum(struct cpuinfo_mips *c)
+ {
++ unsigned int imp = c->processor_id & 0xff00;
++ unsigned int rev = c->processor_id & PRID_REV_MASK;
++
+ /*
+ * Early versions of the 74K do not update the cache tags on a
+ * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
+ * aliases. In this case it is better to treat the cache as always
+ * having aliases.
+ */
+- if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
+- c->dcache.flags |= MIPS_CACHE_VTAG;
+- if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
+- write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+- if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
+- ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
+- c->dcache.flags |= MIPS_CACHE_VTAG;
+- write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
++ switch (imp) {
++ case PRID_IMP_74K:
++ if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
++ c->dcache.flags |= MIPS_CACHE_VTAG;
++ if (rev == PRID_REV_ENCODE_332(2, 4, 0))
++ write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
++ break;
++ case PRID_IMP_1074K:
++ if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
++ c->dcache.flags |= MIPS_CACHE_VTAG;
++ write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
++ }
++ break;
++ default:
++ BUG();
+ }
+ }
+
diff --git a/target/linux/ramips/patches-3.10/0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch b/target/linux/ramips/patches-3.10/0205-MIPS-GIC-Send-IPIs-using-the-GIC.patch
similarity index 95%
rename from target/linux/ramips/patches-3.10/0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch
rename to target/linux/ramips/patches-3.10/0205-MIPS-GIC-Send-IPIs-using-the-GIC.patch
index 366fdb2aff..01ac8757e3 100644
--- a/target/linux/ramips/patches-3.10/0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch
+++ b/target/linux/ramips/patches-3.10/0205-MIPS-GIC-Send-IPIs-using-the-GIC.patch
@@ -1,7 +1,7 @@
-From 43334f8438704001deb258b6e7223699bd336c77 Mon Sep 17 00:00:00 2001
+From 5a43b20db2fd18f8ea5f3a919d4bc9d9c2038c6c Mon Sep 17 00:00:00 2001
From: "Steven J. Hill" <Steven.Hill@imgtec.com>
Date: Wed, 25 Sep 2013 14:58:19 -0500
-Subject: [PATCH 093/105] MIPS: GIC: Send IPIs using the GIC.
+Subject: [PATCH 205/215] MIPS: GIC: Send IPIs using the GIC.
If a GIC present, then use it to send IPIs between the cores.
diff --git a/target/linux/ramips/patches-3.10/0502-MIPS-ralink-add-MT7621-support.patch b/target/linux/ramips/patches-3.10/0206-MIPS-ralink-add-MT7621-support.patch
similarity index 77%
rename from target/linux/ramips/patches-3.10/0502-MIPS-ralink-add-MT7621-support.patch
rename to target/linux/ramips/patches-3.10/0206-MIPS-ralink-add-MT7621-support.patch
index 83a48f37c1..74fdf1d787 100644
--- a/target/linux/ramips/patches-3.10/0502-MIPS-ralink-add-MT7621-support.patch
+++ b/target/linux/ramips/patches-3.10/0206-MIPS-ralink-add-MT7621-support.patch
@@ -1,23 +1,39 @@
-From 99342a0481d49b6e1ade90fdb02f597cb75f103f Mon Sep 17 00:00:00 2001
+From 259ce690b20562aa5dfef711e72ed02a4f514ce4 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
-Date: Mon, 2 Dec 2013 16:11:09 +0100
-Subject: [PATCH 502/507] MIPS: ralink: add MT7621 support
+Date: Sun, 16 Mar 2014 05:19:37 +0000
+Subject: [PATCH 206/215] MIPS: ralink: add MT7621 support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
- arch/mips/include/asm/mach-ralink/mt7621.h | 39 +++++
+ arch/mips/include/asm/gic.h | 2 +
+ arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++
+ arch/mips/kernel/vmlinux.lds.S | 1 +
arch/mips/ralink/Kconfig | 18 ++
arch/mips/ralink/Makefile | 7 +-
- arch/mips/ralink/Platform | 5 +
- arch/mips/ralink/irq-gic.c | 255 ++++++++++++++++++++++++++++
+ arch/mips/ralink/Platform | 7 +
+ arch/mips/ralink/irq-gic.c | 271 ++++++++++++++++++++++++++++
arch/mips/ralink/malta-amon.c | 81 +++++++++
- arch/mips/ralink/mt7621.c | 186 ++++++++++++++++++++
- 7 files changed, 590 insertions(+), 1 deletion(-)
+ arch/mips/ralink/mt7621.c | 183 +++++++++++++++++++
+ 9 files changed, 608 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
create mode 100644 arch/mips/ralink/irq-gic.c
create mode 100644 arch/mips/ralink/malta-amon.c
create mode 100644 arch/mips/ralink/mt7621.c
+--- a/arch/mips/include/asm/gic.h
++++ b/arch/mips/include/asm/gic.h
+@@ -19,7 +19,11 @@
+ #define GIC_TRIG_EDGE 1
+ #define GIC_TRIG_LEVEL 0
+
++#define GIC_NUM_INTRS 64
++
++#ifndef GIC_NUM_INTRS
+ #define GIC_NUM_INTRS (24 + NR_CPUS * 2)
++#endif
+
+ #define MSK(n) ((1 << (n)) - 1)
+ #define REG32(addr) (*(volatile unsigned int *) (addr))
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
@@ -0,0 +1,39 @@
@@ -60,19 +76,30 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
+
+#endif
+--- a/arch/mips/kernel/vmlinux.lds.S
++++ b/arch/mips/kernel/vmlinux.lds.S
+@@ -51,6 +51,7 @@ SECTIONS
+ /* read-only */
+ _text = .; /* Text and read-only data */
+ .text : {
++ /*. = . + 0x8000; */
+ TEXT_TEXT
+ SCHED_TEXT
+ LOCK_TEXT
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
-@@ -1,5 +1,10 @@
- if RALINK
+@@ -7,6 +7,11 @@ config CLKEVT_RT3352
+ select CLKSRC_OF
+ select CLKSRC_MMIO
+config IRQ_INTC
+ bool
+ default y
+ depends on !SOC_MT7621
+
- config CLKEVT_RT3352
- bool "Systick Clockevent source"
- depends on SOC_RT305X || SOC_MT7620
+ choice
+ prompt "Ralink SoC selection"
+ default SOC_RT305X
@@ -35,6 +40,15 @@ choice
select USB_ARCH_HAS_EHCI
select HW_HAS_PCI
@@ -102,20 +129,22 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
endif
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
-@@ -6,7 +6,11 @@
+@@ -6,16 +6,21 @@
# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-obj-y := prom.o of.o reset.o clk.o irq.o timer.o
+obj-y := prom.o of.o reset.o clk.o timer.o
-+
-+obj-$(CONFIG_IRQ_INTC) += irq.o
-+obj-$(CONFIG_IRQ_GIC) += irq-gic.o
-+obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
-@@ -16,6 +20,7 @@ obj-$(CONFIG_SOC_RT288X) += rt288x.o
+ obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
+
++obj-$(CONFIG_IRQ_INTC) += irq.o
++obj-$(CONFIG_IRQ_GIC) += irq-gic.o
++obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
++
+ obj-$(CONFIG_SOC_RT288X) += rt288x.o
obj-$(CONFIG_SOC_RT305X) += rt305x.o
obj-$(CONFIG_SOC_RT3883) += rt3883.o
obj-$(CONFIG_SOC_MT7620) += mt7620.o
@@ -138,7 +167,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
--- /dev/null
+++ b/arch/mips/ralink/irq-gic.c
-@@ -0,0 +1,255 @@
+@@ -0,0 +1,271 @@
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
@@ -162,61 +191,20 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+
+#include <asm/mach-ralink/mt7621.h>
+
-+static unsigned long _gcmp_base;
++unsigned long _gcmp_base;
+static int gic_resched_int_base = 56;
+static int gic_call_int_base = 60;
+static struct irq_chip *irq_gic;
++static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
++
++#if defined(CONFIG_MIPS_MT_SMP)
++static int gic_resched_int_base;
++static int gic_call_int_base;
+
+#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
+#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
+
-+static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //0
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { GIC_UNUSED },
-+ { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //FE
-+ { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //PCIE0
-+ { GIC_UNUSED},
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //10
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { GIC_UNUSED },
-+ { GIC_UNUSED },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //20
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { GIC_UNUSED },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //25
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },//30
-+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
-+};
-+
-+static struct gic_intr_map ipi_intr_map[8] = {
-+ { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
-+ { 1, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
-+ { 2, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
-+ { 3, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
-+ { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
-+ { 1, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
-+ { 2, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
-+ { 3, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
-+};
-+
-+static irqreturn_t
-+ipi_resched_interrupt(int irq, void *dev_id)
++static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
+{
+ scheduler_ipi();
+
@@ -243,6 +231,43 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ .name = "ipi call"
+};
+
++#endif
++
++static void __init
++gic_fill_map(void)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
++ gic_intr_map[i].cpunum = 0;
++ gic_intr_map[i].pin = GIC_CPU_INT0;
++ gic_intr_map[i].polarity = GIC_POL_POS;
++ gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
++ gic_intr_map[i].flags = GIC_FLAG_IPI;
++ }
++
++#if defined(CONFIG_MIPS_MT_SMP)
++ {
++ int cpu;
++
++ gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
++ gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
++
++ i = gic_resched_int_base;
++
++ for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
++ gic_intr_map[i + cpu].cpunum = cpu;
++ gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
++ gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
++
++ gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
++ gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
++ gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
++ }
++ }
++#endif
++}
++
+void
+gic_irq_ack(struct irq_data *d)
+{
@@ -267,12 +292,17 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+}
+
+static void
-+vi_gic_irqdispatch(void)
++gic_irqdispatch(void)
+{
-+ int irq = gic_get_int();
++ unsigned int irq = gic_get_int();
+
-+ if (irq >= 0)
++ if (likely(irq < GIC_NUM_INTRS))
+ do_IRQ(MIPS_GIC_IRQ_BASE + irq);
++ else {
++ pr_err("Spurious GIC Interrupt!\n");
++ spurious_interrupt();
++ }
++
+}
+
+static void
@@ -281,6 +311,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ do_IRQ(cp0_compare_irq);
+}
+
++#if defined(CONFIG_MIPS_MT_SMP)
+unsigned int
+plat_ipi_call_int_xlate(unsigned int cpu)
+{
@@ -292,18 +323,23 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+{
+ return GIC_RESCHED_INT(cpu);
+}
++#endif
+
+asmlinkage void
+plat_irq_dispatch(void)
+{
+ unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+
-+ if (pending & CAUSEF_IP7)
-+ do_IRQ(cp0_compare_irq);
-+ else if (pending & (CAUSEF_IP4 | CAUSEF_IP3))
-+ vi_gic_irqdispatch();
-+ else
++ if (unlikely(!pending)) {
++ pr_err("Spurious CP0 Interrupt!\n");
+ spurious_interrupt();
++ } else {
++ if (pending & CAUSEF_IP7)
++ do_IRQ(cp0_compare_irq);
++
++ if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
++ gic_irqdispatch();
++ }
+}
+
+unsigned int __cpuinit
@@ -315,7 +351,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+static int
+gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
-+ irq_set_chip_and_handler(irq, irq_gic, handle_percpu_irq);
++ irq_set_chip_and_handler(irq, irq_gic,
++#if defined(CONFIG_MIPS_MT_SMP)
++ (hw >= gic_resched_int_base) ?
++ handle_percpu_irq :
++#endif
++ handle_level_irq);
+
+ return 0;
+}
@@ -356,12 +397,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
+ gic_present = 1;
+ if (cpu_has_vint) {
-+ set_vi_handler(3, vi_gic_irqdispatch);
-+ set_vi_handler(4, vi_gic_irqdispatch);
++ set_vi_handler(2, gic_irqdispatch);
++ set_vi_handler(3, gic_irqdispatch);
++ set_vi_handler(4, gic_irqdispatch);
+ set_vi_handler(7, vi_timer_irqdispatch);
+ }
+
-+ memcpy(&gic_intr_map[gic_resched_int_base], ipi_intr_map, sizeof(ipi_intr_map));
++ gic_fill_map();
++
+ gic_init(gic.start, resource_size(&gic), gic_intr_map,
+ ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
+
@@ -373,13 +416,15 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ if (!domain)
+ panic("Failed to add irqdomain");
+
-+ for (i = 0; i < NR_CPUS; i++) {
++#if defined(CONFIG_MIPS_MT_SMP)
++ for (i = 0; i < nr_cpu_ids; i++) {
+ setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
+ setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
+ }
++#endif
+
-+ change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 |
-+ STATUSF_IP7);
++ change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
++ STATUSF_IP2);
+ return 0;
+}
+
@@ -480,7 +525,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+}
--- /dev/null
+++ b/arch/mips/ralink/mt7621.c
-@@ -0,0 +1,186 @@
+@@ -0,0 +1,183 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
@@ -499,6 +544,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#include <asm/gcmpregs.h>
+
+#include <asm/mipsregs.h>
++#include <asm/smp-ops.h>
+#include <asm/mach-ralink/ralink_regs.h>
+#include <asm/mach-ralink/mt7621.h>
+
@@ -597,22 +643,17 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ cpu_fdiv = ((clk_sts >> 8) & 0x1F);
+ cpu_ffrac = (clk_sts & 0x1F);
+ cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
-+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ break;
+
+ case 1:
+ fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
+ syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
+ xtal_mode = (syscfg >> 6) & 0x7;
-+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ if(xtal_mode >= 6) { //25Mhz Xtal
-+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ cpu_clk = 25 * fbdiv * 1000 * 1000;
+ } else if(xtal_mode >=3) { //40Mhz Xtal
-+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ cpu_clk = 40 * fbdiv * 1000 * 1000;
+ } else { // 20Mhz Xtal
-+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ cpu_clk = 20 * fbdiv * 1000 * 1000;
+ }
+ break;
@@ -621,6 +662,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ ralink_clk_add("cpu", cpu_clk);
+ ralink_clk_add("1e000b00.spi", 50000000);
+ ralink_clk_add("1e000c00.uartlite", 50000000);
++ ralink_clk_add("1e000d00.uart", 50000000);
+}
+
+void __init ralink_of_remap(void)
@@ -667,3 +709,15 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ if (register_cmp_smp_ops())
+ panic("failed to register_vsmp_smp_ops()");
+}
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/irq.h
+@@ -0,0 +1,9 @@
++#ifndef __ASM_MACH_RALINK_IRQ_H
++#define __ASM_MACH_RALINK_IRQ_H
++
++#define GIC_NUM_INTRS 64
++#define NR_IRQS 256
++
++#include_next <irq.h>
++
++#endif
diff --git a/target/linux/ramips/patches-3.10/0207-MIPS-ralink-add-MT7621-defconfig.patch b/target/linux/ramips/patches-3.10/0207-MIPS-ralink-add-MT7621-defconfig.patch
new file mode 100644
index 0000000000..1dc97266b9
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0207-MIPS-ralink-add-MT7621-defconfig.patch
@@ -0,0 +1,211 @@
+From 29b1c70ab171609fee58ef6642086d571c0ba0c2 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 27 Jan 2014 13:12:41 +0000
+Subject: [PATCH 207/215] MIPS: ralink: add MT7621 defconfig
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/configs/mt7621_defconfig | 197 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 197 insertions(+)
+ create mode 100644 arch/mips/configs/mt7621_defconfig
+
+--- /dev/null
++++ b/arch/mips/configs/mt7621_defconfig
+@@ -0,0 +1,197 @@
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_SYSVIPC=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_RCU_FANOUT=32
++CONFIG_UIDGID_STRICT_TYPE_CHECKS=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE="/openwrt/trunk/build_dir/target-mipsel_24kec+dsp_uClibc-0.9.33.2/root-ramips /openwrt/trunk/target/linux/generic/image/initramfs-base-files.txt"
++CONFIG_INITRAMFS_ROOT_UID=1000
++CONFIG_INITRAMFS_ROOT_GID=1000
++# CONFIG_RD_GZIP is not set
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++# CONFIG_AIO is not set
++CONFIG_EMBEDDED=y
++# CONFIG_VM_EVENT_COUNTERS is not set
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_COMPAT_BRK is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++# CONFIG_BLK_DEV_BSG is not set
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_IOSCHED_CFQ is not set
++CONFIG_SMP=y
++CONFIG_NR_CPUS=4
++CONFIG_SCHED_SMT=y
++# CONFIG_COMPACTION is not set
++# CONFIG_CROSS_MEMORY_ATTACH is not set
++# CONFIG_SECCOMP is not set
++CONFIG_HZ_100=y
++CONFIG_CMDLINE_BOOL=y
++CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_IP_MULTIPLE_TABLES=y
++CONFIG_IP_ROUTE_MULTIPATH=y
++CONFIG_IP_ROUTE_VERBOSE=y
++CONFIG_IP_MROUTE=y
++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
++CONFIG_ARPD=y
++CONFIG_SYN_COOKIES=y
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++# CONFIG_INET_LRO is not set
++# CONFIG_INET_DIAG is not set
++CONFIG_TCP_CONG_ADVANCED=y
++# CONFIG_TCP_CONG_BIC is not set
++# CONFIG_TCP_CONG_WESTWOOD is not set
++# CONFIG_TCP_CONG_HTCP is not set
++CONFIG_IPV6_PRIVACY=y
++# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET6_XFRM_MODE_BEET is not set
++# CONFIG_IPV6_SIT is not set
++CONFIG_IPV6_MULTIPLE_TABLES=y
++CONFIG_IPV6_SUBTREES=y
++CONFIG_IPV6_MROUTE=y
++CONFIG_NETFILTER=y
++# CONFIG_BRIDGE_NETFILTER is not set
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NETFILTER_XT_MARK=m
++CONFIG_NETFILTER_XT_TARGET_LOG=m
++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
++CONFIG_NETFILTER_XT_MATCH_COMMENT=m
++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
++CONFIG_NETFILTER_XT_MATCH_LIMIT=m
++CONFIG_NETFILTER_XT_MATCH_MAC=m
++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
++CONFIG_NETFILTER_XT_MATCH_STATE=m
++CONFIG_NETFILTER_XT_MATCH_TIME=m
++CONFIG_NF_CONNTRACK_IPV4=m
++# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
++CONFIG_IP_NF_IPTABLES=m
++CONFIG_IP_NF_FILTER=m
++CONFIG_IP_NF_TARGET_REJECT=m
++CONFIG_NF_NAT_IPV4=m
++CONFIG_IP_NF_TARGET_MASQUERADE=m
++CONFIG_IP_NF_TARGET_REDIRECT=m
++CONFIG_IP_NF_MANGLE=m
++CONFIG_IP_NF_RAW=m
++CONFIG_NF_CONNTRACK_IPV6=m
++CONFIG_IP6_NF_IPTABLES=m
++CONFIG_IP6_NF_MATCH_AH=m
++CONFIG_IP6_NF_MATCH_EUI64=m
++CONFIG_IP6_NF_MATCH_FRAG=m
++CONFIG_IP6_NF_MATCH_OPTS=m
++CONFIG_IP6_NF_MATCH_IPV6HEADER=m
++CONFIG_IP6_NF_MATCH_MH=m
++CONFIG_IP6_NF_MATCH_RT=m
++CONFIG_IP6_NF_FILTER=m
++CONFIG_IP6_NF_TARGET_REJECT=m
++CONFIG_IP6_NF_MANGLE=m
++CONFIG_IP6_NF_RAW=m
++CONFIG_BRIDGE=m
++# CONFIG_BRIDGE_IGMP_SNOOPING is not set
++CONFIG_VLAN_8021Q=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_FQ_CODEL=y
++CONFIG_HAMRADIO=y
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++# CONFIG_FIRMWARE_IN_KERNEL is not set
++CONFIG_MTD=y
++CONFIG_MTD_CMDLINE_PARTS=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_CFI=y
++CONFIG_MTD_CFI_AMDSTD=y
++CONFIG_MTD_COMPLEX_MAPPINGS=y
++CONFIG_MTD_PHYSMAP=y
++CONFIG_MTD_M25P80=y
++CONFIG_EEPROM_93CX6=m
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++CONFIG_NETDEVICES=y
++# CONFIG_NET_PACKET_ENGINE is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++CONFIG_PHYLIB=y
++CONFIG_SWCONFIG=y
++CONFIG_PPP=m
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MULTILINK=y
++CONFIG_PPPOE=m
++CONFIG_PPP_ASYNC=m
++CONFIG_ISDN=y
++# CONFIG_INPUT is not set
++# CONFIG_SERIO is not set
++# CONFIG_VT is not set
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_DEVKMEM is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++# CONFIG_SERIAL_8250_PCI is not set
++CONFIG_SERIAL_8250_RUNTIME_UARTS=2
++CONFIG_SPI=y
++CONFIG_GPIOLIB=y
++CONFIG_GPIO_SYSFS=y
++# CONFIG_HWMON is not set
++CONFIG_WATCHDOG=y
++CONFIG_WATCHDOG_CORE=y
++# CONFIG_VGA_ARB is not set
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_PLATFORM=y
++CONFIG_USB_MT7621_XHCI_PLATFORM=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_PHY=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=m
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_STAGING=y
++CONFIG_USB_DWC2=m
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_RESET_CONTROLLER=y
++# CONFIG_FIRMWARE_MEMMAP is not set
++# CONFIG_DNOTIFY is not set
++# CONFIG_PROC_PAGE_MONITOR is not set
++CONFIG_TMPFS=y
++CONFIG_TMPFS_XATTR=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_SUMMARY=y
++CONFIG_JFFS2_FS_XATTR=y
++# CONFIG_JFFS2_FS_POSIX_ACL is not set
++# CONFIG_JFFS2_FS_SECURITY is not set
++CONFIG_JFFS2_COMPRESSION_OPTIONS=y
++# CONFIG_JFFS2_ZLIB is not set
++CONFIG_SQUASHFS=y
++# CONFIG_SQUASHFS_ZLIB is not set
++CONFIG_SQUASHFS_XZ=y
++CONFIG_PRINTK_TIME=y
++# CONFIG_ENABLE_MUST_CHECK is not set
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_STRIP_ASM_SYMS=y
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_SCHED_DEBUG is not set
++CONFIG_DEBUG_INFO=y
++CONFIG_DEBUG_INFO_REDUCED=y
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++# CONFIG_FTRACE is not set
++CONFIG_CRYPTO_ARC4=m
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++# CONFIG_VIRTUALIZATION is not set
++CONFIG_CRC_ITU_T=m
++CONFIG_CRC32_SARWATE=y
++# CONFIG_XZ_DEC_X86 is not set
++CONFIG_AVERAGE=y
diff --git a/target/linux/ramips/patches-3.10/0208-MIPS-ralink-add-MT7621-dts-file.patch b/target/linux/ramips/patches-3.10/0208-MIPS-ralink-add-MT7621-dts-file.patch
new file mode 100644
index 0000000000..880252856b
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0208-MIPS-ralink-add-MT7621-dts-file.patch
@@ -0,0 +1,300 @@
+From dd4f939bb7c30f9256a35d31de673241ead350ab Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 24 Jan 2014 17:01:22 +0100
+Subject: [PATCH 208/215] MIPS: ralink: add MT7621 dts file
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/dts/Makefile | 1 +
+ arch/mips/ralink/dts/mt7621.dtsi | 257 ++++++++++++++++++++++++++++++++++
+ arch/mips/ralink/dts/mt7621_eval.dts | 16 +++
+ 3 files changed, 274 insertions(+)
+ create mode 100644 arch/mips/ralink/dts/mt7621.dtsi
+ create mode 100644 arch/mips/ralink/dts/mt7621_eval.dts
+
+--- a/arch/mips/ralink/dts/Makefile
++++ b/arch/mips/ralink/dts/Makefile
+@@ -2,3 +2,4 @@ obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_
+ obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
+ obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
+ obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o
++obj-$(CONFIG_DTB_MT7621_EVAL) := mt7621_eval.dtb.o
+--- /dev/null
++++ b/arch/mips/ralink/dts/mt7621.dtsi
+@@ -0,0 +1,257 @@
++/ {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "ralink,mtk7620a-soc";
++
++ cpus {
++ cpu@0 {
++ compatible = "mips,mips24KEc";
++ };
++ };
++
++ cpuintc: cpuintc@0 {
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ interrupt-controller;
++ compatible = "mti,cpu-interrupt-controller";
++ };
++
++ palmbus@1E000000 {
++ compatible = "palmbus";
++ reg = <0x1E000000 0x100000>;
++ ranges = <0x0 0x1E000000 0x0FFFFF>;
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ sysc@0 {
++ compatible = "mtk,mt7621-sysc";
++ reg = <0x0 0x100>;
++ };
++
++ wdt@100 {
++ compatible = "mtk,mt7621-wdt";
++ reg = <0x100 0x100>;
++ };
++
++ gpio@600 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ compatible = "mtk,mt7621-gpio";
++ reg = <0x600 0x100>;
++
++ gpio0: bank@0 {
++ reg = <0>;
++ compatible = "mtk,mt7621-gpio-bank";
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++
++ gpio1: bank@1 {
++ reg = <1>;
++ compatible = "mtk,mt7621-gpio-bank";
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++
++ gpio2: bank@2 {
++ reg = <2>;
++ compatible = "mtk,mt7621-gpio-bank";
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++ };
++
++ memc@5000 {
++ compatible = "mtk,mt7621-memc";
++ reg = <0x300 0x100>;
++ };
++
++ uartlite@c00 {
++ compatible = "ns16550a";
++ reg = <0xc00 0x100>;
++
++ interrupt-parent = <&gic>;
++ interrupts = <26>;
++
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ no-loopback-test;
++ };
++
++ uart@d00 {
++ compatible = "ns16550a";
++ reg = <0xd00 0x100>;
++
++ interrupt-parent = <&gic>;
++ interrupts = <27>;
++
++ fifo-size = <16>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ no-loopback-test;
++ };
++
++ spi@b00 {
++ status = "okay";
++
++ compatible = "ralink,mt7621-spi";
++ reg = <0xb00 0x100>;
++
++ resets = <&rstctrl 18>;
++ reset-names = "spi";
++
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++/* pinctrl-names = "default";
++ pinctrl-0 = <&spi_pins>;*/
++
++ m25p80@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "en25q64";
++ reg = <0 0>;
++ linux,modalias = "m25p80", "en25q64";
++ spi-max-frequency = <10000000>;
++
++ m25p,chunked-io;
++
++ partition@0 {
++ label = "u-boot";
++ reg = <0x0 0x30000>;
++ read-only;
++ };
++
++ partition@30000 {
++ label = "u-boot-env";
++ reg = <0x30000 0x10000>;
++ read-only;
++ };
++
++ factory: partition@40000 {
++ label = "factory";
++ reg = <0x40000 0x10000>;
++ read-only;
++ };
++
++ partition@50000 {
++ label = "firmware";
++ reg = <0x50000 0x7a0000>;
++ };
++
++ partition@7f0000 {
++ label = "test";
++ reg = <0x7f0000 0x10000>;
++ };
++ };
++ };
++ };
++
++ rstctrl: rstctrl {
++ compatible = "ralink,rt2880-reset";
++ #reset-cells = <1>;
++ };
++
++ sdhci@1E130000 {
++ compatible = "ralink,mt7620a-sdhci";
++ reg = <0x1E130000 4000>;
++
++ interrupt-parent = <&gic>;
++ interrupts = <20>;
++ };
++
++ xhci@1E1C0000 {
++ compatible = "xhci-platform";
++ reg = <0x1E1C0000 4000>;
++
++ interrupt-parent = <&gic>;
++ interrupts = <22>;
++ };
++
++ gic: gic@1fbc0000 {
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ interrupt-controller;
++ compatible = "ralink,mt7621-gic";
++ reg = < 0x1fbc0000 0x80 /* gic */
++ 0x1fbf0000 0x8000 /* cpc */
++ 0x1fbf8000 0x8000 /* gpmc */
++ >;
++ };
++
++ nand@1e003000 {
++ compatible = "mtk,mt7621-nand";
++ bank-width = <2>;
++ reg = <0x1e003000 0x800
++ 0x1e003800 0x800>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "uboot";
++ reg = <0x00000 0x80000>; /* 64 KB */
++ };
++ partition@80000 {
++ label = "uboot_env";
++ reg = <0x80000 0x80000>; /* 64 KB */
++ };
++ partition@100000 {
++ label = "factory";
++ reg = <0x100000 0x40000>;
++ };
++ partition@140000 {
++ label = "rootfs";
++ reg = <0x140000 0xec0000>;
++ };
++ };
++
++ ethernet@1e100000 {
++ compatible = "ralink,mt7621-eth";
++ reg = <0x1e100000 10000>;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ralink,port-map = "llllw";
++
++ interrupt-parent = <&gic>;
++ interrupts = <3>;
++
++/* resets = <&rstctrl 21 &rstctrl 23>;
++ reset-names = "fe", "esw";
++
++ port@4 {
++ compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
++ reg = <4>;
++
++ status = "disabled";
++ };
++
++ port@5 {
++ compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
++ reg = <5>;
++
++ status = "disabled";
++ };
++*/
++ mdio-bus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy1f: ethernet-phy@1f {
++ reg = <0x1f>;
++ phy-mode = "rgmii";
++
++/* interrupt-parent = <&gic>;
++ interrupts = <23>;
++*/ };
++ };
++ };
++
++ gsw@1e110000 {
++ compatible = "ralink,mt7620a-gsw";
++ reg = <0x1e110000 8000>;
++ };
++};
+--- /dev/null
++++ b/arch/mips/ralink/dts/mt7621_eval.dts
+@@ -0,0 +1,16 @@
++/dts-v1/;
++
++/include/ "mt7621.dtsi"
++
++/ {
++ compatible = "ralink,mt7621-eval-board", "ralink,mt7621-soc";
++ model = "Ralink MT7621 evaluation board";
++
++ memory@0 {
++ reg = <0x0 0x2000000>;
++ };
++
++ chosen {
++ bootargs = "console=ttyS0,57600";
++ };
++};
diff --git a/target/linux/ramips/patches-3.10/0503-MIPS-ralink-add-MT7621-early_printk-support.patch b/target/linux/ramips/patches-3.10/0209-MIPS-ralink-add-MT7621-early_printk-support.patch
similarity index 68%
rename from target/linux/ramips/patches-3.10/0503-MIPS-ralink-add-MT7621-early_printk-support.patch
rename to target/linux/ramips/patches-3.10/0209-MIPS-ralink-add-MT7621-early_printk-support.patch
index 0da9480804..d518ee6800 100644
--- a/target/linux/ramips/patches-3.10/0503-MIPS-ralink-add-MT7621-early_printk-support.patch
+++ b/target/linux/ramips/patches-3.10/0209-MIPS-ralink-add-MT7621-early_printk-support.patch
@@ -1,7 +1,7 @@
-From 643e61b22155cd95ae6e18e57da50acd120da091 Mon Sep 17 00:00:00 2001
+From a9d4390c6d27e737887388ccbb48f3767f9f89ef Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
-Date: Mon, 2 Dec 2013 16:11:33 +0100
-Subject: [PATCH 503/507] MIPS: ralink: add MT7621 early_printk support
+Date: Fri, 24 Jan 2014 17:01:17 +0100
+Subject: [PATCH 209/215] MIPS: ralink: add MT7621 early_printk support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
@@ -19,19 +19,19 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
#else
#define EARLY_UART_BASE 0x10000c00
#endif
-@@ -40,9 +42,13 @@ static inline u32 uart_r32(unsigned reg)
+@@ -40,9 +42,15 @@ static inline u32 uart_r32(unsigned reg)
void prom_putchar(unsigned char ch)
{
-- while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
+#ifdef CONFIG_SOC_MT7621
+ uart_w32(ch, UART_TX);
+ while ((uart_r32(0x14) & UART_LSR_THRE) == 0)
- ;
-- uart_w32(ch, UART_REG_TX);
++ ;
+#else
while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
;
-+ uart_w32(ch, UART_REG_TX);
+ uart_w32(ch, UART_REG_TX);
+ while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
+ ;
+#endif
}
diff --git a/target/linux/ramips/patches-3.10/0504-MIPS-ralink-add-pcie-driver.patch b/target/linux/ramips/patches-3.10/0210-MIPS-ralink-add-MT7621-pcie-driver.patch
similarity index 99%
rename from target/linux/ramips/patches-3.10/0504-MIPS-ralink-add-pcie-driver.patch
rename to target/linux/ramips/patches-3.10/0210-MIPS-ralink-add-MT7621-pcie-driver.patch
index 3ca3c9dbaf..8dae5b3e59 100644
--- a/target/linux/ramips/patches-3.10/0504-MIPS-ralink-add-pcie-driver.patch
+++ b/target/linux/ramips/patches-3.10/0210-MIPS-ralink-add-MT7621-pcie-driver.patch
@@ -1,7 +1,7 @@
-From 50216a5b7b3cc269043e7123db4bea262e35364e Mon Sep 17 00:00:00 2001
+From 6541090161342ef11cf319a7471aeb6769e20c2c Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
-Date: Mon, 2 Dec 2013 16:13:40 +0100
-Subject: [PATCH 504/507] MIPS: ralink: add pcie driver
+Date: Sun, 16 Mar 2014 05:22:39 +0000
+Subject: [PATCH 210/215] MIPS: ralink: add MT7621 pcie driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---
@@ -12,14 +12,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
-@@ -44,6 +44,7 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o
+@@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
+ obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
+ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
obj-$(CONFIG_SOC_MT7620) += pci-mt7620a.o
++obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
-+obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
- obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
- obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
--- /dev/null
+++ b/arch/mips/pci/pci-mt7621.c
@@ -0,0 +1,797 @@
diff --git a/target/linux/ramips/patches-3.10/0505-watchdog-add-MT7621-support.patch b/target/linux/ramips/patches-3.10/0211-watchdog-add-MT7621-support.patch
similarity index 82%
rename from target/linux/ramips/patches-3.10/0505-watchdog-add-MT7621-support.patch
rename to target/linux/ramips/patches-3.10/0211-watchdog-add-MT7621-support.patch
index b1d2da7766..dde4a35aef 100644
--- a/target/linux/ramips/patches-3.10/0505-watchdog-add-MT7621-support.patch
+++ b/target/linux/ramips/patches-3.10/0211-watchdog-add-MT7621-support.patch
@@ -1,7 +1,7 @@
-From eb50d97682d78af68388d24956a74de4ab751cf7 Mon Sep 17 00:00:00 2001
+From 158f2deb6349046ee4406578a5d3146ce9870cb3 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
-Date: Mon, 2 Dec 2013 16:18:36 +0100
-Subject: [PATCH 505/507] watchdog: add MT7621 support
+Date: Sun, 16 Mar 2014 05:24:42 +0000
+Subject: [PATCH 211/215] watchdog: add MT7621 support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
@@ -11,27 +11,29 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
3 files changed, 193 insertions(+)
create mode 100644 drivers/watchdog/mt7621_wdt.c
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -1116,7 +1116,14 @@ config LANTIQ_WDT
- config RALINK_WDT
- tristate "Ralink SoC watchdog"
- select WATCHDOG_CORE
-- depends on RALINK
-+ depends on RALINK && !SOC_MT7621
-+ help
-+ Hardware driver for the Ralink SoC Watchdog Timer.
-+
+Index: linux-3.10.32/drivers/watchdog/Kconfig
+===================================================================
+--- linux-3.10.32.orig/drivers/watchdog/Kconfig 2014-03-18 11:00:30.629639835 +0000
++++ linux-3.10.32/drivers/watchdog/Kconfig 2014-03-18 11:02:35.141634769 +0000
+@@ -1120,6 +1120,13 @@
+ help
+ Hardware driver for the Ralink SoC Watchdog Timer.
+
+config MT7621_WDT
+ tristate "Mediatek SoC watchdog"
+ select WATCHDOG_CORE
-+ depends on RALINK && SOC_MT7621
- help
- Hardware driver for the Ralink SoC Watchdog Timer.
++ depends on SOC_MT7621
++ help
++ Hardware driver for the Ralink SoC Watchdog Timer.
++
+ # PARISC Architecture
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -136,6 +136,7 @@ obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
+ # POWERPC Architecture
+Index: linux-3.10.32/drivers/watchdog/Makefile
+===================================================================
+--- linux-3.10.32.orig/drivers/watchdog/Makefile 2014-03-18 11:00:30.629639835 +0000
++++ linux-3.10.32/drivers/watchdog/Makefile 2014-03-18 11:00:31.317639807 +0000
+@@ -136,6 +136,7 @@
octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o
obj-$(CONFIG_RALINK_WDT) += rt2880_wdt.o
@@ -39,8 +41,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
# PARISC Architecture
---- /dev/null
-+++ b/drivers/watchdog/mt7621_wdt.c
+Index: linux-3.10.32/drivers/watchdog/mt7621_wdt.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-3.10.32/drivers/watchdog/mt7621_wdt.c 2014-03-18 11:00:31.317639807 +0000
@@ -0,0 +1,185 @@
+/*
+ * Ralink RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
diff --git a/target/linux/ramips/patches-3.10/0506-GPIO-ralink-add-mt7621-gpio-controller.patch b/target/linux/ramips/patches-3.10/0212-GPIO-ralink-add-mt7621-gpio-controller.patch
similarity index 76%
rename from target/linux/ramips/patches-3.10/0506-GPIO-ralink-add-mt7621-gpio-controller.patch
rename to target/linux/ramips/patches-3.10/0212-GPIO-ralink-add-mt7621-gpio-controller.patch
index d783d261ab..5a554fd349 100644
--- a/target/linux/ramips/patches-3.10/0506-GPIO-ralink-add-mt7621-gpio-controller.patch
+++ b/target/linux/ramips/patches-3.10/0212-GPIO-ralink-add-mt7621-gpio-controller.patch
@@ -1,41 +1,63 @@
-From e19957560170d63c6a5f0b1d7ba63695e4d1f033 Mon Sep 17 00:00:00 2001
+From 2a9b5a9fc1a0707b95dbe61dd1c30b9337cb457d Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
-Date: Mon, 2 Dec 2013 16:14:28 +0100
-Subject: [PATCH 506/507] GPIO: ralink: add mt7621 gpio controller
+Date: Sun, 16 Mar 2014 05:26:34 +0000
+Subject: [PATCH 212/215] GPIO: ralink: add mt7621 gpio controller
Signed-off-by: John Crispin <blogic@openwrt.org>
---
- arch/mips/Kconfig | 1 +
+ arch/mips/Kconfig | 5 +-
drivers/gpio/Kconfig | 6 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-mt7621.c | 183 ++++++++++++++++++++++++++++++++++++++++++++
- 4 files changed, 191 insertions(+)
+ 4 files changed, 194 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpio/gpio-mt7621.c
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -710,6 +710,12 @@ config GPIO_MSIC
+Index: linux-3.10.32/arch/mips/Kconfig
+===================================================================
+--- linux-3.10.32.orig/arch/mips/Kconfig 2014-03-18 11:00:30.945639822 +0000
++++ linux-3.10.32/arch/mips/Kconfig 2014-03-18 11:00:31.325639806 +0000
+@@ -448,7 +448,10 @@
+ select ARCH_REQUIRE_GPIOLIB
+ select PINCTRL
+ select PINCTRL_RT2880
+-
++ select ARCH_HAS_RESET_CONTROLLER
++ select RESET_CONTROLLER
++ select ARCH_REQUIRE_GPIOLIB
++
+ config SGI_IP22
+ bool "SGI IP22 (Indy/Indigo2)"
+ select FW_ARC
+Index: linux-3.10.32/drivers/gpio/Kconfig
+===================================================================
+--- linux-3.10.32.orig/drivers/gpio/Kconfig 2014-03-18 11:00:30.653639834 +0000
++++ linux-3.10.32/drivers/gpio/Kconfig 2014-03-18 11:02:01.901636126 +0000
+@@ -710,6 +710,12 @@
Enable support for GPIO on intel MSIC controllers found in
intel MID devices
+config GPIO_MT7621
+ bool "Mediatek GPIO Support"
-+ depends on RALINK && SOC_MT7621
++ depends on SOC_MT7621
+ help
+ Say yes here to support the Mediatek SoC GPIO device
+
comment "USB GPIO expanders:"
config GPIO_VIPERBOARD
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -88,3 +88,4 @@ obj-$(CONFIG_GPIO_WM831X) += gpio-wm831x
+Index: linux-3.10.32/drivers/gpio/Makefile
+===================================================================
+--- linux-3.10.32.orig/drivers/gpio/Makefile 2014-03-18 11:00:30.653639834 +0000
++++ linux-3.10.32/drivers/gpio/Makefile 2014-03-18 11:00:31.325639806 +0000
+@@ -88,3 +88,4 @@
obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o
obj-$(CONFIG_GPIO_WM8994) += gpio-wm8994.o
obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx.o
+obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o
---- /dev/null
-+++ b/drivers/gpio/gpio-mt7621.c
+Index: linux-3.10.32/drivers/gpio/gpio-mt7621.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-3.10.32/drivers/gpio/gpio-mt7621.c 2014-03-18 11:00:31.325639806 +0000
@@ -0,0 +1,183 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
diff --git a/target/linux/ramips/patches-3.10/0507-MTD-add-mt7621-nand-support.patch b/target/linux/ramips/patches-3.10/0213-MTD-add-mt7621-nand-support.patch
similarity index 99%
rename from target/linux/ramips/patches-3.10/0507-MTD-add-mt7621-nand-support.patch
rename to target/linux/ramips/patches-3.10/0213-MTD-add-mt7621-nand-support.patch
index bac031aba3..6e8aec9fc6 100644
--- a/target/linux/ramips/patches-3.10/0507-MTD-add-mt7621-nand-support.patch
+++ b/target/linux/ramips/patches-3.10/0213-MTD-add-mt7621-nand-support.patch
@@ -1,7 +1,7 @@
-From 203189714320fe43b4c0cf953efec9e28963c03b Mon Sep 17 00:00:00 2001
+From 3598d232eb3456fa7aca78e6eeea64210b49c1fc Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
-Date: Mon, 2 Dec 2013 16:23:57 +0100
-Subject: [PATCH 507/507] MTD: add mt7621 nand support
+Date: Fri, 24 Jan 2014 17:01:21 +0100
+Subject: [PATCH 213/215] MTD: add mt7621 nand support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
@@ -14,11 +14,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
drivers/mtd/nand/mtk_nand.c | 2304 +++++++++++++++++++++++++++++++++++
drivers/mtd/nand/mtk_nand.h | 452 +++++++
drivers/mtd/nand/nand_base.c | 6 +-
- drivers/mtd/nand/nand_bbt.c | 19 +
+ drivers/mtd/nand/nand_bbt.c | 41 +
drivers/mtd/nand/nand_def.h | 123 ++
drivers/mtd/nand/nand_device_list.h | 55 +
drivers/mtd/nand/partition.h | 115 ++
- 13 files changed, 4311 insertions(+), 3 deletions(-)
+ 13 files changed, 4333 insertions(+), 3 deletions(-)
create mode 100644 drivers/mtd/nand/bmt.c
create mode 100644 drivers/mtd/nand/bmt.h
create mode 100644 drivers/mtd/nand/dev-nand.c
@@ -4089,10 +4089,32 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
struct nand_chip *chip = mtd->priv;
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
-@@ -1378,6 +1378,25 @@ int nand_isbad_bbt(struct mtd_info *mtd,
+@@ -1378,6 +1378,47 @@ int nand_isbad_bbt(struct mtd_info *mtd,
return 1;
}
++/**
++ * nand_markbad_bbt - [NAND Interface] Mark a block bad in the BBT
++ * @mtd: MTD device structure
++ * @offs: offset of the bad block
++ */
++int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs)
++{
++ struct nand_chip *this = mtd->priv;
++ int block, ret = 0;
++
++ block = (int)(offs >> this->bbt_erase_shift);
++
++ /* Mark bad block in memory */
++ bbt_mark_entry(this, block, BBT_BLOCK_WORN);
++
++ /* Update flash-based bad block table */
++ if (this->bbt_options & NAND_BBT_USE_FLASH)
++ ret = nand_update_bbt(mtd, offs);
++
++ return ret;
++}
++
+void nand_bbt_set(struct mtd_info *mtd, int page, int flag)
+{
+ struct nand_chip *this = mtd->priv;
diff --git a/target/linux/ramips/patches-3.10/0214-usb-add-mt7621-xhci-support.patch b/target/linux/ramips/patches-3.10/0214-usb-add-mt7621-xhci-support.patch
new file mode 100644
index 0000000000..bcac2b43e6
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0214-usb-add-mt7621-xhci-support.patch
@@ -0,0 +1,5768 @@
+From b823088d8782e02cc39c7eb4d834396b83dabe49 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 27 Jan 2014 13:11:01 +0000
+Subject: [PATCH 214/215] usb: add mt7621 xhci support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/usb/core/hub.c | 2 +-
+ drivers/usb/core/port.c | 3 +-
+ drivers/usb/host/Kconfig | 6 +-
+ drivers/usb/host/Makefile | 10 +-
+ drivers/usb/host/mtk-phy-7621.c | 445 +++++
+ drivers/usb/host/mtk-phy-7621.h | 2871 +++++++++++++++++++++++++++++++++
+ drivers/usb/host/mtk-phy-ahb.c | 58 +
+ drivers/usb/host/mtk-phy.c | 102 ++
+ drivers/usb/host/mtk-phy.h | 179 ++
+ drivers/usb/host/pci-quirks.h | 2 +-
+ drivers/usb/host/xhci-dbg.c | 3 +
+ drivers/usb/host/xhci-mem.c | 11 +
+ drivers/usb/host/xhci-mtk-power.c | 115 ++
+ drivers/usb/host/xhci-mtk-power.h | 13 +
+ drivers/usb/host/xhci-mtk-scheduler.c | 608 +++++++
+ drivers/usb/host/xhci-mtk-scheduler.h | 77 +
+ drivers/usb/host/xhci-mtk.c | 265 +++
+ drivers/usb/host/xhci-mtk.h | 120 ++
+ drivers/usb/host/xhci-plat.c | 19 +
+ drivers/usb/host/xhci-ring.c | 109 +-
+ drivers/usb/host/xhci.c | 201 ++-
+ drivers/usb/host/xhci.h | 23 +-
+ 22 files changed, 5229 insertions(+), 13 deletions(-)
+ create mode 100644 drivers/usb/host/mtk-phy-7621.c
+ create mode 100644 drivers/usb/host/mtk-phy-7621.h
+ create mode 100644 drivers/usb/host/mtk-phy-ahb.c
+ create mode 100644 drivers/usb/host/mtk-phy.c
+ create mode 100644 drivers/usb/host/mtk-phy.h
+ create mode 100644 drivers/usb/host/xhci-mtk-power.c
+ create mode 100644 drivers/usb/host/xhci-mtk-power.h
+ create mode 100644 drivers/usb/host/xhci-mtk-scheduler.c
+ create mode 100644 drivers/usb/host/xhci-mtk-scheduler.h
+ create mode 100644 drivers/usb/host/xhci-mtk.c
+ create mode 100644 drivers/usb/host/xhci-mtk.h
+
+--- a/drivers/usb/core/hub.c
++++ b/drivers/usb/core/hub.c
+@@ -1254,7 +1254,7 @@ static void hub_quiesce(struct usb_hub *
+ if (type != HUB_SUSPEND) {
+ /* Disconnect all the children */
+ for (i = 0; i < hdev->maxchild; ++i) {
+- if (hub->ports[i]->child)
++ if (hub->ports[i] && hub->ports[i]->child)
+ usb_disconnect(&hub->ports[i]->child);
+ }
+ }
+--- a/drivers/usb/core/port.c
++++ b/drivers/usb/core/port.c
+@@ -193,6 +193,7 @@ exit:
+ void usb_hub_remove_port_device(struct usb_hub *hub,
+ int port1)
+ {
+- device_unregister(&hub->ports[port1 - 1]->dev);
++ if (hub->ports[port1 - 1])
++ device_unregister(&hub->ports[port1 - 1]->dev);
+ }
+
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -28,7 +28,11 @@ config USB_XHCI_HCD
+ if USB_XHCI_HCD
+
+ config USB_XHCI_PLATFORM
+- tristate
++ bool "xHCI platform"
++
++config USB_MT7621_XHCI_PLATFORM
++ bool "MTK MT7621 xHCI"
++ depends on USB_XHCI_PLATFORM
+
+ config USB_XHCI_HCD_DEBUGGING
+ bool "Debugging for the xHCI host controller"
+--- a/drivers/usb/host/Makefile
++++ b/drivers/usb/host/Makefile
+@@ -13,15 +13,23 @@ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
+
+ xhci-hcd-y := xhci.o xhci-mem.o
+ xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
++ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
+ xhci-hcd-$(CONFIG_PCI) += xhci-pci.o
++endif
++
++ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
++xhci-hcd-y += mtk-phy.o xhci-mtk-scheduler.o xhci-mtk-power.o xhci-mtk.o mtk-phy-7621.o mtk-phy-ahb.o
++endif
+
+ ifneq ($(CONFIG_USB_XHCI_PLATFORM), )
+- xhci-hcd-y += xhci-plat.o
++xhci-hcd-y += xhci-plat.o
+ endif
+
+ obj-$(CONFIG_USB_WHCI_HCD) += whci/
+
++ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
+ obj-$(CONFIG_PCI) += pci-quirks.o
++endif
+
+ obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
+ obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
+--- /dev/null
++++ b/drivers/usb/host/mtk-phy-7621.c
+@@ -0,0 +1,445 @@
++#include "mtk-phy.h"
++
++#ifdef CONFIG_PROJECT_7621
++#include "mtk-phy-7621.h"
++
++//not used on SoC
++PHY_INT32 phy_init(struct u3phy_info *info){
++ return PHY_TRUE;
++}
++
++//not used on SoC
++PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
++ return PHY_TRUE;
++}
++
++//--------------------------------------------------------
++// Function : fgEyeScanHelper_CheckPtInRegion()
++// Description : Check if the test point is in a rectangle region.
++// If it is in the rectangle, also check if this point
++// is on the multiple of deltaX and deltaY.
++// Parameter : strucScanRegion * prEye - the region
++// BYTE bX
++// BYTE bY
++// Return : BYTE - TRUE : This point needs to be tested
++// FALSE: This point will be omitted
++// Note : First check within the rectangle.
++// Secondly, use modulous to check if the point will be tested.
++//--------------------------------------------------------
++static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
++{
++ PHY_INT8 fgValid = true;
++
++
++ /// Be careful, the axis origin is on the TOP-LEFT corner.
++ /// Therefore the top-left point has the minimum X and Y
++ /// Botton-right point is the maximum X and Y
++ if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
++ && (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
++ {
++ // With the region, now check whether or not the input test point is
++ // on the multiples of X and Y
++ // Do not have to worry about negative value, because we have already
++ // check the input bX, and bY is within the region.
++ if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
++ || ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
++ {
++ // if the division will have remainder, that means
++ // the input test point is on the multiples of X and Y
++ fgValid = false;
++ }
++ else
++ {
++ }
++ }
++ else
++ {
++
++ fgValid = false;
++ }
++ return fgValid;
++}
++
++//--------------------------------------------------------
++// Function : EyeScanHelper_RunTest()
++// Description : Enable the test, and wait til it is completed
++// Parameter : None
++// Return : None
++// Note : None
++//--------------------------------------------------------
++static void EyeScanHelper_RunTest(struct u3phy_info *info)
++{
++ DRV_UDELAY(100);
++ // Disable the test
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0); //RG_SSUSB_RX_EYE_CNT_EN = 0
++ DRV_UDELAY(100);
++ // Run the test
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1); //RG_SSUSB_RX_EYE_CNT_EN = 1
++ DRV_UDELAY(100);
++ // Wait til it's done
++ //RGS_SSUSB_RX_EYE_CNT_RDY
++ while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
++ , RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
++}
++
++//--------------------------------------------------------
++// Function : fgEyeScanHelper_CalNextPoint()
++// Description : Calcualte the test point for the measurement
++// Parameter : None
++// Return : BOOL - TRUE : the next point is within the
++// boundaryof HW limit
++// FALSE: the next point is out of the HW limit
++// Note : The next point is obtained by calculating
++// from the bottom left of the region rectangle
++// and then scanning up until it reaches the upper
++// limit. At this time, the x will increment, and
++// start scanning downwards until the y hits the
++// zero.
++//--------------------------------------------------------
++static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
++{
++ if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
++ || ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
++ )
++ {
++ /// Reaches the limit of Y axis
++ /// Increment X
++ _bXcurr++;
++ _fgXChged = true;
++ _eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
++
++ if (_bXcurr > MAX_X)
++ {
++ return false;
++ }
++ }
++ else
++ {
++ _bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
++ _fgXChged = false;
++ }
++ return PHY_TRUE;
++}
++
++PHY_INT32 eyescan_init(struct u3phy_info *info){
++ //initial PHY setting
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
++ , RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
++ , RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
++ , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
++ , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
++ return PHY_TRUE;
++}
++
++PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
++ , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
++ PHY_INT32 cOfst = 0;
++ PHY_UINT8 bIdxX = 0;
++ PHY_UINT8 bIdxY = 0;
++ //PHY_INT8 bCnt = 0;
++ PHY_UINT8 bIdxCycCnt = 0;
++ PHY_INT8 fgValid;
++ PHY_INT8 cX;
++ PHY_INT8 cY;
++ PHY_UINT8 bExtendCnt;
++ PHY_INT8 isContinue;
++ //PHY_INT8 isBreak;
++ PHY_UINT32 wErr0 = 0, wErr1 = 0;
++ //PHY_UINT32 temp;
++
++ PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
++ PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
++
++ _rEye1.bX_tl = x_t1;
++ _rEye1.bY_tl = y_t1;
++ _rEye1.bX_br = x_br;
++ _rEye1.bY_br = y_br;
++ _rEye1.bDeltaX = delta_x;
++ _rEye1.bDeltaY = delta_y;
++
++ _rEye2.bX_tl = x_t1;
++ _rEye2.bY_tl = y_t1;
++ _rEye2.bX_br = x_br;
++ _rEye2.bY_br = y_br;
++ _rEye2.bDeltaX = delta_x;
++ _rEye2.bDeltaY = delta_y;
++
++ _rTestCycle.wEyeCnt = eye_cnt;
++ _rTestCycle.bNumOfEyeCnt = num_cnt;
++ _rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
++ _rTestCycle.bPICalEn = PI_cal_en;
++
++ _bXcurr = 0;
++ _bYcurr = 0;
++ _eScanDir = SCAN_DN;
++ _fgXChged = false;
++
++ printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
++ eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
++ x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);
++
++ //force SIGDET to OFF
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
++ , RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1); //RG_SSUSB_RX_SIGDET_SEL = 1
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
++ , RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0); //RG_SSUSB_RX_SIGDET_EN = 0
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
++ , RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0); //RG_SSUSB_RX_SIGDET = 0
++
++ // RX_TRI_DET_EN to Disable
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
++ , RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0); //RG_SSUSB_RX_TRI_DET_EN = 0
++
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0); //RG_SSUSB_RX_EYE_XOFFSET = 0
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0); //RG_SSUSB_RX_EYE0_Y = 0
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0); //RG_SSUSB_RX_EYE1_Y = 0
++
++
++ if (PI_cal_en){
++ // PI Calibration
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
++ , RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
++ , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
++ , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
++
++ DRV_UDELAY(20);
++
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
++ , RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
++ _bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
++ , RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO); //read RGS_SSUSB_RX_PILPO
++
++ printk(KERN_ERR "PI result: %d\n", _bPIResult);
++ }
++ // Read Initial DAC
++ // Set CYCLE
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
++ ,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt); //RG_SSUSB_RX_EYE_CNT
++
++ // Eye Monitor Feature
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
++ , RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff); //RG_SSUSB_RX_EYE_MASK = 0x3ff
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
++
++ // Move X,Y to the top-left corner
++ for (cOfst = 0; cOfst >= -64; cOfst--)
++ {
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ ,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
++ }
++ for (cOfst = 0; cOfst < 64; cOfst++)
++ {
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst); //RG_SSUSB_RX_EYE0_Y
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst); //RG_SSUSB_RX_EYE1_Y
++ }
++ //ClearErrorResult
++ for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
++ for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
++ {
++ for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
++ pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
++ pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
++ }
++ }
++ }
++ isContinue = true;
++ while(isContinue){
++ //printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
++ // The point is within the boundary, then let's check if it is within
++ // the testing region.
++ // The point is only test-able if one of the eye region
++ // includes this point.
++ fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
++ || fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
++ // Translate bX and bY to 2's complement from where the origin was on the
++ // top left corner.
++ // 0x40 and 0x3F needs a bit of thinking!!!! >"<
++ cX = (_bXcurr ^ 0x40);
++ cY = (_bYcurr ^ 0x3F);
++
++ // Set X if necessary
++ if (_fgXChged == true)
++ {
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX); //RG_SSUSB_RX_EYE_XOFFSET
++ }
++ // Set Y
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY); //RG_SSUSB_RX_EYE0_Y
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY); //RG_SSUSB_RX_EYE1_Y
++
++ /// Test this point!
++ if (fgValid){
++ for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
++ {
++ //run test
++ EyeScanHelper_RunTest(info);
++ }
++ for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
++ {
++ EyeScanHelper_RunTest(info);
++ wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
++ , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
++ wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
++ , RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
++
++ pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
++ pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr] = wErr1;
++
++ //EyeScanHelper_GetResult(&_rRes.pwErrCnt0[bCnt], &_rRes.pwErrCnt1[bCnt]);
++// printk(KERN_ERR "cnt[%d] cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n"
++// , bExtendCnt, _bXcurr, _bYcurr, cX, cY, pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr], pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr]);
++ }
++ //printk(KERN_ERR "cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n", _bXcurr, _bYcurr, cX, cY, pwErrCnt0[0][_bXcurr][_bYcurr], pwErrCnt1[0][_bXcurr][_bYcurr]);
++ }
++ else{
++
++ }
++ if (fgEyeScanHelper_CalNextPoint() == false){
++#if 0
++ printk(KERN_ERR "Xcurr [0x%x] Ycurr [0x%x]\n", _bXcurr, _bYcurr);
++ printk(KERN_ERR "XcurrREG [0x%x] YcurrREG [0x%x]\n", cX, cY);
++#endif
++ printk(KERN_ERR "end of eye scan\n");
++ isContinue = false;
++ }
++ }
++ printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
++ , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
++ , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
++
++ // Move X,Y to the top-left corner
++ for (cOfst = 63; cOfst >= 0; cOfst--)
++ {
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
++ }
++ for (cOfst = 63; cOfst >= 0; cOfst--)
++ {
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);
++ U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
++ , RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);
++
++ }
++ printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
++ , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
++ , U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
++
++ printk(KERN_ERR "PI result: %d\n", _bPIResult);
++ printk(KERN_ERR "pwErrCnt0 addr: 0x%x\n", (PHY_UINT32)pwErrCnt0);
++ printk(KERN_ERR "pwErrCnt1 addr: 0x%x\n", (PHY_UINT32)pwErrCnt1);
++
++ return PHY_TRUE;
++}
++
++//not used on SoC
++PHY_INT32 u2_save_cur_en(struct u3phy_info *info){
++ return PHY_TRUE;
++}
++
++//not used on SoC
++PHY_INT32 u2_save_cur_re(struct u3phy_info *info){
++ return PHY_TRUE;
++}
++
++PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info){
++ PHY_INT32 i=0;
++ //PHY_INT32 j=0;
++ //PHY_INT8 u1SrCalVal = 0;
++ //PHY_INT8 u1Reg_addr_HSTX_SRCAL_EN;
++ PHY_INT32 fgRet = 0;
++ PHY_INT32 u4FmOut = 0;
++ PHY_INT32 u4Tmp = 0;
++ //PHY_INT32 temp;
++
++ // => RG_USB20_HSTX_SRCAL_EN = 1
++ // enable HS TX SR calibration
++ U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
++ , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0x1);
++ DRV_MSLEEP(1);
++
++ // => RG_FRCK_EN = 1
++ // Enable free run clock
++ U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
++ , RG_FRCK_EN_OFST, RG_FRCK_EN, 1);
++
++ // MT6290 HS signal quality patch
++ // => RG_CYCLECNT = 400
++ // Setting cyclecnt =400
++ U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
++ , RG_CYCLECNT_OFST, RG_CYCLECNT, 0x400);
++
++ // => RG_FREQDET_EN = 1
++ // Enable frequency meter
++ U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
++ , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0x1);
++
++ // wait for FM detection done, set 10ms timeout
++ for(i=0; i<10; i++){
++ // => u4FmOut = USB_FM_OUT
++ // read FM_OUT
++ u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr0));
++ printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
++
++ // check if FM detection done
++ if (u4FmOut != 0)
++ {
++ fgRet = 0;
++ printk("FM detection done! loop = %d\n", i);
++
++ break;
++ }
++
++ fgRet = 1;
++ DRV_MSLEEP(1);
++ }
++ // => RG_FREQDET_EN = 0
++ // disable frequency meter
++ U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
++ , RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0);
++
++ // => RG_FRCK_EN = 0
++ // disable free run clock
++ U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
++ , RG_FRCK_EN_OFST, RG_FRCK_EN, 0);
++
++ // => RG_USB20_HSTX_SRCAL_EN = 0
++ // disable HS TX SR calibration
++ U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
++ , RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0);
++ DRV_MSLEEP(1);
++
++ if(u4FmOut == 0){
++ U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
++ , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, 0x4);
++
++ fgRet = 1;
++ }
++ else{
++ // set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
++ u4Tmp = (((1024 * 25 * U2_SR_COEF_7621) / u4FmOut) + 500) / 1000;
++ printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
++ U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
++ , RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, u4Tmp);
++ }
++ return fgRet;
++}
++
++#endif
+--- /dev/null
++++ b/drivers/usb/host/mtk-phy-7621.h
+@@ -0,0 +1,2871 @@
++#ifdef CONFIG_PROJECT_7621
++#ifndef __MTK_PHY_7621_H
++#define __MTK_PHY_7621_H
++
++#define U2_SR_COEF_7621 28
++
++///////////////////////////////////////////////////////////////////////////////
++
++struct u2phy_reg {
++ //0x0
++ PHY_LE32 u2phyac0;
++ PHY_LE32 u2phyac1;
++ PHY_LE32 u2phyac2;
++ PHY_LE32 reserve0;
++ //0x10
++ PHY_LE32 u2phyacr0;
++ PHY_LE32 u2phyacr1;
++ PHY_LE32 u2phyacr2;
++ PHY_LE32 u2phyacr3;
++ //0x20
++ PHY_LE32 u2phyacr4;
++ PHY_LE32 u2phyamon0;
++ PHY_LE32 reserve1[2];
++ //0x30~0x50
++ PHY_LE32 reserve2[12];
++ //0x60
++ PHY_LE32 u2phydcr0;
++ PHY_LE32 u2phydcr1;
++ PHY_LE32 u2phydtm0;
++ PHY_LE32 u2phydtm1;
++ //0x70
++ PHY_LE32 u2phydmon0;
++ PHY_LE32 u2phydmon1;
++ PHY_LE32 u2phydmon2;
++ PHY_LE32 u2phydmon3;
++ //0x80
++ PHY_LE32 u2phybc12c;
++ PHY_LE32 u2phybc12c1;
++ PHY_LE32 reserve3[2];
++ //0x90~0xe0
++ PHY_LE32 reserve4[24];
++ //0xf0
++ PHY_LE32 reserve6[3];
++ PHY_LE32 regfcom;
++};
++
++//U3D_U2PHYAC0
++#define RG_USB20_USBPLL_DIVEN (0x7<<28) //30:28
++#define RG_USB20_USBPLL_CKCTRL (0x3<<26) //27:26
++#define RG_USB20_USBPLL_PREDIV (0x3<<24) //25:24
++#define RG_USB20_USBPLL_FORCE_ON (0x1<<23) //23:23
++#define RG_USB20_USBPLL_FBDIV (0x7f<<16) //22:16
++#define RG_USB20_REF_EN (0x1<<15) //15:15
++#define RG_USB20_INTR_EN (0x1<<14) //14:14
++#define RG_USB20_BG_TRIM (0xf<<8) //11:8
++#define RG_USB20_BG_RBSEL (0x3<<6) //7:6
++#define RG_USB20_BG_RASEL (0x3<<4) //5:4
++#define RG_USB20_BGR_DIV (0x3<<2) //3:2
++#define RG_SIFSLV_CHP_EN (0x1<<1) //1:1
++#define RG_SIFSLV_BGR_EN (0x1<<0) //0:0
++
++//U3D_U2PHYAC1
++#define RG_USB20_VRT_VREF_SEL (0x7<<28) //30:28
++#define RG_USB20_TERM_VREF_SEL (0x7<<24) //26:24
++#define RG_USB20_MPX_SEL (0xff<<16) //23:16
++#define RG_USB20_MPX_OUT_SEL (0x3<<12) //13:12
++#define RG_USB20_TX_PH_ROT_SEL (0x7<<8) //10:8
++#define RG_USB20_USBPLL_ACCEN (0x1<<3) //3:3
++#define RG_USB20_USBPLL_LF (0x1<<2) //2:2
++#define RG_USB20_USBPLL_BR (0x1<<1) //1:1
++#define RG_USB20_USBPLL_BP (0x1<<0) //0:0
++
++//U3D_U2PHYAC2
++#define RG_SIFSLV_MAC_BANDGAP_EN (0x1<<17) //17:17
++#define RG_SIFSLV_MAC_CHOPPER_EN (0x1<<16) //16:16
++#define RG_USB20_CLKREF_REV (0xff<<0) //7:0
++
++//U3D_U2PHYACR0
++#define RG_USB20_ICUSB_EN (0x1<<24) //24:24
++#define RG_USB20_HSTX_SRCAL_EN (0x1<<23) //23:23
++#define RG_USB20_HSTX_SRCTRL (0x7<<16) //18:16
++#define RG_USB20_LS_CR (0x7<<12) //14:12
++#define RG_USB20_FS_CR (0x7<<8) //10:8
++#define RG_USB20_LS_SR (0x7<<4) //6:4
++#define RG_USB20_FS_SR (0x7<<0) //2:0
++
++//U3D_U2PHYACR1
++#define RG_USB20_INIT_SQ_EN_DG (0x3<<28) //29:28
++#define RG_USB20_SQD (0x3<<24) //25:24
++#define RG_USB20_HSTX_TMODE_SEL (0x3<<20) //21:20
++#define RG_USB20_HSTX_TMODE_EN (0x1<<19) //19:19
++#define RG_USB20_PHYD_MONEN (0x1<<18) //18:18
++#define RG_USB20_INLPBK_EN (0x1<<17) //17:17
++#define RG_USB20_CHIRP_EN (0x1<<16) //16:16
++#define RG_USB20_DM_ABIST_SOURCE_EN (0x1<<15) //15:15
++#define RG_USB20_DM_ABIST_SELE (0xf<<8) //11:8
++#define RG_USB20_DP_ABIST_SOURCE_EN (0x1<<7) //7:7
++#define RG_USB20_DP_ABIST_SELE (0xf<<0) //3:0
++
++//U3D_U2PHYACR2
++#define RG_USB20_OTG_ABIST_SELE (0x7<<29) //31:29
++#define RG_USB20_OTG_ABIST_EN (0x1<<28) //28:28
++#define RG_USB20_OTG_VBUSCMP_EN (0x1<<27) //27:27
++#define RG_USB20_OTG_VBUSTH (0x7<<24) //26:24
++#define RG_USB20_DISC_FIT_EN (0x1<<22) //22:22
++#define RG_USB20_DISCD (0x3<<20) //21:20
++#define RG_USB20_DISCTH (0xf<<16) //19:16
++#define RG_USB20_SQCAL_EN (0x1<<15) //15:15
++#define RG_USB20_SQCAL (0xf<<8) //11:8
++#define RG_USB20_SQTH (0xf<<0) //3:0
++
++//U3D_U2PHYACR3
++#define RG_USB20_HSTX_DBIST (0xf<<28) //31:28
++#define RG_USB20_HSTX_BIST_EN (0x1<<26) //26:26
++#define RG_USB20_HSTX_I_EN_MODE (0x3<<24) //25:24
++#define RG_USB20_HSRX_TMODE_EN (0x1<<23) //23:23
++#define RG_USB20_HSRX_BIAS_EN_SEL (0x3<<20) //21:20
++#define RG_USB20_USB11_TMODE_EN (0x1<<19) //19:19
++#define RG_USB20_TMODE_FS_LS_TX_EN (0x1<<18) //18:18
++#define RG_USB20_TMODE_FS_LS_RCV_EN (0x1<<17) //17:17
++#define RG_USB20_TMODE_FS_LS_MODE (0x1<<16) //16:16
++#define RG_USB20_HS_TERM_EN_MODE (0x3<<13) //14:13
++#define RG_USB20_PUPD_BIST_EN (0x1<<12) //12:12
++#define RG_USB20_EN_PU_DM (0x1<<11) //11:11
++#define RG_USB20_EN_PD_DM (0x1<<10) //10:10
++#define RG_USB20_EN_PU_DP (0x1<<9) //9:9
++#define RG_USB20_EN_PD_DP (0x1<<8) //8:8
++#define RG_USB20_PHY_REV (0xff<<0) //7:0
++
++//U3D_U2PHYACR4
++#define RG_USB20_DP_100K_MODE (0x1<<18) //18:18
++#define RG_USB20_DM_100K_EN (0x1<<17) //17:17
++#define USB20_DP_100K_EN (0x1<<16) //16:16
++#define USB20_GPIO_DM_I (0x1<<15) //15:15
++#define USB20_GPIO_DP_I (0x1<<14) //14:14
++#define USB20_GPIO_DM_OE (0x1<<13) //13:13
++#define USB20_GPIO_DP_OE (0x1<<12) //12:12
++#define RG_USB20_GPIO_CTL (0x1<<9) //9:9
++#define USB20_GPIO_MODE (0x1<<8) //8:8
++#define RG_USB20_TX_BIAS_EN (0x1<<5) //5:5
++#define RG_USB20_TX_VCMPDN_EN (0x1<<4) //4:4
++#define RG_USB20_HS_SQ_EN_MODE (0x3<<2) //3:2
++#define RG_USB20_HS_RCV_EN_MODE (0x3<<0) //1:0
++
++//U3D_U2PHYAMON0
++#define RGO_USB20_GPIO_DM_O (0x1<<1) //1:1
++#define RGO_USB20_GPIO_DP_O (0x1<<0) //0:0
++
++//U3D_U2PHYDCR0
++#define RG_USB20_CDR_TST (0x3<<30) //31:30
++#define RG_USB20_GATED_ENB (0x1<<29) //29:29
++#define RG_USB20_TESTMODE (0x3<<26) //27:26
++#define RG_USB20_PLL_STABLE (0x1<<25) //25:25
++#define RG_USB20_PLL_FORCE_ON (0x1<<24) //24:24
++#define RG_USB20_PHYD_RESERVE (0xffff<<8) //23:8
++#define RG_USB20_EBTHRLD (0x1<<7) //7:7
++#define RG_USB20_EARLY_HSTX_I (0x1<<6) //6:6
++#define RG_USB20_TX_TST (0x1<<5) //5:5
++#define RG_USB20_NEGEDGE_ENB (0x1<<4) //4:4
++#define RG_USB20_CDR_FILT (0xf<<0) //3:0
++
++//U3D_U2PHYDCR1
++#define RG_USB20_PROBE_SEL (0xff<<24) //31:24
++#define RG_USB20_DRVVBUS (0x1<<23) //23:23
++#define RG_DEBUG_EN (0x1<<22) //22:22
++#define RG_USB20_OTG_PROBE (0x3<<20) //21:20
++#define RG_USB20_SW_PLLMODE (0x3<<18) //19:18
++#define RG_USB20_BERTH (0x3<<16) //17:16
++#define RG_USB20_LBMODE (0x3<<13) //14:13
++#define RG_USB20_FORCE_TAP (0x1<<12) //12:12
++#define RG_USB20_TAPSEL (0xfff<<0) //11:0
++
++//U3D_U2PHYDTM0
++#define RG_UART_MODE (0x3<<30) //31:30
++#define FORCE_UART_I (0x1<<29) //29:29
++#define FORCE_UART_BIAS_EN (0x1<<28) //28:28
++#define FORCE_UART_TX_OE (0x1<<27) //27:27
++#define FORCE_UART_EN (0x1<<26) //26:26
++#define FORCE_USB_CLKEN (0x1<<25) //25:25
++#define FORCE_DRVVBUS (0x1<<24) //24:24
++#define FORCE_DATAIN (0x1<<23) //23:23
++#define FORCE_TXVALID (0x1<<22) //22:22
++#define FORCE_DM_PULLDOWN (0x1<<21) //21:21
++#define FORCE_DP_PULLDOWN (0x1<<20) //20:20
++#define FORCE_XCVRSEL (0x1<<19) //19:19
++#define FORCE_SUSPENDM (0x1<<18) //18:18
++#define FORCE_TERMSEL (0x1<<17) //17:17
++#define FORCE_OPMODE (0x1<<16) //16:16
++#define UTMI_MUXSEL (0x1<<15) //15:15
++#define RG_RESET (0x1<<14) //14:14
++#define RG_DATAIN (0xf<<10) //13:10
++#define RG_TXVALIDH (0x1<<9) //9:9
++#define RG_TXVALID (0x1<<8) //8:8
++#define RG_DMPULLDOWN (0x1<<7) //7:7
++#define RG_DPPULLDOWN (0x1<<6) //6:6
++#define RG_XCVRSEL (0x3<<4) //5:4
++#define RG_SUSPENDM (0x1<<3) //3:3
++#define RG_TERMSEL (0x1<<2) //2:2
++#define RG_OPMODE (0x3<<0) //1:0
++
++//U3D_U2PHYDTM1
++#define RG_USB20_PRBS7_EN (0x1<<31) //31:31
++#define RG_USB20_PRBS7_BITCNT (0x3f<<24) //29:24
++#define RG_USB20_CLK48M_EN (0x1<<23) //23:23
++#define RG_USB20_CLK60M_EN (0x1<<22) //22:22
++#define RG_UART_I (0x1<<19) //19:19
++#define RG_UART_BIAS_EN (0x1<<18) //18:18
++#define RG_UART_TX_OE (0x1<<17) //17:17
++#define RG_UART_EN (0x1<<16) //16:16
++#define FORCE_VBUSVALID (0x1<<13) //13:13
++#define FORCE_SESSEND (0x1<<12) //12:12
++#define FORCE_BVALID (0x1<<11) //11:11
++#define FORCE_AVALID (0x1<<10) //10:10
++#define FORCE_IDDIG (0x1<<9) //9:9
++#define FORCE_IDPULLUP (0x1<<8) //8:8
++#define RG_VBUSVALID (0x1<<5) //5:5
++#define RG_SESSEND (0x1<<4) //4:4
++#define RG_BVALID (0x1<<3) //3:3
++#define RG_AVALID (0x1<<2) //2:2
++#define RG_IDDIG (0x1<<1) //1:1
++#define RG_IDPULLUP (0x1<<0) //0:0
++
++//U3D_U2PHYDMON0
++#define RG_USB20_PRBS7_BERTH (0xff<<0) //7:0
++
++//U3D_U2PHYDMON1
++#define USB20_UART_O (0x1<<31) //31:31
++#define RGO_USB20_LB_PASS (0x1<<30) //30:30
++#define RGO_USB20_LB_DONE (0x1<<29) //29:29
++#define AD_USB20_BVALID (0x1<<28) //28:28
++#define USB20_IDDIG (0x1<<27) //27:27
++#define AD_USB20_VBUSVALID (0x1<<26) //26:26
++#define AD_USB20_SESSEND (0x1<<25) //25:25
++#define AD_USB20_AVALID (0x1<<24) //24:24
++#define USB20_LINE_STATE (0x3<<22) //23:22
++#define USB20_HST_DISCON (0x1<<21) //21:21
++#define USB20_TX_READY (0x1<<20) //20:20
++#define USB20_RX_ERROR (0x1<<19) //19:19
++#define USB20_RX_ACTIVE (0x1<<18) //18:18
++#define USB20_RX_VALIDH (0x1<<17) //17:17
++#define USB20_RX_VALID (0x1<<16) //16:16
++#define USB20_DATA_OUT (0xffff<<0) //15:0
++
++//U3D_U2PHYDMON2
++#define RGO_TXVALID_CNT (0xff<<24) //31:24
++#define RGO_RXACTIVE_CNT (0xff<<16) //23:16
++#define RGO_USB20_LB_BERCNT (0xff<<8) //15:8
++#define USB20_PROBE_OUT (0xff<<0) //7:0
++
++//U3D_U2PHYDMON3
++#define RGO_USB20_PRBS7_ERRCNT (0xffff<<16) //31:16
++#define RGO_USB20_PRBS7_DONE (0x1<<3) //3:3
++#define RGO_USB20_PRBS7_LOCK (0x1<<2) //2:2
++#define RGO_USB20_PRBS7_PASS (0x1<<1) //1:1
++#define RGO_USB20_PRBS7_PASSTH (0x1<<0) //0:0
++
++//U3D_U2PHYBC12C
++#define RG_SIFSLV_CHGDT_DEGLCH_CNT (0xf<<28) //31:28
++#define RG_SIFSLV_CHGDT_CTRL_CNT (0xf<<24) //27:24
++#define RG_SIFSLV_CHGDT_FORCE_MODE (0x1<<16) //16:16
++#define RG_CHGDT_ISRC_LEV (0x3<<14) //15:14
++#define RG_CHGDT_VDATSRC (0x1<<13) //13:13
++#define RG_CHGDT_BGVREF_SEL (0x7<<10) //12:10
++#define RG_CHGDT_RDVREF_SEL (0x3<<8) //9:8
++#define RG_CHGDT_ISRC_DP (0x1<<7) //7:7
++#define RG_SIFSLV_CHGDT_OPOUT_DM (0x1<<6) //6:6
++#define RG_CHGDT_VDAT_DM (0x1<<5) //5:5
++#define RG_CHGDT_OPOUT_DP (0x1<<4) //4:4
++#define RG_SIFSLV_CHGDT_VDAT_DP (0x1<<3) //3:3
++#define RG_SIFSLV_CHGDT_COMP_EN (0x1<<2) //2:2
++#define RG_SIFSLV_CHGDT_OPDRV_EN (0x1<<1) //1:1
++#define RG_CHGDT_EN (0x1<<0) //0:0
++
++//U3D_U2PHYBC12C1
++#define RG_CHGDT_REV (0xff<<0) //7:0
++
++//U3D_REGFCOM
++#define RG_PAGE (0xff<<24) //31:24
++#define I2C_MODE (0x1<<16) //16:16
++
++
++/* OFFSET */
++
++//U3D_U2PHYAC0
++#define RG_USB20_USBPLL_DIVEN_OFST (28)
++#define RG_USB20_USBPLL_CKCTRL_OFST (26)
++#define RG_USB20_USBPLL_PREDIV_OFST (24)
++#define RG_USB20_USBPLL_FORCE_ON_OFST (23)
++#define RG_USB20_USBPLL_FBDIV_OFST (16)
++#define RG_USB20_REF_EN_OFST (15)
++#define RG_USB20_INTR_EN_OFST (14)
++#define RG_USB20_BG_TRIM_OFST (8)
++#define RG_USB20_BG_RBSEL_OFST (6)
++#define RG_USB20_BG_RASEL_OFST (4)
++#define RG_USB20_BGR_DIV_OFST (2)
++#define RG_SIFSLV_CHP_EN_OFST (1)
++#define RG_SIFSLV_BGR_EN_OFST (0)
++
++//U3D_U2PHYAC1
++#define RG_USB20_VRT_VREF_SEL_OFST (28)
++#define RG_USB20_TERM_VREF_SEL_OFST (24)
++#define RG_USB20_MPX_SEL_OFST (16)
++#define RG_USB20_MPX_OUT_SEL_OFST (12)
++#define RG_USB20_TX_PH_ROT_SEL_OFST (8)
++#define RG_USB20_USBPLL_ACCEN_OFST (3)
++#define RG_USB20_USBPLL_LF_OFST (2)
++#define RG_USB20_USBPLL_BR_OFST (1)
++#define RG_USB20_USBPLL_BP_OFST (0)
++
++//U3D_U2PHYAC2
++#define RG_SIFSLV_MAC_BANDGAP_EN_OFST (17)
++#define RG_SIFSLV_MAC_CHOPPER_EN_OFST (16)
++#define RG_USB20_CLKREF_REV_OFST (0)
++
++//U3D_U2PHYACR0
++#define RG_USB20_ICUSB_EN_OFST (24)
++#define RG_USB20_HSTX_SRCAL_EN_OFST (23)
++#define RG_USB20_HSTX_SRCTRL_OFST (16)
++#define RG_USB20_LS_CR_OFST (12)
++#define RG_USB20_FS_CR_OFST (8)
++#define RG_USB20_LS_SR_OFST (4)
++#define RG_USB20_FS_SR_OFST (0)
++
++//U3D_U2PHYACR1
++#define RG_USB20_INIT_SQ_EN_DG_OFST (28)
++#define RG_USB20_SQD_OFST (24)
++#define RG_USB20_HSTX_TMODE_SEL_OFST (20)
++#define RG_USB20_HSTX_TMODE_EN_OFST (19)
++#define RG_USB20_PHYD_MONEN_OFST (18)
++#define RG_USB20_INLPBK_EN_OFST (17)
++#define RG_USB20_CHIRP_EN_OFST (16)
++#define RG_USB20_DM_ABIST_SOURCE_EN_OFST (15)
++#define RG_USB20_DM_ABIST_SELE_OFST (8)
++#define RG_USB20_DP_ABIST_SOURCE_EN_OFST (7)
++#define RG_USB20_DP_ABIST_SELE_OFST (0)
++
++//U3D_U2PHYACR2
++#define RG_USB20_OTG_ABIST_SELE_OFST (29)
++#define RG_USB20_OTG_ABIST_EN_OFST (28)
++#define RG_USB20_OTG_VBUSCMP_EN_OFST (27)
++#define RG_USB20_OTG_VBUSTH_OFST (24)
++#define RG_USB20_DISC_FIT_EN_OFST (22)
++#define RG_USB20_DISCD_OFST (20)
++#define RG_USB20_DISCTH_OFST (16)
++#define RG_USB20_SQCAL_EN_OFST (15)
++#define RG_USB20_SQCAL_OFST (8)
++#define RG_USB20_SQTH_OFST (0)
++
++//U3D_U2PHYACR3
++#define RG_USB20_HSTX_DBIST_OFST (28)
++#define RG_USB20_HSTX_BIST_EN_OFST (26)
++#define RG_USB20_HSTX_I_EN_MODE_OFST (24)
++#define RG_USB20_HSRX_TMODE_EN_OFST (23)
++#define RG_USB20_HSRX_BIAS_EN_SEL_OFST (20)
++#define RG_USB20_USB11_TMODE_EN_OFST (19)
++#define RG_USB20_TMODE_FS_LS_TX_EN_OFST (18)
++#define RG_USB20_TMODE_FS_LS_RCV_EN_OFST (17)
++#define RG_USB20_TMODE_FS_LS_MODE_OFST (16)
++#define RG_USB20_HS_TERM_EN_MODE_OFST (13)
++#define RG_USB20_PUPD_BIST_EN_OFST (12)
++#define RG_USB20_EN_PU_DM_OFST (11)
++#define RG_USB20_EN_PD_DM_OFST (10)
++#define RG_USB20_EN_PU_DP_OFST (9)
++#define RG_USB20_EN_PD_DP_OFST (8)
++#define RG_USB20_PHY_REV_OFST (0)
++
++//U3D_U2PHYACR4
++#define RG_USB20_DP_100K_MODE_OFST (18)
++#define RG_USB20_DM_100K_EN_OFST (17)
++#define USB20_DP_100K_EN_OFST (16)
++#define USB20_GPIO_DM_I_OFST (15)
++#define USB20_GPIO_DP_I_OFST (14)
++#define USB20_GPIO_DM_OE_OFST (13)
++#define USB20_GPIO_DP_OE_OFST (12)
++#define RG_USB20_GPIO_CTL_OFST (9)
++#define USB20_GPIO_MODE_OFST (8)
++#define RG_USB20_TX_BIAS_EN_OFST (5)
++#define RG_USB20_TX_VCMPDN_EN_OFST (4)
++#define RG_USB20_HS_SQ_EN_MODE_OFST (2)
++#define RG_USB20_HS_RCV_EN_MODE_OFST (0)
++
++//U3D_U2PHYAMON0
++#define RGO_USB20_GPIO_DM_O_OFST (1)
++#define RGO_USB20_GPIO_DP_O_OFST (0)
++
++//U3D_U2PHYDCR0
++#define RG_USB20_CDR_TST_OFST (30)
++#define RG_USB20_GATED_ENB_OFST (29)
++#define RG_USB20_TESTMODE_OFST (26)
++#define RG_USB20_PLL_STABLE_OFST (25)
++#define RG_USB20_PLL_FORCE_ON_OFST (24)
++#define RG_USB20_PHYD_RESERVE_OFST (8)
++#define RG_USB20_EBTHRLD_OFST (7)
++#define RG_USB20_EARLY_HSTX_I_OFST (6)
++#define RG_USB20_TX_TST_OFST (5)
++#define RG_USB20_NEGEDGE_ENB_OFST (4)
++#define RG_USB20_CDR_FILT_OFST (0)
++
++//U3D_U2PHYDCR1
++#define RG_USB20_PROBE_SEL_OFST (24)
++#define RG_USB20_DRVVBUS_OFST (23)
++#define RG_DEBUG_EN_OFST (22)
++#define RG_USB20_OTG_PROBE_OFST (20)
++#define RG_USB20_SW_PLLMODE_OFST (18)
++#define RG_USB20_BERTH_OFST (16)
++#define RG_USB20_LBMODE_OFST (13)
++#define RG_USB20_FORCE_TAP_OFST (12)
++#define RG_USB20_TAPSEL_OFST (0)
++
++//U3D_U2PHYDTM0
++#define RG_UART_MODE_OFST (30)
++#define FORCE_UART_I_OFST (29)
++#define FORCE_UART_BIAS_EN_OFST (28)
++#define FORCE_UART_TX_OE_OFST (27)
++#define FORCE_UART_EN_OFST (26)
++#define FORCE_USB_CLKEN_OFST (25)
++#define FORCE_DRVVBUS_OFST (24)
++#define FORCE_DATAIN_OFST (23)
++#define FORCE_TXVALID_OFST (22)
++#define FORCE_DM_PULLDOWN_OFST (21)
++#define FORCE_DP_PULLDOWN_OFST (20)
++#define FORCE_XCVRSEL_OFST (19)
++#define FORCE_SUSPENDM_OFST (18)
++#define FORCE_TERMSEL_OFST (17)
++#define FORCE_OPMODE_OFST (16)
++#define UTMI_MUXSEL_OFST (15)
++#define RG_RESET_OFST (14)
++#define RG_DATAIN_OFST (10)
++#define RG_TXVALIDH_OFST (9)
++#define RG_TXVALID_OFST (8)
++#define RG_DMPULLDOWN_OFST (7)
++#define RG_DPPULLDOWN_OFST (6)
++#define RG_XCVRSEL_OFST (4)
++#define RG_SUSPENDM_OFST (3)
++#define RG_TERMSEL_OFST (2)
++#define RG_OPMODE_OFST (0)
++
++//U3D_U2PHYDTM1
++#define RG_USB20_PRBS7_EN_OFST (31)
++#define RG_USB20_PRBS7_BITCNT_OFST (24)
++#define RG_USB20_CLK48M_EN_OFST (23)
++#define RG_USB20_CLK60M_EN_OFST (22)
++#define RG_UART_I_OFST (19)
++#define RG_UART_BIAS_EN_OFST (18)
++#define RG_UART_TX_OE_OFST (17)
++#define RG_UART_EN_OFST (16)
++#define FORCE_VBUSVALID_OFST (13)
++#define FORCE_SESSEND_OFST (12)
++#define FORCE_BVALID_OFST (11)
++#define FORCE_AVALID_OFST (10)
++#define FORCE_IDDIG_OFST (9)
++#define FORCE_IDPULLUP_OFST (8)
++#define RG_VBUSVALID_OFST (5)
++#define RG_SESSEND_OFST (4)
++#define RG_BVALID_OFST (3)
++#define RG_AVALID_OFST (2)
++#define RG_IDDIG_OFST (1)
++#define RG_IDPULLUP_OFST (0)
++
++//U3D_U2PHYDMON0
++#define RG_USB20_PRBS7_BERTH_OFST (0)
++
++//U3D_U2PHYDMON1
++#define USB20_UART_O_OFST (31)
++#define RGO_USB20_LB_PASS_OFST (30)
++#define RGO_USB20_LB_DONE_OFST (29)
++#define AD_USB20_BVALID_OFST (28)
++#define USB20_IDDIG_OFST (27)
++#define AD_USB20_VBUSVALID_OFST (26)
++#define AD_USB20_SESSEND_OFST (25)
++#define AD_USB20_AVALID_OFST (24)
++#define USB20_LINE_STATE_OFST (22)
++#define USB20_HST_DISCON_OFST (21)
++#define USB20_TX_READY_OFST (20)
++#define USB20_RX_ERROR_OFST (19)
++#define USB20_RX_ACTIVE_OFST (18)
++#define USB20_RX_VALIDH_OFST (17)
++#define USB20_RX_VALID_OFST (16)
++#define USB20_DATA_OUT_OFST (0)
++
++//U3D_U2PHYDMON2
++#define RGO_TXVALID_CNT_OFST (24)
++#define RGO_RXACTIVE_CNT_OFST (16)
++#define RGO_USB20_LB_BERCNT_OFST (8)
++#define USB20_PROBE_OUT_OFST (0)
++
++//U3D_U2PHYDMON3
++#define RGO_USB20_PRBS7_ERRCNT_OFST (16)
++#define RGO_USB20_PRBS7_DONE_OFST (3)
++#define RGO_USB20_PRBS7_LOCK_OFST (2)
++#define RGO_USB20_PRBS7_PASS_OFST (1)
++#define RGO_USB20_PRBS7_PASSTH_OFST (0)
++
++//U3D_U2PHYBC12C
++#define RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST (28)
++#define RG_SIFSLV_CHGDT_CTRL_CNT_OFST (24)
++#define RG_SIFSLV_CHGDT_FORCE_MODE_OFST (16)
++#define RG_CHGDT_ISRC_LEV_OFST (14)
++#define RG_CHGDT_VDATSRC_OFST (13)
++#define RG_CHGDT_BGVREF_SEL_OFST (10)
++#define RG_CHGDT_RDVREF_SEL_OFST (8)
++#define RG_CHGDT_ISRC_DP_OFST (7)
++#define RG_SIFSLV_CHGDT_OPOUT_DM_OFST (6)
++#define RG_CHGDT_VDAT_DM_OFST (5)
++#define RG_CHGDT_OPOUT_DP_OFST (4)
++#define RG_SIFSLV_CHGDT_VDAT_DP_OFST (3)
++#define RG_SIFSLV_CHGDT_COMP_EN_OFST (2)
++#define RG_SIFSLV_CHGDT_OPDRV_EN_OFST (1)
++#define RG_CHGDT_EN_OFST (0)
++
++//U3D_U2PHYBC12C1
++#define RG_CHGDT_REV_OFST (0)
++
++//U3D_REGFCOM
++#define RG_PAGE_OFST (24)
++#define I2C_MODE_OFST (16)
++
++
++///////////////////////////////////////////////////////////////////////////////
++
++struct u3phya_reg {
++ //0x0
++ PHY_LE32 reg0;
++ PHY_LE32 reg1;
++ PHY_LE32 reg2;
++ PHY_LE32 reg3;
++ //0x10
++ PHY_LE32 reg4;
++ PHY_LE32 reg5;
++ PHY_LE32 reg6;
++ PHY_LE32 reg7;
++ //0x20
++ PHY_LE32 reg8;
++ PHY_LE32 reg9;
++ PHY_LE32 rega;
++ PHY_LE32 regb;
++ //0x30
++ PHY_LE32 regc;
++ PHY_LE32 regd;
++ PHY_LE32 rege;
++};
++
++//U3D_reg0
++#define RG_SSUSB_BGR_EN (0x1<<31) //31:31
++#define RG_SSUSB_CHPEN (0x1<<30) //30:30
++#define RG_SSUSB_BG_DIV (0x3<<28) //29:28
++#define RG_SSUSB_INTR_EN (0x1<<26) //26:26
++#define RG_SSUSB_MPX_OUT_SEL (0x3<<24) //25:24
++#define RG_SSUSB_MPX_SEL (0xff<<16) //23:16
++#define RG_SSUSB_REF_EN (0x1<<15) //15:15
++#define RG_SSUSB_VRT_VREF_SEL (0xf<<11) //14:11
++#define RG_SSUSB_BG_RASEL (0x3<<9) //10:9
++#define RG_SSUSB_BG_RBSEL (0x3<<7) //8:7
++#define RG_SSUSB_BG_MONEN (0x1<<6) //6:6
++#define RG_PCIE_CLKDRV_OFFSET (0x3<<0) //1:0
++
++//U3D_reg1
++#define RG_PCIE_CLKDRV_SLEW (0x3<<30) //31:30
++#define RG_PCIE_CLKDRV_AMP (0x7<<27) //29:27
++#define RG_SSUSB_XTAL_TST_A2DCK_EN (0x1<<26) //26:26
++#define RG_SSUSB_XTAL_MON_EN (0x1<<25) //25:25
++#define RG_SSUSB_XTAL_HYS (0x1<<24) //24:24
++#define RG_SSUSB_XTAL_TOP_RESERVE (0xffff<<8) //23:8
++#define RG_SSUSB_SYSPLL_RESERVE (0xf<<4) //7:4
++#define RG_SSUSB_SYSPLL_FBSEL (0x3<<2) //3:2
++#define RG_SSUSB_SYSPLL_PREDIV (0x3<<0) //1:0
++
++//U3D_reg2
++#define RG_SSUSB_SYSPLL_LF (0x1<<31) //31:31
++#define RG_SSUSB_SYSPLL_FBDIV (0x7f<<24) //30:24
++#define RG_SSUSB_SYSPLL_POSDIV (0x3<<22) //23:22
++#define RG_SSUSB_SYSPLL_VCO_DIV_SEL (0x1<<21) //21:21
++#define RG_SSUSB_SYSPLL_BLP (0x1<<20) //20:20
++#define RG_SSUSB_SYSPLL_BP (0x1<<19) //19:19
++#define RG_SSUSB_SYSPLL_BR (0x1<<18) //18:18
++#define RG_SSUSB_SYSPLL_BC (0x1<<17) //17:17
++#define RG_SSUSB_SYSPLL_DIVEN (0x7<<14) //16:14
++#define RG_SSUSB_SYSPLL_FPEN (0x1<<13) //13:13
++#define RG_SSUSB_SYSPLL_MONCK_EN (0x1<<12) //12:12
++#define RG_SSUSB_SYSPLL_MONVC_EN (0x1<<11) //11:11
++#define RG_SSUSB_SYSPLL_MONREF_EN (0x1<<10) //10:10
++#define RG_SSUSB_SYSPLL_VOD_EN (0x1<<9) //9:9
++#define RG_SSUSB_SYSPLL_CK_SEL (0x1<<8) //8:8
++
++//U3D_reg3
++#define RG_SSUSB_SYSPLL_TOP_RESERVE (0xffff<<16) //31:16
++
++//U3D_reg4
++#define RG_SSUSB_SYSPLL_PCW_NCPO (0x7fffffff<<1) //31:1
++
++//U3D_reg5
++#define RG_SSUSB_SYSPLL_DDS_PI_C (0x7<<29) //31:29
++#define RG_SSUSB_SYSPLL_DDS_HF_EN (0x1<<28) //28:28
++#define RG_SSUSB_SYSPLL_DDS_PREDIV2 (0x1<<27) //27:27
++#define RG_SSUSB_SYSPLL_DDS_POSTDIV2 (0x1<<26) //26:26
++#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN (0x1<<25) //25:25
++#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL (0x1<<24) //24:24
++#define RG_SSUSB_SYSPLL_DDS_MONEN (0x1<<23) //23:23
++#define RG_SSUSB_SYSPLL_DDS_LPF_EN (0x1<<22) //22:22
++#define RG_SSUSB_SYSPLL_CLK_PH_INV (0x1<<21) //21:21
++#define RG_SSUSB_SYSPLL_DDS_SEL_EXT (0x1<<20) //20:20
++#define RG_SSUSB_SYSPLL_DDS_DMY (0xffff<<0) //15:0
++
++//U3D_reg6
++#define RG_SSUSB_TX250MCK_INVB (0x1<<31) //31:31
++#define RG_SSUSB_IDRV_ITAILOP_EN (0x1<<30) //30:30
++#define RG_SSUSB_IDRV_CALIB (0x3f<<24) //29:24
++#define RG_SSUSB_TX_R50_FON (0x1<<23) //23:23
++#define RG_SSUSB_TX_SR (0x7<<20) //22:20
++#define RG_SSUSB_TX_EIDLE_CM (0xf<<16) //19:16
++#define RG_SSUSB_RXDET_RSEL (0x3<<14) //15:14
++#define RG_SSUSB_RXDET_VTHSEL (0x3<<12) //13:12
++#define RG_SSUSB_CKMON_EN (0x1<<11) //11:11
++#define RG_SSUSB_CKMON_SEL (0x7<<8) //10:8
++#define RG_SSUSB_TX_VLMON_EN (0x1<<7) //7:7
++#define RG_SSUSB_TX_VLMON_SEL (0x1<<6) //6:6
++#define RG_SSUSB_RXLBTX_EN (0x1<<5) //5:5
++#define RG_SSUSB_TXLBRX_EN (0x1<<4) //4:4
++
++//U3D_reg7
++#define RG_SSUSB_RESERVE (0xfffff<<12) //31:12
++#define RG_SSUSB_PLL_CKCTRL (0x3<<10) //11:10
++#define RG_SSUSB_PLL_POSDIV (0x3<<8) //9:8
++#define RG_SSUSB_PLL_AUTOK_LOAD (0x1<<7) //7:7
++#define RG_SSUSB_PLL_LOAD_RSTB (0x1<<6) //6:6
++#define RG_SSUSB_PLL_EP_EN (0x1<<5) //5:5
++#define RG_SSUSB_PLL_VOD_EN (0x1<<4) //4:4
++#define RG_SSUSB_PLL_V11_EN (0x1<<3) //3:3
++#define RG_SSUSB_PLL_MONREF_EN (0x1<<2) //2:2
++#define RG_SSUSB_PLL_MONCK_EN (0x1<<1) //1:1
++#define RG_SSUSB_PLL_MONVC_EN (0x1<<0) //0:0
++
++//U3D_reg8
++#define RG_SSUSB_PLL_RESERVE (0xffff<<0) //15:0
++
++//U3D_reg9
++#define RG_SSUSB_PLL_DDS_DMY (0xffff<<16) //31:16
++#define RG_SSUSB_PLL_SSC_PRD (0xffff<<0) //15:0
++
++//U3D_regA
++#define RG_SSUSB_PLL_SSC_PHASE_INI (0x1<<31) //31:31
++#define RG_SSUSB_PLL_SSC_TRI_EN (0x1<<30) //30:30
++#define RG_SSUSB_PLL_CLK_PH_INV (0x1<<29) //29:29
++#define RG_SSUSB_PLL_DDS_LPF_EN (0x1<<28) //28:28
++#define RG_SSUSB_PLL_DDS_VADJ (0x7<<21) //23:21
++#define RG_SSUSB_PLL_DDS_MONEN (0x1<<20) //20:20
++#define RG_SSUSB_PLL_DDS_PS_VADJ (0x7<<17) //19:17
++#define RG_SSUSB_PLL_DDS_SEL_EXT (0x1<<16) //16:16
++#define RG_SSUSB_CDR_PD_DIV_BYPASS (0x1<<15) //15:15
++#define RG_SSUSB_CDR_PD_DIV_SEL (0x1<<14) //14:14
++#define RG_SSUSB_CDR_CPBIAS_SEL (0x1<<13) //13:13
++#define RG_SSUSB_CDR_OSCDET_EN (0x1<<12) //12:12
++#define RG_SSUSB_CDR_MONMUX (0x1<<11) //11:11
++#define RG_SSUSB_CDR_CKCTRL (0x3<<9) //10:9
++#define RG_SSUSB_CDR_ACCEN (0x1<<8) //8:8
++#define RG_SSUSB_CDR_BYPASS (0x3<<6) //7:6
++#define RG_SSUSB_CDR_PI_SLEW (0x3<<4) //5:4
++#define RG_SSUSB_CDR_EPEN (0x1<<3) //3:3
++#define RG_SSUSB_CDR_AUTOK_LOAD (0x1<<2) //2:2
++#define RG_SSUSB_CDR_LOAD_RSTB (0x1<<1) //1:1
++#define RG_SSUSB_CDR_MONEN (0x1<<0) //0:0
++
++//U3D_regB
++#define RG_SSUSB_CDR_MONEN_DIG (0x1<<31) //31:31
++#define RG_SSUSB_CDR_REGOD (0x3<<29) //30:29
++#define RG_SSUSB_RX_DAC_EN (0x1<<26) //26:26
++#define RG_SSUSB_RX_DAC_PWD (0x1<<25) //25:25
++#define RG_SSUSB_EQ_CURSEL (0x1<<24) //24:24
++#define RG_SSUSB_RX_DAC_MUX (0x1f<<19) //23:19
++#define RG_SSUSB_RX_R2T_EN (0x1<<18) //18:18
++#define RG_SSUSB_RX_T2R_EN (0x1<<17) //17:17
++#define RG_SSUSB_RX_50_LOWER (0x7<<14) //16:14
++#define RG_SSUSB_RX_50_TAR (0x3<<12) //13:12
++#define RG_SSUSB_RX_SW_CTRL (0xf<<7) //10:7
++#define RG_PCIE_SIGDET_VTH (0x3<<5) //6:5
++#define RG_PCIE_SIGDET_LPF (0x3<<3) //4:3
++#define RG_SSUSB_LFPS_MON_EN (0x1<<2) //2:2
++
++//U3D_regC
++#define RG_SSUSB_RXAFE_DCMON_SEL (0xf<<28) //31:28
++#define RG_SSUSB_CDR_RESERVE (0xff<<16) //23:16
++#define RG_SSUSB_RXAFE_RESERVE (0xff<<8) //15:8
++#define RG_PCIE_RX_RESERVE (0xff<<0) //7:0
++
++//U3D_redD
++#define RGS_SSUSB_CDR_NO_OSC (0x1<<8) //8:8
++#define RGS_SSUSB_RX_DEBUG_RESERVE (0xff<<0) //7:0
++
++//U3D_regE
++#define RG_SSUSB_INT_BIAS_SEL (0x1<<4) //4:4
++#define RG_SSUSB_EXT_BIAS_SEL (0x1<<3) //3:3
++#define RG_SSUSB_RX_P1_ENTRY_PASS (0x1<<2) //2:2
++#define RG_SSUSB_RX_PD_RST (0x1<<1) //1:1
++#define RG_SSUSB_RX_PD_RST_PASS (0x1<<0) //0:0
++
++
++/* OFFSET */
++
++//U3D_reg0
++#define RG_SSUSB_BGR_EN_OFST (31)
++#define RG_SSUSB_CHPEN_OFST (30)
++#define RG_SSUSB_BG_DIV_OFST (28)
++#define RG_SSUSB_INTR_EN_OFST (26)
++#define RG_SSUSB_MPX_OUT_SEL_OFST (24)
++#define RG_SSUSB_MPX_SEL_OFST (16)
++#define RG_SSUSB_REF_EN_OFST (15)
++#define RG_SSUSB_VRT_VREF_SEL_OFST (11)
++#define RG_SSUSB_BG_RASEL_OFST (9)
++#define RG_SSUSB_BG_RBSEL_OFST (7)
++#define RG_SSUSB_BG_MONEN_OFST (6)
++#define RG_PCIE_CLKDRV_OFFSET_OFST (0)
++
++//U3D_reg1
++#define RG_PCIE_CLKDRV_SLEW_OFST (30)
++#define RG_PCIE_CLKDRV_AMP_OFST (27)
++#define RG_SSUSB_XTAL_TST_A2DCK_EN_OFST (26)
++#define RG_SSUSB_XTAL_MON_EN_OFST (25)
++#define RG_SSUSB_XTAL_HYS_OFST (24)
++#define RG_SSUSB_XTAL_TOP_RESERVE_OFST (8)
++#define RG_SSUSB_SYSPLL_RESERVE_OFST (4)
++#define RG_SSUSB_SYSPLL_FBSEL_OFST (2)
++#define RG_SSUSB_SYSPLL_PREDIV_OFST (0)
++
++//U3D_reg2
++#define RG_SSUSB_SYSPLL_LF_OFST (31)
++#define RG_SSUSB_SYSPLL_FBDIV_OFST (24)
++#define RG_SSUSB_SYSPLL_POSDIV_OFST (22)
++#define RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST (21)
++#define RG_SSUSB_SYSPLL_BLP_OFST (20)
++#define RG_SSUSB_SYSPLL_BP_OFST (19)
++#define RG_SSUSB_SYSPLL_BR_OFST (18)
++#define RG_SSUSB_SYSPLL_BC_OFST (17)
++#define RG_SSUSB_SYSPLL_DIVEN_OFST (14)
++#define RG_SSUSB_SYSPLL_FPEN_OFST (13)
++#define RG_SSUSB_SYSPLL_MONCK_EN_OFST (12)
++#define RG_SSUSB_SYSPLL_MONVC_EN_OFST (11)
++#define RG_SSUSB_SYSPLL_MONREF_EN_OFST (10)
++#define RG_SSUSB_SYSPLL_VOD_EN_OFST (9)
++#define RG_SSUSB_SYSPLL_CK_SEL_OFST (8)
++
++//U3D_reg3
++#define RG_SSUSB_SYSPLL_TOP_RESERVE_OFST (16)
++
++//U3D_reg4
++#define RG_SSUSB_SYSPLL_PCW_NCPO_OFST (1)
++
++//U3D_reg5
++#define RG_SSUSB_SYSPLL_DDS_PI_C_OFST (29)
++#define RG_SSUSB_SYSPLL_DDS_HF_EN_OFST (28)
++#define RG_SSUSB_SYSPLL_DDS_PREDIV2_OFST (27)
++#define RG_SSUSB_SYSPLL_DDS_POSTDIV2_OFST (26)
++#define RG_SSUSB_SYSPLL_DDS_PI_PL_EN_OFST (25)
++#define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL_OFST (24)
++#define RG_SSUSB_SYSPLL_DDS_MONEN_OFST (23)
++#define RG_SSUSB_SYSPLL_DDS_LPF_EN_OFST (22)
++#define RG_SSUSB_SYSPLL_CLK_PH_INV_OFST (21)
++#define RG_SSUSB_SYSPLL_DDS_SEL_EXT_OFST (20)
++#define RG_SSUSB_SYSPLL_DDS_DMY_OFST (0)
++
++//U3D_reg6
++#define RG_SSUSB_TX250MCK_INVB_OFST (31)
++#define RG_SSUSB_IDRV_ITAILOP_EN_OFST (30)
++#define RG_SSUSB_IDRV_CALIB_OFST (24)
++#define RG_SSUSB_TX_R50_FON_OFST (23)
++#define RG_SSUSB_TX_SR_OFST (20)
++#define RG_SSUSB_TX_EIDLE_CM_OFST (16)
++#define RG_SSUSB_RXDET_RSEL_OFST (14)
++#define RG_SSUSB_RXDET_VTHSEL_OFST (12)
++#define RG_SSUSB_CKMON_EN_OFST (11)
++#define RG_SSUSB_CKMON_SEL_OFST (8)
++#define RG_SSUSB_TX_VLMON_EN_OFST (7)
++#define RG_SSUSB_TX_VLMON_SEL_OFST (6)
++#define RG_SSUSB_RXLBTX_EN_OFST (5)
++#define RG_SSUSB_TXLBRX_EN_OFST (4)
++
++//U3D_reg7
++#define RG_SSUSB_RESERVE_OFST (12)
++#define RG_SSUSB_PLL_CKCTRL_OFST (10)
++#define RG_SSUSB_PLL_POSDIV_OFST (8)
++#define RG_SSUSB_PLL_AUTOK_LOAD_OFST (7)
++#define RG_SSUSB_PLL_LOAD_RSTB_OFST (6)
++#define RG_SSUSB_PLL_EP_EN_OFST (5)
++#define RG_SSUSB_PLL_VOD_EN_OFST (4)
++#define RG_SSUSB_PLL_V11_EN_OFST (3)
++#define RG_SSUSB_PLL_MONREF_EN_OFST (2)
++#define RG_SSUSB_PLL_MONCK_EN_OFST (1)
++#define RG_SSUSB_PLL_MONVC_EN_OFST (0)
++
++//U3D_reg8
++#define RG_SSUSB_PLL_RESERVE_OFST (0)
++
++//U3D_reg9
++#define RG_SSUSB_PLL_DDS_DMY_OFST (16)
++#define RG_SSUSB_PLL_SSC_PRD_OFST (0)
++
++//U3D_regA
++#define RG_SSUSB_PLL_SSC_PHASE_INI_OFST (31)
++#define RG_SSUSB_PLL_SSC_TRI_EN_OFST (30)
++#define RG_SSUSB_PLL_CLK_PH_INV_OFST (29)
++#define RG_SSUSB_PLL_DDS_LPF_EN_OFST (28)
++#define RG_SSUSB_PLL_DDS_VADJ_OFST (21)
++#define RG_SSUSB_PLL_DDS_MONEN_OFST (20)
++#define RG_SSUSB_PLL_DDS_PS_VADJ_OFST (17)
++#define RG_SSUSB_PLL_DDS_SEL_EXT_OFST (16)
++#define RG_SSUSB_CDR_PD_DIV_BYPASS_OFST (15)
++#define RG_SSUSB_CDR_PD_DIV_SEL_OFST (14)
++#define RG_SSUSB_CDR_CPBIAS_SEL_OFST (13)
++#define RG_SSUSB_CDR_OSCDET_EN_OFST (12)
++#define RG_SSUSB_CDR_MONMUX_OFST (11)
++#define RG_SSUSB_CDR_CKCTRL_OFST (9)
++#define RG_SSUSB_CDR_ACCEN_OFST (8)
++#define RG_SSUSB_CDR_BYPASS_OFST (6)
++#define RG_SSUSB_CDR_PI_SLEW_OFST (4)
++#define RG_SSUSB_CDR_EPEN_OFST (3)
++#define RG_SSUSB_CDR_AUTOK_LOAD_OFST (2)
++#define RG_SSUSB_CDR_LOAD_RSTB_OFST (1)
++#define RG_SSUSB_CDR_MONEN_OFST (0)
++
++//U3D_regB
++#define RG_SSUSB_CDR_MONEN_DIG_OFST (31)
++#define RG_SSUSB_CDR_REGOD_OFST (29)
++#define RG_SSUSB_RX_DAC_EN_OFST (26)
++#define RG_SSUSB_RX_DAC_PWD_OFST (25)
++#define RG_SSUSB_EQ_CURSEL_OFST (24)
++#define RG_SSUSB_RX_DAC_MUX_OFST (19)
++#define RG_SSUSB_RX_R2T_EN_OFST (18)
++#define RG_SSUSB_RX_T2R_EN_OFST (17)
++#define RG_SSUSB_RX_50_LOWER_OFST (14)
++#define RG_SSUSB_RX_50_TAR_OFST (12)
++#define RG_SSUSB_RX_SW_CTRL_OFST (7)
++#define RG_PCIE_SIGDET_VTH_OFST (5)
++#define RG_PCIE_SIGDET_LPF_OFST (3)
++#define RG_SSUSB_LFPS_MON_EN_OFST (2)
++
++//U3D_regC
++#define RG_SSUSB_RXAFE_DCMON_SEL_OFST (28)
++#define RG_SSUSB_CDR_RESERVE_OFST (16)
++#define RG_SSUSB_RXAFE_RESERVE_OFST (8)
++#define RG_PCIE_RX_RESERVE_OFST (0)
++
++//U3D_redD
++#define RGS_SSUSB_CDR_NO_OSC_OFST (8)
++#define RGS_SSUSB_RX_DEBUG_RESERVE_OFST (0)
++
++//U3D_regE
++#define RG_SSUSB_INT_BIAS_SEL_OFST (4)
++#define RG_SSUSB_EXT_BIAS_SEL_OFST (3)
++#define RG_SSUSB_RX_P1_ENTRY_PASS_OFST (2)
++#define RG_SSUSB_RX_PD_RST_OFST (1)
++#define RG_SSUSB_RX_PD_RST_PASS_OFST (0)
++
++///////////////////////////////////////////////////////////////////////////////
++
++struct u3phya_da_reg {
++ //0x0
++ PHY_LE32 reg0;
++ PHY_LE32 reg1;
++ PHY_LE32 reg4;
++ PHY_LE32 reg5;
++ //0x10
++ PHY_LE32 reg6;
++ PHY_LE32 reg7;
++ PHY_LE32 reg8;
++ PHY_LE32 reg9;
++ //0x20
++ PHY_LE32 reg10;
++ PHY_LE32 reg12;
++ PHY_LE32 reg13;
++ PHY_LE32 reg14;
++ //0x30
++ PHY_LE32 reg15;
++ PHY_LE32 reg16;
++ PHY_LE32 reg19;
++ PHY_LE32 reg20;
++ //0x40
++ PHY_LE32 reg21;
++ PHY_LE32 reg23;
++ PHY_LE32 reg25;
++ PHY_LE32 reg26;
++ //0x50
++ PHY_LE32 reg28;
++ PHY_LE32 reg29;
++ PHY_LE32 reg30;
++ PHY_LE32 reg31;
++ //0x60
++ PHY_LE32 reg32;
++ PHY_LE32 reg33;
++};
++
++//U3D_reg0
++#define RG_PCIE_SPEED_PE2D (0x1<<24) //24:24
++#define RG_PCIE_SPEED_PE2H (0x1<<23) //23:23
++#define RG_PCIE_SPEED_PE1D (0x1<<22) //22:22
++#define RG_PCIE_SPEED_PE1H (0x1<<21) //21:21
++#define RG_PCIE_SPEED_U3 (0x1<<20) //20:20
++#define RG_SSUSB_XTAL_EXT_EN_PE2D (0x3<<18) //19:18
++#define RG_SSUSB_XTAL_EXT_EN_PE2H (0x3<<16) //17:16
++#define RG_SSUSB_XTAL_EXT_EN_PE1D (0x3<<14) //15:14
++#define RG_SSUSB_XTAL_EXT_EN_PE1H (0x3<<12) //13:12
++#define RG_SSUSB_XTAL_EXT_EN_U3 (0x3<<10) //11:10
++#define RG_SSUSB_CDR_REFCK_SEL_PE2D (0x3<<8) //9:8
++#define RG_SSUSB_CDR_REFCK_SEL_PE2H (0x3<<6) //7:6
++#define RG_SSUSB_CDR_REFCK_SEL_PE1D (0x3<<4) //5:4
++#define RG_SSUSB_CDR_REFCK_SEL_PE1H (0x3<<2) //3:2
++#define RG_SSUSB_CDR_REFCK_SEL_U3 (0x3<<0) //1:0
++
++//U3D_reg1
++#define RG_USB20_REFCK_SEL_PE2D (0x1<<30) //30:30
++#define RG_USB20_REFCK_SEL_PE2H (0x1<<29) //29:29
++#define RG_USB20_REFCK_SEL_PE1D (0x1<<28) //28:28
++#define RG_USB20_REFCK_SEL_PE1H (0x1<<27) //27:27
++#define RG_USB20_REFCK_SEL_U3 (0x1<<26) //26:26
++#define RG_PCIE_REFCK_DIV4_PE2D (0x1<<25) //25:25
++#define RG_PCIE_REFCK_DIV4_PE2H (0x1<<24) //24:24
++#define RG_PCIE_REFCK_DIV4_PE1D (0x1<<18) //18:18
++#define RG_PCIE_REFCK_DIV4_PE1H (0x1<<17) //17:17
++#define RG_PCIE_REFCK_DIV4_U3 (0x1<<16) //16:16
++#define RG_PCIE_MODE_PE2D (0x1<<8) //8:8
++#define RG_PCIE_MODE_PE2H (0x1<<3) //3:3
++#define RG_PCIE_MODE_PE1D (0x1<<2) //2:2
++#define RG_PCIE_MODE_PE1H (0x1<<1) //1:1
++#define RG_PCIE_MODE_U3 (0x1<<0) //0:0
++
++//U3D_reg4
++#define RG_SSUSB_PLL_DIVEN_PE2D (0x7<<22) //24:22
++#define RG_SSUSB_PLL_DIVEN_PE2H (0x7<<19) //21:19
++#define RG_SSUSB_PLL_DIVEN_PE1D (0x7<<16) //18:16
++#define RG_SSUSB_PLL_DIVEN_PE1H (0x7<<13) //15:13
++#define RG_SSUSB_PLL_DIVEN_U3 (0x7<<10) //12:10
++#define RG_SSUSB_PLL_BC_PE2D (0x3<<8) //9:8
++#define RG_SSUSB_PLL_BC_PE2H (0x3<<6) //7:6
++#define RG_SSUSB_PLL_BC_PE1D (0x3<<4) //5:4
++#define RG_SSUSB_PLL_BC_PE1H (0x3<<2) //3:2
++#define RG_SSUSB_PLL_BC_U3 (0x3<<0) //1:0
++
++//U3D_reg5
++#define RG_SSUSB_PLL_BR_PE2D (0x7<<27) //29:27
++#define RG_SSUSB_PLL_BR_PE2H (0x7<<24) //26:24
++#define RG_SSUSB_PLL_BR_PE1D (0x7<<21) //23:21
++#define RG_SSUSB_PLL_BR_PE1H (0x7<<18) //20:18
++#define RG_SSUSB_PLL_BR_U3 (0x7<<15) //17:15
++#define RG_SSUSB_PLL_IC_PE2D (0x7<<12) //14:12
++#define RG_SSUSB_PLL_IC_PE2H (0x7<<9) //11:9
++#define RG_SSUSB_PLL_IC_PE1D (0x7<<6) //8:6
++#define RG_SSUSB_PLL_IC_PE1H (0x7<<3) //5:3
++#define RG_SSUSB_PLL_IC_U3 (0x7<<0) //2:0
++
++//U3D_reg6
++#define RG_SSUSB_PLL_IR_PE2D (0xf<<24) //27:24
++#define RG_SSUSB_PLL_IR_PE2H (0xf<<16) //19:16
++#define RG_SSUSB_PLL_IR_PE1D (0xf<<8) //11:8
++#define RG_SSUSB_PLL_IR_PE1H (0xf<<4) //7:4
++#define RG_SSUSB_PLL_IR_U3 (0xf<<0) //3:0
++
++//U3D_reg7
++#define RG_SSUSB_PLL_BP_PE2D (0xf<<24) //27:24
++#define RG_SSUSB_PLL_BP_PE2H (0xf<<16) //19:16
++#define RG_SSUSB_PLL_BP_PE1D (0xf<<8) //11:8
++#define RG_SSUSB_PLL_BP_PE1H (0xf<<4) //7:4
++#define RG_SSUSB_PLL_BP_U3 (0xf<<0) //3:0
++
++//U3D_reg8
++#define RG_SSUSB_PLL_FBKSEL_PE2D (0x3<<24) //25:24
++#define RG_SSUSB_PLL_FBKSEL_PE2H (0x3<<16) //17:16
++#define RG_SSUSB_PLL_FBKSEL_PE1D (0x3<<8) //9:8
++#define RG_SSUSB_PLL_FBKSEL_PE1H (0x3<<2) //3:2
++#define RG_SSUSB_PLL_FBKSEL_U3 (0x3<<0) //1:0
++
++//U3D_reg9
++#define RG_SSUSB_PLL_FBKDIV_PE2H (0x7f<<24) //30:24
++#define RG_SSUSB_PLL_FBKDIV_PE1D (0x7f<<16) //22:16
++#define RG_SSUSB_PLL_FBKDIV_PE1H (0x7f<<8) //14:8
++#define RG_SSUSB_PLL_FBKDIV_U3 (0x7f<<0) //6:0
++
++//U3D_reg10
++#define RG_SSUSB_PLL_PREDIV_PE2D (0x3<<26) //27:26
++#define RG_SSUSB_PLL_PREDIV_PE2H (0x3<<24) //25:24
++#define RG_SSUSB_PLL_PREDIV_PE1D (0x3<<18) //19:18
++#define RG_SSUSB_PLL_PREDIV_PE1H (0x3<<16) //17:16
++#define RG_SSUSB_PLL_PREDIV_U3 (0x3<<8) //9:8
++#define RG_SSUSB_PLL_FBKDIV_PE2D (0x7f<<0) //6:0
++
++//U3D_reg12
++#define RG_SSUSB_PLL_PCW_NCPO_U3 (0x7fffffff<<0) //30:0
++
++//U3D_reg13
++#define RG_SSUSB_PLL_PCW_NCPO_PE1H (0x7fffffff<<0) //30:0
++
++//U3D_reg14
++#define RG_SSUSB_PLL_PCW_NCPO_PE1D (0x7fffffff<<0) //30:0
++
++//U3D_reg15
++#define RG_SSUSB_PLL_PCW_NCPO_PE2H (0x7fffffff<<0) //30:0
++
++//U3D_reg16
++#define RG_SSUSB_PLL_PCW_NCPO_PE2D (0x7fffffff<<0) //30:0
++
++//U3D_reg19
++#define RG_SSUSB_PLL_SSC_DELTA1_PE1H (0xffff<<16) //31:16
++#define RG_SSUSB_PLL_SSC_DELTA1_U3 (0xffff<<0) //15:0
++
++//U3D_reg20
++#define RG_SSUSB_PLL_SSC_DELTA1_PE2H (0xffff<<16) //31:16
++#define RG_SSUSB_PLL_SSC_DELTA1_PE1D (0xffff<<0) //15:0
++
++//U3D_reg21
++#define RG_SSUSB_PLL_SSC_DELTA_U3 (0xffff<<16) //31:16
++#define RG_SSUSB_PLL_SSC_DELTA1_PE2D (0xffff<<0) //15:0
++
++//U3D_reg23
++#define RG_SSUSB_PLL_SSC_DELTA_PE1D (0xffff<<16) //31:16
++#define RG_SSUSB_PLL_SSC_DELTA_PE1H (0xffff<<0) //15:0
++
++//U3D_reg25
++#define RG_SSUSB_PLL_SSC_DELTA_PE2D (0xffff<<16) //31:16
++#define RG_SSUSB_PLL_SSC_DELTA_PE2H (0xffff<<0) //15:0
++
++//U3D_reg26
++#define RG_SSUSB_PLL_REFCKDIV_PE2D (0x1<<25) //25:25
++#define RG_SSUSB_PLL_REFCKDIV_PE2H (0x1<<24) //24:24
++#define RG_SSUSB_PLL_REFCKDIV_PE1D (0x1<<16) //16:16
++#define RG_SSUSB_PLL_REFCKDIV_PE1H (0x1<<8) //8:8
++#define RG_SSUSB_PLL_REFCKDIV_U3 (0x1<<0) //0:0
++
++//U3D_reg28
++#define RG_SSUSB_CDR_BPA_PE2D (0x3<<24) //25:24
++#define RG_SSUSB_CDR_BPA_PE2H (0x3<<16) //17:16
++#define RG_SSUSB_CDR_BPA_PE1D (0x3<<10) //11:10
++#define RG_SSUSB_CDR_BPA_PE1H (0x3<<8) //9:8
++#define RG_SSUSB_CDR_BPA_U3 (0x3<<0) //1:0
++
++//U3D_reg29
++#define RG_SSUSB_CDR_BPB_PE2D (0x7<<24) //26:24
++#define RG_SSUSB_CDR_BPB_PE2H (0x7<<16) //18:16
++#define RG_SSUSB_CDR_BPB_PE1D (0x7<<6) //8:6
++#define RG_SSUSB_CDR_BPB_PE1H (0x7<<3) //5:3
++#define RG_SSUSB_CDR_BPB_U3 (0x7<<0) //2:0
++
++//U3D_reg30
++#define RG_SSUSB_CDR_BR_PE2D (0x7<<24) //26:24
++#define RG_SSUSB_CDR_BR_PE2H (0x7<<16) //18:16
++#define RG_SSUSB_CDR_BR_PE1D (0x7<<6) //8:6
++#define RG_SSUSB_CDR_BR_PE1H (0x7<<3) //5:3
++#define RG_SSUSB_CDR_BR_U3 (0x7<<0) //2:0
++
++//U3D_reg31
++#define RG_SSUSB_CDR_FBDIV_PE2H (0x7f<<24) //30:24
++#define RG_SSUSB_CDR_FBDIV_PE1D (0x7f<<16) //22:16
++#define RG_SSUSB_CDR_FBDIV_PE1H (0x7f<<8) //14:8
++#define RG_SSUSB_CDR_FBDIV_U3 (0x7f<<0) //6:0
++
++//U3D_reg32
++#define RG_SSUSB_EQ_RSTEP1_PE2D (0x3<<30) //31:30
++#define RG_SSUSB_EQ_RSTEP1_PE2H (0x3<<28) //29:28
++#define RG_SSUSB_EQ_RSTEP1_PE1D (0x3<<26) //27:26
++#define RG_SSUSB_EQ_RSTEP1_PE1H (0x3<<24) //25:24
++#define RG_SSUSB_EQ_RSTEP1_U3 (0x3<<22) //23:22
++#define RG_SSUSB_LFPS_DEGLITCH_PE2D (0x3<<20) //21:20
++#define RG_SSUSB_LFPS_DEGLITCH_PE2H (0x3<<18) //19:18
++#define RG_SSUSB_LFPS_DEGLITCH_PE1D (0x3<<16) //17:16
++#define RG_SSUSB_LFPS_DEGLITCH_PE1H (0x3<<14) //15:14
++#define RG_SSUSB_LFPS_DEGLITCH_U3 (0x3<<12) //13:12
++#define RG_SSUSB_CDR_KVSEL_PE2D (0x1<<11) //11:11
++#define RG_SSUSB_CDR_KVSEL_PE2H (0x1<<10) //10:10
++#define RG_SSUSB_CDR_KVSEL_PE1D (0x1<<9) //9:9
++#define RG_SSUSB_CDR_KVSEL_PE1H (0x1<<8) //8:8
++#define RG_SSUSB_CDR_KVSEL_U3 (0x1<<7) //7:7
++#define RG_SSUSB_CDR_FBDIV_PE2D (0x7f<<0) //6:0
++
++//U3D_reg33
++#define RG_SSUSB_RX_CMPWD_PE2D (0x1<<26) //26:26
++#define RG_SSUSB_RX_CMPWD_PE2H (0x1<<25) //25:25
++#define RG_SSUSB_RX_CMPWD_PE1D (0x1<<24) //24:24
++#define RG_SSUSB_RX_CMPWD_PE1H (0x1<<23) //23:23
++#define RG_SSUSB_RX_CMPWD_U3 (0x1<<16) //16:16
++#define RG_SSUSB_EQ_RSTEP2_PE2D (0x3<<8) //9:8
++#define RG_SSUSB_EQ_RSTEP2_PE2H (0x3<<6) //7:6
++#define RG_SSUSB_EQ_RSTEP2_PE1D (0x3<<4) //5:4
++#define RG_SSUSB_EQ_RSTEP2_PE1H (0x3<<2) //3:2
++#define RG_SSUSB_EQ_RSTEP2_U3 (0x3<<0) //1:0
++
++
++/* OFFSET */
++
++//U3D_reg0
++#define RG_PCIE_SPEED_PE2D_OFST (24)
++#define RG_PCIE_SPEED_PE2H_OFST (23)
++#define RG_PCIE_SPEED_PE1D_OFST (22)
++#define RG_PCIE_SPEED_PE1H_OFST (21)
++#define RG_PCIE_SPEED_U3_OFST (20)
++#define RG_SSUSB_XTAL_EXT_EN_PE2D_OFST (18)
++#define RG_SSUSB_XTAL_EXT_EN_PE2H_OFST (16)
++#define RG_SSUSB_XTAL_EXT_EN_PE1D_OFST (14)
++#define RG_SSUSB_XTAL_EXT_EN_PE1H_OFST (12)
++#define RG_SSUSB_XTAL_EXT_EN_U3_OFST (10)
++#define RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST (8)
++#define RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST (6)
++#define RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST (4)
++#define RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST (2)
++#define RG_SSUSB_CDR_REFCK_SEL_U3_OFST (0)
++
++//U3D_reg1
++#define RG_USB20_REFCK_SEL_PE2D_OFST (30)
++#define RG_USB20_REFCK_SEL_PE2H_OFST (29)
++#define RG_USB20_REFCK_SEL_PE1D_OFST (28)
++#define RG_USB20_REFCK_SEL_PE1H_OFST (27)
++#define RG_USB20_REFCK_SEL_U3_OFST (26)
++#define RG_PCIE_REFCK_DIV4_PE2D_OFST (25)
++#define RG_PCIE_REFCK_DIV4_PE2H_OFST (24)
++#define RG_PCIE_REFCK_DIV4_PE1D_OFST (18)
++#define RG_PCIE_REFCK_DIV4_PE1H_OFST (17)
++#define RG_PCIE_REFCK_DIV4_U3_OFST (16)
++#define RG_PCIE_MODE_PE2D_OFST (8)
++#define RG_PCIE_MODE_PE2H_OFST (3)
++#define RG_PCIE_MODE_PE1D_OFST (2)
++#define RG_PCIE_MODE_PE1H_OFST (1)
++#define RG_PCIE_MODE_U3_OFST (0)
++
++//U3D_reg4
++#define RG_SSUSB_PLL_DIVEN_PE2D_OFST (22)
++#define RG_SSUSB_PLL_DIVEN_PE2H_OFST (19)
++#define RG_SSUSB_PLL_DIVEN_PE1D_OFST (16)
++#define RG_SSUSB_PLL_DIVEN_PE1H_OFST (13)
++#define RG_SSUSB_PLL_DIVEN_U3_OFST (10)
++#define RG_SSUSB_PLL_BC_PE2D_OFST (8)
++#define RG_SSUSB_PLL_BC_PE2H_OFST (6)
++#define RG_SSUSB_PLL_BC_PE1D_OFST (4)
++#define RG_SSUSB_PLL_BC_PE1H_OFST (2)
++#define RG_SSUSB_PLL_BC_U3_OFST (0)
++
++//U3D_reg5
++#define RG_SSUSB_PLL_BR_PE2D_OFST (27)
++#define RG_SSUSB_PLL_BR_PE2H_OFST (24)
++#define RG_SSUSB_PLL_BR_PE1D_OFST (21)
++#define RG_SSUSB_PLL_BR_PE1H_OFST (18)
++#define RG_SSUSB_PLL_BR_U3_OFST (15)
++#define RG_SSUSB_PLL_IC_PE2D_OFST (12)
++#define RG_SSUSB_PLL_IC_PE2H_OFST (9)
++#define RG_SSUSB_PLL_IC_PE1D_OFST (6)
++#define RG_SSUSB_PLL_IC_PE1H_OFST (3)
++#define RG_SSUSB_PLL_IC_U3_OFST (0)
++
++//U3D_reg6
++#define RG_SSUSB_PLL_IR_PE2D_OFST (24)
++#define RG_SSUSB_PLL_IR_PE2H_OFST (16)
++#define RG_SSUSB_PLL_IR_PE1D_OFST (8)
++#define RG_SSUSB_PLL_IR_PE1H_OFST (4)
++#define RG_SSUSB_PLL_IR_U3_OFST (0)
++
++//U3D_reg7
++#define RG_SSUSB_PLL_BP_PE2D_OFST (24)
++#define RG_SSUSB_PLL_BP_PE2H_OFST (16)
++#define RG_SSUSB_PLL_BP_PE1D_OFST (8)
++#define RG_SSUSB_PLL_BP_PE1H_OFST (4)
++#define RG_SSUSB_PLL_BP_U3_OFST (0)
++
++//U3D_reg8
++#define RG_SSUSB_PLL_FBKSEL_PE2D_OFST (24)
++#define RG_SSUSB_PLL_FBKSEL_PE2H_OFST (16)
++#define RG_SSUSB_PLL_FBKSEL_PE1D_OFST (8)
++#define RG_SSUSB_PLL_FBKSEL_PE1H_OFST (2)
++#define RG_SSUSB_PLL_FBKSEL_U3_OFST (0)
++
++//U3D_reg9
++#define RG_SSUSB_PLL_FBKDIV_PE2H_OFST (24)
++#define RG_SSUSB_PLL_FBKDIV_PE1D_OFST (16)
++#define RG_SSUSB_PLL_FBKDIV_PE1H_OFST (8)
++#define RG_SSUSB_PLL_FBKDIV_U3_OFST (0)
++
++//U3D_reg10
++#define RG_SSUSB_PLL_PREDIV_PE2D_OFST (26)
++#define RG_SSUSB_PLL_PREDIV_PE2H_OFST (24)
++#define RG_SSUSB_PLL_PREDIV_PE1D_OFST (18)
++#define RG_SSUSB_PLL_PREDIV_PE1H_OFST (16)
++#define RG_SSUSB_PLL_PREDIV_U3_OFST (8)
++#define RG_SSUSB_PLL_FBKDIV_PE2D_OFST (0)
++
++//U3D_reg12
++#define RG_SSUSB_PLL_PCW_NCPO_U3_OFST (0)
++
++//U3D_reg13
++#define RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST (0)
++
++//U3D_reg14
++#define RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST (0)
++
++//U3D_reg15
++#define RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST (0)
++
++//U3D_reg16
++#define RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST (0)
++
++//U3D_reg19
++#define RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST (16)
++#define RG_SSUSB_PLL_SSC_DELTA1_U3_OFST (0)
++
++//U3D_reg20
++#define RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST (16)
++#define RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST (0)
++
++//U3D_reg21
++#define RG_SSUSB_PLL_SSC_DELTA_U3_OFST (16)
++#define RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST (0)
++
++//U3D_reg23
++#define RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST (16)
++#define RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST (0)
++
++//U3D_reg25
++#define RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST (16)
++#define RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST (0)
++
++//U3D_reg26
++#define RG_SSUSB_PLL_REFCKDIV_PE2D_OFST (25)
++#define RG_SSUSB_PLL_REFCKDIV_PE2H_OFST (24)
++#define RG_SSUSB_PLL_REFCKDIV_PE1D_OFST (16)
++#define RG_SSUSB_PLL_REFCKDIV_PE1H_OFST (8)
++#define RG_SSUSB_PLL_REFCKDIV_U3_OFST (0)
++
++//U3D_reg28
++#define RG_SSUSB_CDR_BPA_PE2D_OFST (24)
++#define RG_SSUSB_CDR_BPA_PE2H_OFST (16)
++#define RG_SSUSB_CDR_BPA_PE1D_OFST (10)
++#define RG_SSUSB_CDR_BPA_PE1H_OFST (8)
++#define RG_SSUSB_CDR_BPA_U3_OFST (0)
++
++//U3D_reg29
++#define RG_SSUSB_CDR_BPB_PE2D_OFST (24)
++#define RG_SSUSB_CDR_BPB_PE2H_OFST (16)
++#define RG_SSUSB_CDR_BPB_PE1D_OFST (6)
++#define RG_SSUSB_CDR_BPB_PE1H_OFST (3)
++#define RG_SSUSB_CDR_BPB_U3_OFST (0)
++
++//U3D_reg30
++#define RG_SSUSB_CDR_BR_PE2D_OFST (24)
++#define RG_SSUSB_CDR_BR_PE2H_OFST (16)
++#define RG_SSUSB_CDR_BR_PE1D_OFST (6)
++#define RG_SSUSB_CDR_BR_PE1H_OFST (3)
++#define RG_SSUSB_CDR_BR_U3_OFST (0)
++
++//U3D_reg31
++#define RG_SSUSB_CDR_FBDIV_PE2H_OFST (24)
++#define RG_SSUSB_CDR_FBDIV_PE1D_OFST (16)
++#define RG_SSUSB_CDR_FBDIV_PE1H_OFST (8)
++#define RG_SSUSB_CDR_FBDIV_U3_OFST (0)
++
++//U3D_reg32
++#define RG_SSUSB_EQ_RSTEP1_PE2D_OFST (30)
++#define RG_SSUSB_EQ_RSTEP1_PE2H_OFST (28)
++#define RG_SSUSB_EQ_RSTEP1_PE1D_OFST (26)
++#define RG_SSUSB_EQ_RSTEP1_PE1H_OFST (24)
++#define RG_SSUSB_EQ_RSTEP1_U3_OFST (22)
++#define RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST (20)
++#define RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST (18)
++#define RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST (16)
++#define RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST (14)
++#define RG_SSUSB_LFPS_DEGLITCH_U3_OFST (12)
++#define RG_SSUSB_CDR_KVSEL_PE2D_OFST (11)
++#define RG_SSUSB_CDR_KVSEL_PE2H_OFST (10)
++#define RG_SSUSB_CDR_KVSEL_PE1D_OFST (9)
++#define RG_SSUSB_CDR_KVSEL_PE1H_OFST (8)
++#define RG_SSUSB_CDR_KVSEL_U3_OFST (7)
++#define RG_SSUSB_CDR_FBDIV_PE2D_OFST (0)
++
++//U3D_reg33
++#define RG_SSUSB_RX_CMPWD_PE2D_OFST (26)
++#define RG_SSUSB_RX_CMPWD_PE2H_OFST (25)
++#define RG_SSUSB_RX_CMPWD_PE1D_OFST (24)
++#define RG_SSUSB_RX_CMPWD_PE1H_OFST (23)
++#define RG_SSUSB_RX_CMPWD_U3_OFST (16)
++#define RG_SSUSB_EQ_RSTEP2_PE2D_OFST (8)
++#define RG_SSUSB_EQ_RSTEP2_PE2H_OFST (6)
++#define RG_SSUSB_EQ_RSTEP2_PE1D_OFST (4)
++#define RG_SSUSB_EQ_RSTEP2_PE1H_OFST (2)
++#define RG_SSUSB_EQ_RSTEP2_U3_OFST (0)
++
++
++///////////////////////////////////////////////////////////////////////////////
++
++struct u3phyd_reg {
++ //0x0
++ PHY_LE32 phyd_mix0;
++ PHY_LE32 phyd_mix1;
++ PHY_LE32 phyd_lfps0;
++ PHY_LE32 phyd_lfps1;
++ //0x10
++ PHY_LE32 phyd_impcal0;
++ PHY_LE32 phyd_impcal1;
++ PHY_LE32 phyd_txpll0;
++ PHY_LE32 phyd_txpll1;
++ //0x20
++ PHY_LE32 phyd_txpll2;
++ PHY_LE32 phyd_fl0;
++ PHY_LE32 phyd_mix2;
++ PHY_LE32 phyd_rx0;
++ //0x30
++ PHY_LE32 phyd_t2rlb;
++ PHY_LE32 phyd_cppat;
++ PHY_LE32 phyd_mix3;
++ PHY_LE32 phyd_ebufctl;
++ //0x40
++ PHY_LE32 phyd_pipe0;
++ PHY_LE32 phyd_pipe1;
++ PHY_LE32 phyd_mix4;
++ PHY_LE32 phyd_ckgen0;
++ //0x50
++ PHY_LE32 phyd_mix5;
++ PHY_LE32 phyd_reserved;
++ PHY_LE32 phyd_cdr0;
++ PHY_LE32 phyd_cdr1;
++ //0x60
++ PHY_LE32 phyd_pll_0;
++ PHY_LE32 phyd_pll_1;
++ PHY_LE32 phyd_bcn_det_1;
++ PHY_LE32 phyd_bcn_det_2;
++ //0x70
++ PHY_LE32 eq0;
++ PHY_LE32 eq1;
++ PHY_LE32 eq2;
++ PHY_LE32 eq3;
++ //0x80
++ PHY_LE32 eq_eye0;
++ PHY_LE32 eq_eye1;
++ PHY_LE32 eq_eye2;
++ PHY_LE32 eq_dfe0;
++ //0x90
++ PHY_LE32 eq_dfe1;
++ PHY_LE32 eq_dfe2;
++ PHY_LE32 eq_dfe3;
++ PHY_LE32 reserve0;
++ //0xa0
++ PHY_LE32 phyd_mon0;
++ PHY_LE32 phyd_mon1;
++ PHY_LE32 phyd_mon2;
++ PHY_LE32 phyd_mon3;
++ //0xb0
++ PHY_LE32 phyd_mon4;
++ PHY_LE32 phyd_mon5;
++ PHY_LE32 phyd_mon6;
++ PHY_LE32 phyd_mon7;
++ //0xc0
++ PHY_LE32 phya_rx_mon0;
++ PHY_LE32 phya_rx_mon1;
++ PHY_LE32 phya_rx_mon2;
++ PHY_LE32 phya_rx_mon3;
++ //0xd0
++ PHY_LE32 phya_rx_mon4;
++ PHY_LE32 phya_rx_mon5;
++ PHY_LE32 phyd_cppat2;
++ PHY_LE32 eq_eye3;
++ //0xe0
++ PHY_LE32 kband_out;
++ PHY_LE32 kband_out1;
++};
++
++//U3D_PHYD_MIX0
++#define RG_SSUSB_P_P3_TX_NG (0x1<<31) //31:31
++#define RG_SSUSB_TSEQ_EN (0x1<<30) //30:30
++#define RG_SSUSB_TSEQ_POLEN (0x1<<29) //29:29
++#define RG_SSUSB_TSEQ_POL (0x1<<28) //28:28
++#define RG_SSUSB_P_P3_PCLK_NG (0x1<<27) //27:27
++#define RG_SSUSB_TSEQ_TH (0x7<<24) //26:24
++#define RG_SSUSB_PRBS_BERTH (0xff<<16) //23:16
++#define RG_SSUSB_DISABLE_PHY_U2_ON (0x1<<15) //15:15
++#define RG_SSUSB_DISABLE_PHY_U2_OFF (0x1<<14) //14:14
++#define RG_SSUSB_PRBS_EN (0x1<<13) //13:13
++#define RG_SSUSB_BPSLOCK (0x1<<12) //12:12
++#define RG_SSUSB_RTCOMCNT (0xf<<8) //11:8
++#define RG_SSUSB_COMCNT (0xf<<4) //7:4
++#define RG_SSUSB_PRBSEL_CALIB (0xf<<0) //3:0
++
++//U3D_PHYD_MIX1
++#define RG_SSUSB_SLEEP_EN (0x1<<31) //31:31
++#define RG_SSUSB_PRBSEL_PCS (0x7<<28) //30:28
++#define RG_SSUSB_TXLFPS_PRD (0xf<<24) //27:24
++#define RG_SSUSB_P_RX_P0S_CK (0x1<<23) //23:23
++#define RG_SSUSB_P_TX_P0S_CK (0x1<<22) //22:22
++#define RG_SSUSB_PDNCTL (0x3f<<16) //21:16
++#define RG_SSUSB_TX_DRV_EN (0x1<<15) //15:15
++#define RG_SSUSB_TX_DRV_SEL (0x1<<14) //14:14
++#define RG_SSUSB_TX_DRV_DLY (0x3f<<8) //13:8
++#define RG_SSUSB_BERT_EN (0x1<<7) //7:7
++#define RG_SSUSB_SCP_TH (0x7<<4) //6:4
++#define RG_SSUSB_SCP_EN (0x1<<3) //3:3
++#define RG_SSUSB_RXANSIDEC_TEST (0x7<<0) //2:0
++
++//U3D_PHYD_LFPS0
++#define RG_SSUSB_LFPS_PWD (0x1<<30) //30:30
++#define RG_SSUSB_FORCE_LFPS_PWD (0x1<<29) //29:29
++#define RG_SSUSB_RXLFPS_OVF (0x1f<<24) //28:24
++#define RG_SSUSB_P3_ENTRY_SEL (0x1<<23) //23:23
++#define RG_SSUSB_P3_ENTRY (0x1<<22) //22:22
++#define RG_SSUSB_RXLFPS_CDRSEL (0x3<<20) //21:20
++#define RG_SSUSB_RXLFPS_CDRTH (0xf<<16) //19:16
++#define RG_SSUSB_LOCK5G_BLOCK (0x1<<15) //15:15
++#define RG_SSUSB_TFIFO_EXT_D_SEL (0x1<<14) //14:14
++#define RG_SSUSB_TFIFO_NO_EXTEND (0x1<<13) //13:13
++#define RG_SSUSB_RXLFPS_LOB (0x1f<<8) //12:8
++#define RG_SSUSB_TXLFPS_EN (0x1<<7) //7:7
++#define RG_SSUSB_TXLFPS_SEL (0x1<<6) //6:6
++#define RG_SSUSB_RXLFPS_CDRLOCK (0x1<<5) //5:5
++#define RG_SSUSB_RXLFPS_UPB (0x1f<<0) //4:0
++
++//U3D_PHYD_LFPS1
++#define RG_SSUSB_RX_IMP_BIAS (0xf<<28) //31:28
++#define RG_SSUSB_TX_IMP_BIAS (0xf<<24) //27:24
++#define RG_SSUSB_FWAKE_TH (0x3f<<16) //21:16
++#define RG_SSUSB_RXLFPS_UDF (0x1f<<8) //12:8
++#define RG_SSUSB_RXLFPS_P0IDLETH (0xff<<0) //7:0
++
++//U3D_PHYD_IMPCAL0
++#define RG_SSUSB_FORCE_TX_IMPSEL (0x1<<31) //31:31
++#define RG_SSUSB_TX_IMPCAL_EN (0x1<<30) //30:30
++#define RG_SSUSB_FORCE_TX_IMPCAL_EN (0x1<<29) //29:29
++#define RG_SSUSB_TX_IMPSEL (0x1f<<24) //28:24
++#define RG_SSUSB_TX_IMPCAL_CALCYC (0x3f<<16) //21:16
++#define RG_SSUSB_TX_IMPCAL_STBCYC (0x1f<<10) //14:10
++#define RG_SSUSB_TX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
++
++//U3D_PHYD_IMPCAL1
++#define RG_SSUSB_FORCE_RX_IMPSEL (0x1<<31) //31:31
++#define RG_SSUSB_RX_IMPCAL_EN (0x1<<30) //30:30
++#define RG_SSUSB_FORCE_RX_IMPCAL_EN (0x1<<29) //29:29
++#define RG_SSUSB_RX_IMPSEL (0x1f<<24) //28:24
++#define RG_SSUSB_RX_IMPCAL_CALCYC (0x3f<<16) //21:16
++#define RG_SSUSB_RX_IMPCAL_STBCYC (0x1f<<10) //14:10
++#define RG_SSUSB_RX_IMPCAL_CYCCNT (0x3ff<<0) //9:0
++
++//U3D_PHYD_TXPLL0
++#define RG_SSUSB_TXPLL_DDSEN_CYC (0x1f<<27) //31:27
++#define RG_SSUSB_TXPLL_ON (0x1<<26) //26:26
++#define RG_SSUSB_FORCE_TXPLLON (0x1<<25) //25:25
++#define RG_SSUSB_TXPLL_STBCYC (0x1ff<<16) //24:16
++#define RG_SSUSB_TXPLL_NCPOCHG_CYC (0xf<<12) //15:12
++#define RG_SSUSB_TXPLL_NCPOEN_CYC (0x3<<10) //11:10
++#define RG_SSUSB_TXPLL_DDSRSTB_CYC (0x7<<0) //2:0
++
++//U3D_PHYD_TXPLL1
++#define RG_SSUSB_PLL_NCPO_EN (0x1<<31) //31:31
++#define RG_SSUSB_PLL_FIFO_START_MAN (0x1<<30) //30:30
++#define RG_SSUSB_PLL_NCPO_CHG (0x1<<28) //28:28
++#define RG_SSUSB_PLL_DDS_RSTB (0x1<<27) //27:27
++#define RG_SSUSB_PLL_DDS_PWDB (0x1<<26) //26:26
++#define RG_SSUSB_PLL_DDSEN (0x1<<25) //25:25
++#define RG_SSUSB_PLL_AUTOK_VCO (0x1<<24) //24:24
++#define RG_SSUSB_PLL_PWD (0x1<<23) //23:23
++#define RG_SSUSB_RX_AFE_PWD (0x1<<22) //22:22
++#define RG_SSUSB_PLL_TCADJ (0x3f<<16) //21:16
++#define RG_SSUSB_FORCE_CDR_TCADJ (0x1<<15) //15:15
++#define RG_SSUSB_FORCE_CDR_AUTOK_VCO (0x1<<14) //14:14
++#define RG_SSUSB_FORCE_CDR_PWD (0x1<<13) //13:13
++#define RG_SSUSB_FORCE_PLL_NCPO_EN (0x1<<12) //12:12
++#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN (0x1<<11) //11:11
++#define RG_SSUSB_FORCE_PLL_NCPO_CHG (0x1<<9) //9:9
++#define RG_SSUSB_FORCE_PLL_DDS_RSTB (0x1<<8) //8:8
++#define RG_SSUSB_FORCE_PLL_DDS_PWDB (0x1<<7) //7:7
++#define RG_SSUSB_FORCE_PLL_DDSEN (0x1<<6) //6:6
++#define RG_SSUSB_FORCE_PLL_TCADJ (0x1<<5) //5:5
++#define RG_SSUSB_FORCE_PLL_AUTOK_VCO (0x1<<4) //4:4
++#define RG_SSUSB_FORCE_PLL_PWD (0x1<<3) //3:3
++#define RG_SSUSB_FLT_1_DISPERR_B (0x1<<2) //2:2
++
++//U3D_PHYD_TXPLL2
++#define RG_SSUSB_TX_LFPS_EN (0x1<<31) //31:31
++#define RG_SSUSB_FORCE_TX_LFPS_EN (0x1<<30) //30:30
++#define RG_SSUSB_TX_LFPS (0x1<<29) //29:29
++#define RG_SSUSB_FORCE_TX_LFPS (0x1<<28) //28:28
++#define RG_SSUSB_RXPLL_STB (0x1<<27) //27:27
++#define RG_SSUSB_TXPLL_STB (0x1<<26) //26:26
++#define RG_SSUSB_FORCE_RXPLL_STB (0x1<<25) //25:25
++#define RG_SSUSB_FORCE_TXPLL_STB (0x1<<24) //24:24
++#define RG_SSUSB_RXPLL_REFCKSEL (0x1<<16) //16:16
++#define RG_SSUSB_RXPLL_STBMODE (0x1<<11) //11:11
++#define RG_SSUSB_RXPLL_ON (0x1<<10) //10:10
++#define RG_SSUSB_FORCE_RXPLLON (0x1<<9) //9:9
++#define RG_SSUSB_FORCE_RX_AFE_PWD (0x1<<8) //8:8
++#define RG_SSUSB_CDR_AUTOK_VCO (0x1<<7) //7:7
++#define RG_SSUSB_CDR_PWD (0x1<<6) //6:6
++#define RG_SSUSB_CDR_TCADJ (0x3f<<0) //5:0
++
++//U3D_PHYD_FL0
++#define RG_SSUSB_RX_FL_TARGET (0xffff<<16) //31:16
++#define RG_SSUSB_RX_FL_CYCLECNT (0xffff<<0) //15:0
++
++//U3D_PHYD_MIX2
++#define RG_SSUSB_RX_EQ_RST (0x1<<31) //31:31
++#define RG_SSUSB_RX_EQ_RST_SEL (0x1<<30) //30:30
++#define RG_SSUSB_RXVAL_RST (0x1<<29) //29:29
++#define RG_SSUSB_RXVAL_CNT (0x1f<<24) //28:24
++#define RG_SSUSB_CDROS_EN (0x1<<18) //18:18
++#define RG_SSUSB_CDR_LCKOP (0x3<<16) //17:16
++#define RG_SSUSB_RX_FL_LOCKTH (0xf<<8) //11:8
++#define RG_SSUSB_RX_FL_OFFSET (0xff<<0) //7:0
++
++//U3D_PHYD_RX0
++#define RG_SSUSB_T2RLB_BERTH (0xff<<24) //31:24
++#define RG_SSUSB_T2RLB_PAT (0xff<<16) //23:16
++#define RG_SSUSB_T2RLB_EN (0x1<<15) //15:15
++#define RG_SSUSB_T2RLB_BPSCRAMB (0x1<<14) //14:14
++#define RG_SSUSB_T2RLB_SERIAL (0x1<<13) //13:13
++#define RG_SSUSB_T2RLB_MODE (0x3<<11) //12:11
++#define RG_SSUSB_RX_SAOSC_EN (0x1<<10) //10:10
++#define RG_SSUSB_RX_SAOSC_EN_SEL (0x1<<9) //9:9
++#define RG_SSUSB_RX_DFE_OPTION (0x1<<8) //8:8
++#define RG_SSUSB_RX_DFE_EN (0x1<<7) //7:7
++#define RG_SSUSB_RX_DFE_EN_SEL (0x1<<6) //6:6
++#define RG_SSUSB_RX_EQ_EN (0x1<<5) //5:5
++#define RG_SSUSB_RX_EQ_EN_SEL (0x1<<4) //4:4
++#define RG_SSUSB_RX_SAOSC_RST (0x1<<3) //3:3
++#define RG_SSUSB_RX_SAOSC_RST_SEL (0x1<<2) //2:2
++#define RG_SSUSB_RX_DFE_RST (0x1<<1) //1:1
++#define RG_SSUSB_RX_DFE_RST_SEL (0x1<<0) //0:0
++
++//U3D_PHYD_T2RLB
++#define RG_SSUSB_EQTRAIN_CH_MODE (0x1<<28) //28:28
++#define RG_SSUSB_PRB_OUT_CPPAT (0x1<<27) //27:27
++#define RG_SSUSB_BPANSIENC (0x1<<26) //26:26
++#define RG_SSUSB_VALID_EN (0x1<<25) //25:25
++#define RG_SSUSB_EBUF_SRST (0x1<<24) //24:24
++#define RG_SSUSB_K_EMP (0xf<<20) //23:20
++#define RG_SSUSB_K_FUL (0xf<<16) //19:16
++#define RG_SSUSB_T2RLB_BDATRST (0xf<<12) //15:12
++#define RG_SSUSB_P_T2RLB_SKP_EN (0x1<<10) //10:10
++#define RG_SSUSB_T2RLB_PATMODE (0x3<<8) //9:8
++#define RG_SSUSB_T2RLB_TSEQCNT (0xff<<0) //7:0
++
++//U3D_PHYD_CPPAT
++#define RG_SSUSB_CPPAT_PROGRAM_EN (0x1<<24) //24:24
++#define RG_SSUSB_CPPAT_TOZ (0x3<<21) //22:21
++#define RG_SSUSB_CPPAT_PRBS_EN (0x1<<20) //20:20
++#define RG_SSUSB_CPPAT_OUT_TMP2 (0xf<<16) //19:16
++#define RG_SSUSB_CPPAT_OUT_TMP1 (0xff<<8) //15:8
++#define RG_SSUSB_CPPAT_OUT_TMP0 (0xff<<0) //7:0
++
++//U3D_PHYD_MIX3
++#define RG_SSUSB_CDR_TCADJ_MINUS (0x1<<31) //31:31
++#define RG_SSUSB_P_CDROS_EN (0x1<<30) //30:30
++#define RG_SSUSB_P_P2_TX_DRV_DIS (0x1<<28) //28:28
++#define RG_SSUSB_CDR_TCADJ_OFFSET (0x7<<24) //26:24
++#define RG_SSUSB_PLL_TCADJ_MINUS (0x1<<23) //23:23
++#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN (0x1<<20) //20:20
++#define RG_SSUSB_PLL_BIAS_LPF_EN (0x1<<19) //19:19
++#define RG_SSUSB_PLL_TCADJ_OFFSET (0x7<<16) //18:16
++#define RG_SSUSB_FORCE_PLL_SSCEN (0x1<<15) //15:15
++#define RG_SSUSB_PLL_SSCEN (0x1<<14) //14:14
++#define RG_SSUSB_FORCE_CDR_PI_PWD (0x1<<13) //13:13
++#define RG_SSUSB_CDR_PI_PWD (0x1<<12) //12:12
++#define RG_SSUSB_CDR_PI_MODE (0x1<<11) //11:11
++#define RG_SSUSB_TXPLL_SSCEN_CYC (0x3ff<<0) //9:0
++
++//U3D_PHYD_EBUFCTL
++#define RG_SSUSB_EBUFCTL (0xffffffff<<0) //31:0
++
++//U3D_PHYD_PIPE0
++#define RG_SSUSB_RXTERMINATION (0x1<<30) //30:30
++#define RG_SSUSB_RXEQTRAINING (0x1<<29) //29:29
++#define RG_SSUSB_RXPOLARITY (0x1<<28) //28:28
++#define RG_SSUSB_TXDEEMPH (0x3<<26) //27:26
++#define RG_SSUSB_POWERDOWN (0x3<<24) //25:24
++#define RG_SSUSB_TXONESZEROS (0x1<<23) //23:23
++#define RG_SSUSB_TXELECIDLE (0x1<<22) //22:22
++#define RG_SSUSB_TXDETECTRX (0x1<<21) //21:21
++#define RG_SSUSB_PIPE_SEL (0x1<<20) //20:20
++#define RG_SSUSB_TXDATAK (0xf<<16) //19:16
++#define RG_SSUSB_CDR_STABLE_SEL (0x1<<15) //15:15
++#define RG_SSUSB_CDR_STABLE (0x1<<14) //14:14
++#define RG_SSUSB_CDR_RSTB_SEL (0x1<<13) //13:13
++#define RG_SSUSB_CDR_RSTB (0x1<<12) //12:12
++#define RG_SSUSB_P_ERROR_SEL (0x3<<4) //5:4
++#define RG_SSUSB_TXMARGIN (0x7<<1) //3:1
++#define RG_SSUSB_TXCOMPLIANCE (0x1<<0) //0:0
++
++//U3D_PHYD_PIPE1
++#define RG_SSUSB_TXDATA (0xffffffff<<0) //31:0
++
++//U3D_PHYD_MIX4
++#define RG_SSUSB_CDROS_CNT (0x3f<<24) //29:24
++#define RG_SSUSB_T2RLB_BER_EN (0x1<<16) //16:16
++#define RG_SSUSB_T2RLB_BER_RATE (0xffff<<0) //15:0
++
++//U3D_PHYD_CKGEN0
++#define RG_SSUSB_RFIFO_IMPLAT (0x1<<27) //27:27
++#define RG_SSUSB_TFIFO_PSEL (0x7<<24) //26:24
++#define RG_SSUSB_CKGEN_PSEL (0x3<<8) //9:8
++#define RG_SSUSB_RXCK_INV (0x1<<0) //0:0
++
++//U3D_PHYD_MIX5
++#define RG_SSUSB_PRB_SEL (0xffff<<16) //31:16
++#define RG_SSUSB_RXPLL_STBCYC (0x7ff<<0) //10:0
++
++//U3D_PHYD_RESERVED
++#define RG_SSUSB_PHYD_RESERVE (0xffffffff<<0) //31:0
++//#define RG_SSUSB_RX_SIGDET_SEL (0x1<<11)
++//#define RG_SSUSB_RX_SIGDET_EN (0x1<<12)
++//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL (0x1<<9)
++//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN (0x1<<10)
++
++//U3D_PHYD_CDR0
++#define RG_SSUSB_CDR_BIC_LTR (0xf<<28) //31:28
++#define RG_SSUSB_CDR_BIC_LTD0 (0xf<<24) //27:24
++#define RG_SSUSB_CDR_BC_LTD1 (0x1f<<16) //20:16
++#define RG_SSUSB_CDR_BC_LTR (0x1f<<8) //12:8
++#define RG_SSUSB_CDR_BC_LTD0 (0x1f<<0) //4:0
++
++//U3D_PHYD_CDR1
++#define RG_SSUSB_CDR_BIR_LTD1 (0x1f<<24) //28:24
++#define RG_SSUSB_CDR_BIR_LTR (0x1f<<16) //20:16
++#define RG_SSUSB_CDR_BIR_LTD0 (0x1f<<8) //12:8
++#define RG_SSUSB_CDR_BW_SEL (0x3<<6) //7:6
++#define RG_SSUSB_CDR_BIC_LTD1 (0xf<<0) //3:0
++
++//U3D_PHYD_PLL_0
++#define RG_SSUSB_FORCE_CDR_BAND_5G (0x1<<28) //28:28
++#define RG_SSUSB_FORCE_CDR_BAND_2P5G (0x1<<27) //27:27
++#define RG_SSUSB_FORCE_PLL_BAND_5G (0x1<<26) //26:26
++#define RG_SSUSB_FORCE_PLL_BAND_2P5G (0x1<<25) //25:25
++#define RG_SSUSB_P_EQ_T_SEL (0x3ff<<15) //24:15
++#define RG_SSUSB_PLL_ISO_EN_CYC (0x3ff<<5) //14:5
++#define RG_SSUSB_PLLBAND_RECAL (0x1<<4) //4:4
++#define RG_SSUSB_PLL_DDS_ISO_EN (0x1<<3) //3:3
++#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN (0x1<<2) //2:2
++#define RG_SSUSB_PLL_DDS_PWR_ON (0x1<<1) //1:1
++#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON (0x1<<0) //0:0
++
++//U3D_PHYD_PLL_1
++#define RG_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
++#define RG_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
++#define RG_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
++#define RG_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
++
++//U3D_PHYD_BCN_DET_1
++#define RG_SSUSB_P_BCN_OBS_PRD (0xffff<<16) //31:16
++#define RG_SSUSB_U_BCN_OBS_PRD (0xffff<<0) //15:0
++
++//U3D_PHYD_BCN_DET_2
++#define RG_SSUSB_P_BCN_OBS_SEL (0xfff<<16) //27:16
++#define RG_SSUSB_BCN_DET_DIS (0x1<<12) //12:12
++#define RG_SSUSB_U_BCN_OBS_SEL (0xfff<<0) //11:0
++
++//U3D_EQ0
++#define RG_SSUSB_EQ_DLHL_LFI (0x7f<<24) //30:24
++#define RG_SSUSB_EQ_DHHL_LFI (0x7f<<16) //22:16
++#define RG_SSUSB_EQ_DD0HOS_LFI (0x7f<<8) //14:8
++#define RG_SSUSB_EQ_DD0LOS_LFI (0x7f<<0) //6:0
++
++//U3D_EQ1
++#define RG_SSUSB_EQ_DD1HOS_LFI (0x7f<<24) //30:24
++#define RG_SSUSB_EQ_DD1LOS_LFI (0x7f<<16) //22:16
++#define RG_SSUSB_EQ_DE0OS_LFI (0x7f<<8) //14:8
++#define RG_SSUSB_EQ_DE1OS_LFI (0x7f<<0) //6:0
++
++//U3D_EQ2
++#define RG_SSUSB_EQ_DLHLOS_LFI (0x7f<<24) //30:24
++#define RG_SSUSB_EQ_DHHLOS_LFI (0x7f<<16) //22:16
++#define RG_SSUSB_EQ_STOPTIME (0x1<<14) //14:14
++#define RG_SSUSB_EQ_DHHL_LF_SEL (0x7<<11) //13:11
++#define RG_SSUSB_EQ_DSAOS_LF_SEL (0x7<<8) //10:8
++#define RG_SSUSB_EQ_STARTTIME (0x3<<6) //7:6
++#define RG_SSUSB_EQ_DLEQ_LF_SEL (0x7<<3) //5:3
++#define RG_SSUSB_EQ_DLHL_LF_SEL (0x7<<0) //2:0
++
++//U3D_EQ3
++#define RG_SSUSB_EQ_DLEQ_LFI_GEN2 (0xf<<28) //31:28
++#define RG_SSUSB_EQ_DLEQ_LFI_GEN1 (0xf<<24) //27:24
++#define RG_SSUSB_EQ_DEYE0OS_LFI (0x7f<<16) //22:16
++#define RG_SSUSB_EQ_DEYE1OS_LFI (0x7f<<8) //14:8
++#define RG_SSUSB_EQ_TRI_DET_EN (0x1<<7) //7:7
++#define RG_SSUSB_EQ_TRI_DET_TH (0x7f<<0) //6:0
++
++//U3D_EQ_EYE0
++#define RG_SSUSB_EQ_EYE_XOFFSET (0x7f<<25) //31:25
++#define RG_SSUSB_EQ_EYE_MON_EN (0x1<<24) //24:24
++#define RG_SSUSB_EQ_EYE0_Y (0x7f<<16) //22:16
++#define RG_SSUSB_EQ_EYE1_Y (0x7f<<8) //14:8
++#define RG_SSUSB_EQ_PILPO_ROUT (0x1<<7) //7:7
++#define RG_SSUSB_EQ_PI_KPGAIN (0x7<<4) //6:4
++#define RG_SSUSB_EQ_EYE_CNT_EN (0x1<<3) //3:3
++
++//U3D_EQ_EYE1
++#define RG_SSUSB_EQ_SIGDET (0x7f<<24) //30:24
++#define RG_SSUSB_EQ_EYE_MASK (0x3ff<<7) //16:7
++
++//U3D_EQ_EYE2
++#define RG_SSUSB_EQ_RX500M_CK_SEL (0x1<<31) //31:31
++#define RG_SSUSB_EQ_SD_CNT1 (0x3f<<24) //29:24
++#define RG_SSUSB_EQ_ISIFLAG_SEL (0x3<<22) //23:22
++#define RG_SSUSB_EQ_SD_CNT0 (0x3f<<16) //21:16
++
++//U3D_EQ_DFE0
++#define RG_SSUSB_EQ_LEQMAX (0xf<<28) //31:28
++#define RG_SSUSB_EQ_DFEX_EN (0x1<<27) //27:27
++#define RG_SSUSB_EQ_DFEX_LF_SEL (0x7<<24) //26:24
++#define RG_SSUSB_EQ_CHK_EYE_H (0x1<<23) //23:23
++#define RG_SSUSB_EQ_PIEYE_INI (0x7f<<16) //22:16
++#define RG_SSUSB_EQ_PI90_INI (0x7f<<8) //14:8
++#define RG_SSUSB_EQ_PI0_INI (0x7f<<0) //6:0
++
++//U3D_EQ_DFE1
++#define RG_SSUSB_EQ_REV (0xffff<<16) //31:16
++#define RG_SSUSB_EQ_DFEYEN_DUR (0x7<<12) //14:12
++#define RG_SSUSB_EQ_DFEXEN_DUR (0x7<<8) //10:8
++#define RG_SSUSB_EQ_DFEX_RST (0x1<<7) //7:7
++#define RG_SSUSB_EQ_GATED_RXD_B (0x1<<6) //6:6
++#define RG_SSUSB_EQ_PI90CK_SEL (0x3<<4) //5:4
++#define RG_SSUSB_EQ_DFEX_DIS (0x1<<2) //2:2
++#define RG_SSUSB_EQ_DFEYEN_STOP_DIS (0x1<<1) //1:1
++#define RG_SSUSB_EQ_DFEXEN_SEL (0x1<<0) //0:0
++
++//U3D_EQ_DFE2
++#define RG_SSUSB_EQ_MON_SEL (0x1f<<24) //28:24
++#define RG_SSUSB_EQ_LEQOSC_DLYCNT (0x7<<16) //18:16
++#define RG_SSUSB_EQ_DLEQOS_LFI (0x1f<<8) //12:8
++#define RG_SSUSB_EQ_LEQ_STOP_TO (0x3<<0) //1:0
++
++//U3D_EQ_DFE3
++#define RG_SSUSB_EQ_RESERVED (0xffffffff<<0) //31:0
++
++//U3D_PHYD_MON0
++#define RGS_SSUSB_BERT_BERC (0xffff<<16) //31:16
++#define RGS_SSUSB_LFPS (0xf<<12) //15:12
++#define RGS_SSUSB_TRAINDEC (0x7<<8) //10:8
++#define RGS_SSUSB_SCP_PAT (0xff<<0) //7:0
++
++//U3D_PHYD_MON1
++#define RGS_SSUSB_RX_FL_OUT (0xffff<<0) //15:0
++
++//U3D_PHYD_MON2
++#define RGS_SSUSB_T2RLB_ERRCNT (0xffff<<16) //31:16
++#define RGS_SSUSB_RETRACK (0xf<<12) //15:12
++#define RGS_SSUSB_RXPLL_LOCK (0x1<<10) //10:10
++#define RGS_SSUSB_CDR_VCOCAL_CPLT_D (0x1<<9) //9:9
++#define RGS_SSUSB_PLL_VCOCAL_CPLT_D (0x1<<8) //8:8
++#define RGS_SSUSB_PDNCTL (0xff<<0) //7:0
++
++//U3D_PHYD_MON3
++#define RGS_SSUSB_TSEQ_ERRCNT (0xffff<<16) //31:16
++#define RGS_SSUSB_PRBS_ERRCNT (0xffff<<0) //15:0
++
++//U3D_PHYD_MON4
++#define RGS_SSUSB_RX_LSLOCK_CNT (0xf<<24) //27:24
++#define RGS_SSUSB_SCP_DETCNT (0xff<<16) //23:16
++#define RGS_SSUSB_TSEQ_DETCNT (0xffff<<0) //15:0
++
++//U3D_PHYD_MON5
++#define RGS_SSUSB_EBUFMSG (0xffff<<16) //31:16
++#define RGS_SSUSB_BERT_LOCK (0x1<<15) //15:15
++#define RGS_SSUSB_SCP_DET (0x1<<14) //14:14
++#define RGS_SSUSB_TSEQ_DET (0x1<<13) //13:13
++#define RGS_SSUSB_EBUF_UDF (0x1<<12) //12:12
++#define RGS_SSUSB_EBUF_OVF (0x1<<11) //11:11
++#define RGS_SSUSB_PRBS_PASSTH (0x1<<10) //10:10
++#define RGS_SSUSB_PRBS_PASS (0x1<<9) //9:9
++#define RGS_SSUSB_PRBS_LOCK (0x1<<8) //8:8
++#define RGS_SSUSB_T2RLB_ERR (0x1<<6) //6:6
++#define RGS_SSUSB_T2RLB_PASSTH (0x1<<5) //5:5
++#define RGS_SSUSB_T2RLB_PASS (0x1<<4) //4:4
++#define RGS_SSUSB_T2RLB_LOCK (0x1<<3) //3:3
++#define RGS_SSUSB_RX_IMPCAL_DONE (0x1<<2) //2:2
++#define RGS_SSUSB_TX_IMPCAL_DONE (0x1<<1) //1:1
++#define RGS_SSUSB_RXDETECTED (0x1<<0) //0:0
++
++//U3D_PHYD_MON6
++#define RGS_SSUSB_SIGCAL_DONE (0x1<<30) //30:30
++#define RGS_SSUSB_SIGCAL_CAL_OUT (0x1<<29) //29:29
++#define RGS_SSUSB_SIGCAL_OFFSET (0x1f<<24) //28:24
++#define RGS_SSUSB_RX_IMP_SEL (0x1f<<16) //20:16
++#define RGS_SSUSB_TX_IMP_SEL (0x1f<<8) //12:8
++#define RGS_SSUSB_TFIFO_MSG (0xf<<4) //7:4
++#define RGS_SSUSB_RFIFO_MSG (0xf<<0) //3:0
++
++//U3D_PHYD_MON7
++#define RGS_SSUSB_FT_OUT (0xff<<8) //15:8
++#define RGS_SSUSB_PRB_OUT (0xff<<0) //7:0
++
++//U3D_PHYA_RX_MON0
++#define RGS_SSUSB_EQ_DCLEQ (0xf<<24) //27:24
++#define RGS_SSUSB_EQ_DCD0H (0x7f<<16) //22:16
++#define RGS_SSUSB_EQ_DCD0L (0x7f<<8) //14:8
++#define RGS_SSUSB_EQ_DCD1H (0x7f<<0) //6:0
++
++//U3D_PHYA_RX_MON1
++#define RGS_SSUSB_EQ_DCD1L (0x7f<<24) //30:24
++#define RGS_SSUSB_EQ_DCE0 (0x7f<<16) //22:16
++#define RGS_SSUSB_EQ_DCE1 (0x7f<<8) //14:8
++#define RGS_SSUSB_EQ_DCHHL (0x7f<<0) //6:0
++
++//U3D_PHYA_RX_MON2
++#define RGS_SSUSB_EQ_LEQ_STOP (0x1<<31) //31:31
++#define RGS_SSUSB_EQ_DCLHL (0x7f<<24) //30:24
++#define RGS_SSUSB_EQ_STATUS (0xff<<16) //23:16
++#define RGS_SSUSB_EQ_DCEYE0 (0x7f<<8) //14:8
++#define RGS_SSUSB_EQ_DCEYE1 (0x7f<<0) //6:0
++
++//U3D_PHYA_RX_MON3
++#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0 (0xfffff<<0) //19:0
++
++//U3D_PHYA_RX_MON4
++#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1 (0xfffff<<0) //19:0
++
++//U3D_PHYA_RX_MON5
++#define RGS_SSUSB_EQ_DCLEQOS (0x1f<<8) //12:8
++#define RGS_SSUSB_EQ_EYE_CNT_RDY (0x1<<7) //7:7
++#define RGS_SSUSB_EQ_PILPO (0x7f<<0) //6:0
++
++//U3D_PHYD_CPPAT2
++#define RG_SSUSB_CPPAT_OUT_H_TMP2 (0xf<<16) //19:16
++#define RG_SSUSB_CPPAT_OUT_H_TMP1 (0xff<<8) //15:8
++#define RG_SSUSB_CPPAT_OUT_H_TMP0 (0xff<<0) //7:0
++
++//U3D_EQ_EYE3
++#define RG_SSUSB_EQ_LEQ_SHIFT (0x7<<24) //26:24
++#define RG_SSUSB_EQ_EYE_CNT (0xfffff<<0) //19:0
++
++//U3D_KBAND_OUT
++#define RGS_SSUSB_CDR_BAND_5G (0xff<<24) //31:24
++#define RGS_SSUSB_CDR_BAND_2P5G (0xff<<16) //23:16
++#define RGS_SSUSB_PLL_BAND_5G (0xff<<8) //15:8
++#define RGS_SSUSB_PLL_BAND_2P5G (0xff<<0) //7:0
++
++//U3D_KBAND_OUT1
++#define RGS_SSUSB_CDR_VCOCAL_FAIL (0x1<<24) //24:24
++#define RGS_SSUSB_CDR_VCOCAL_STATE (0xff<<16) //23:16
++#define RGS_SSUSB_PLL_VCOCAL_FAIL (0x1<<8) //8:8
++#define RGS_SSUSB_PLL_VCOCAL_STATE (0xff<<0) //7:0
++
++
++/* OFFSET */
++
++//U3D_PHYD_MIX0
++#define RG_SSUSB_P_P3_TX_NG_OFST (31)
++#define RG_SSUSB_TSEQ_EN_OFST (30)
++#define RG_SSUSB_TSEQ_POLEN_OFST (29)
++#define RG_SSUSB_TSEQ_POL_OFST (28)
++#define RG_SSUSB_P_P3_PCLK_NG_OFST (27)
++#define RG_SSUSB_TSEQ_TH_OFST (24)
++#define RG_SSUSB_PRBS_BERTH_OFST (16)
++#define RG_SSUSB_DISABLE_PHY_U2_ON_OFST (15)
++#define RG_SSUSB_DISABLE_PHY_U2_OFF_OFST (14)
++#define RG_SSUSB_PRBS_EN_OFST (13)
++#define RG_SSUSB_BPSLOCK_OFST (12)
++#define RG_SSUSB_RTCOMCNT_OFST (8)
++#define RG_SSUSB_COMCNT_OFST (4)
++#define RG_SSUSB_PRBSEL_CALIB_OFST (0)
++
++//U3D_PHYD_MIX1
++#define RG_SSUSB_SLEEP_EN_OFST (31)
++#define RG_SSUSB_PRBSEL_PCS_OFST (28)
++#define RG_SSUSB_TXLFPS_PRD_OFST (24)
++#define RG_SSUSB_P_RX_P0S_CK_OFST (23)
++#define RG_SSUSB_P_TX_P0S_CK_OFST (22)
++#define RG_SSUSB_PDNCTL_OFST (16)
++#define RG_SSUSB_TX_DRV_EN_OFST (15)
++#define RG_SSUSB_TX_DRV_SEL_OFST (14)
++#define RG_SSUSB_TX_DRV_DLY_OFST (8)
++#define RG_SSUSB_BERT_EN_OFST (7)
++#define RG_SSUSB_SCP_TH_OFST (4)
++#define RG_SSUSB_SCP_EN_OFST (3)
++#define RG_SSUSB_RXANSIDEC_TEST_OFST (0)
++
++//U3D_PHYD_LFPS0
++#define RG_SSUSB_LFPS_PWD_OFST (30)
++#define RG_SSUSB_FORCE_LFPS_PWD_OFST (29)
++#define RG_SSUSB_RXLFPS_OVF_OFST (24)
++#define RG_SSUSB_P3_ENTRY_SEL_OFST (23)
++#define RG_SSUSB_P3_ENTRY_OFST (22)
++#define RG_SSUSB_RXLFPS_CDRSEL_OFST (20)
++#define RG_SSUSB_RXLFPS_CDRTH_OFST (16)
++#define RG_SSUSB_LOCK5G_BLOCK_OFST (15)
++#define RG_SSUSB_TFIFO_EXT_D_SEL_OFST (14)
++#define RG_SSUSB_TFIFO_NO_EXTEND_OFST (13)
++#define RG_SSUSB_RXLFPS_LOB_OFST (8)
++#define RG_SSUSB_TXLFPS_EN_OFST (7)
++#define RG_SSUSB_TXLFPS_SEL_OFST (6)
++#define RG_SSUSB_RXLFPS_CDRLOCK_OFST (5)
++#define RG_SSUSB_RXLFPS_UPB_OFST (0)
++
++//U3D_PHYD_LFPS1
++#define RG_SSUSB_RX_IMP_BIAS_OFST (28)
++#define RG_SSUSB_TX_IMP_BIAS_OFST (24)
++#define RG_SSUSB_FWAKE_TH_OFST (16)
++#define RG_SSUSB_RXLFPS_UDF_OFST (8)
++#define RG_SSUSB_RXLFPS_P0IDLETH_OFST (0)
++
++//U3D_PHYD_IMPCAL0
++#define RG_SSUSB_FORCE_TX_IMPSEL_OFST (31)
++#define RG_SSUSB_TX_IMPCAL_EN_OFST (30)
++#define RG_SSUSB_FORCE_TX_IMPCAL_EN_OFST (29)
++#define RG_SSUSB_TX_IMPSEL_OFST (24)
++#define RG_SSUSB_TX_IMPCAL_CALCYC_OFST (16)
++#define RG_SSUSB_TX_IMPCAL_STBCYC_OFST (10)
++#define RG_SSUSB_TX_IMPCAL_CYCCNT_OFST (0)
++
++//U3D_PHYD_IMPCAL1
++#define RG_SSUSB_FORCE_RX_IMPSEL_OFST (31)
++#define RG_SSUSB_RX_IMPCAL_EN_OFST (30)
++#define RG_SSUSB_FORCE_RX_IMPCAL_EN_OFST (29)
++#define RG_SSUSB_RX_IMPSEL_OFST (24)
++#define RG_SSUSB_RX_IMPCAL_CALCYC_OFST (16)
++#define RG_SSUSB_RX_IMPCAL_STBCYC_OFST (10)
++#define RG_SSUSB_RX_IMPCAL_CYCCNT_OFST (0)
++
++//U3D_PHYD_TXPLL0
++#define RG_SSUSB_TXPLL_DDSEN_CYC_OFST (27)
++#define RG_SSUSB_TXPLL_ON_OFST (26)
++#define RG_SSUSB_FORCE_TXPLLON_OFST (25)
++#define RG_SSUSB_TXPLL_STBCYC_OFST (16)
++#define RG_SSUSB_TXPLL_NCPOCHG_CYC_OFST (12)
++#define RG_SSUSB_TXPLL_NCPOEN_CYC_OFST (10)
++#define RG_SSUSB_TXPLL_DDSRSTB_CYC_OFST (0)
++
++//U3D_PHYD_TXPLL1
++#define RG_SSUSB_PLL_NCPO_EN_OFST (31)
++#define RG_SSUSB_PLL_FIFO_START_MAN_OFST (30)
++#define RG_SSUSB_PLL_NCPO_CHG_OFST (28)
++#define RG_SSUSB_PLL_DDS_RSTB_OFST (27)
++#define RG_SSUSB_PLL_DDS_PWDB_OFST (26)
++#define RG_SSUSB_PLL_DDSEN_OFST (25)
++#define RG_SSUSB_PLL_AUTOK_VCO_OFST (24)
++#define RG_SSUSB_PLL_PWD_OFST (23)
++#define RG_SSUSB_RX_AFE_PWD_OFST (22)
++#define RG_SSUSB_PLL_TCADJ_OFST (16)
++#define RG_SSUSB_FORCE_CDR_TCADJ_OFST (15)
++#define RG_SSUSB_FORCE_CDR_AUTOK_VCO_OFST (14)
++#define RG_SSUSB_FORCE_CDR_PWD_OFST (13)
++#define RG_SSUSB_FORCE_PLL_NCPO_EN_OFST (12)
++#define RG_SSUSB_FORCE_PLL_FIFO_START_MAN_OFST (11)
++#define RG_SSUSB_FORCE_PLL_NCPO_CHG_OFST (9)
++#define RG_SSUSB_FORCE_PLL_DDS_RSTB_OFST (8)
++#define RG_SSUSB_FORCE_PLL_DDS_PWDB_OFST (7)
++#define RG_SSUSB_FORCE_PLL_DDSEN_OFST (6)
++#define RG_SSUSB_FORCE_PLL_TCADJ_OFST (5)
++#define RG_SSUSB_FORCE_PLL_AUTOK_VCO_OFST (4)
++#define RG_SSUSB_FORCE_PLL_PWD_OFST (3)
++#define RG_SSUSB_FLT_1_DISPERR_B_OFST (2)
++
++//U3D_PHYD_TXPLL2
++#define RG_SSUSB_TX_LFPS_EN_OFST (31)
++#define RG_SSUSB_FORCE_TX_LFPS_EN_OFST (30)
++#define RG_SSUSB_TX_LFPS_OFST (29)
++#define RG_SSUSB_FORCE_TX_LFPS_OFST (28)
++#define RG_SSUSB_RXPLL_STB_OFST (27)
++#define RG_SSUSB_TXPLL_STB_OFST (26)
++#define RG_SSUSB_FORCE_RXPLL_STB_OFST (25)
++#define RG_SSUSB_FORCE_TXPLL_STB_OFST (24)
++#define RG_SSUSB_RXPLL_REFCKSEL_OFST (16)
++#define RG_SSUSB_RXPLL_STBMODE_OFST (11)
++#define RG_SSUSB_RXPLL_ON_OFST (10)
++#define RG_SSUSB_FORCE_RXPLLON_OFST (9)
++#define RG_SSUSB_FORCE_RX_AFE_PWD_OFST (8)
++#define RG_SSUSB_CDR_AUTOK_VCO_OFST (7)
++#define RG_SSUSB_CDR_PWD_OFST (6)
++#define RG_SSUSB_CDR_TCADJ_OFST (0)
++
++//U3D_PHYD_FL0
++#define RG_SSUSB_RX_FL_TARGET_OFST (16)
++#define RG_SSUSB_RX_FL_CYCLECNT_OFST (0)
++
++//U3D_PHYD_MIX2
++#define RG_SSUSB_RX_EQ_RST_OFST (31)
++#define RG_SSUSB_RX_EQ_RST_SEL_OFST (30)
++#define RG_SSUSB_RXVAL_RST_OFST (29)
++#define RG_SSUSB_RXVAL_CNT_OFST (24)
++#define RG_SSUSB_CDROS_EN_OFST (18)
++#define RG_SSUSB_CDR_LCKOP_OFST (16)
++#define RG_SSUSB_RX_FL_LOCKTH_OFST (8)
++#define RG_SSUSB_RX_FL_OFFSET_OFST (0)
++
++//U3D_PHYD_RX0
++#define RG_SSUSB_T2RLB_BERTH_OFST (24)
++#define RG_SSUSB_T2RLB_PAT_OFST (16)
++#define RG_SSUSB_T2RLB_EN_OFST (15)
++#define RG_SSUSB_T2RLB_BPSCRAMB_OFST (14)
++#define RG_SSUSB_T2RLB_SERIAL_OFST (13)
++#define RG_SSUSB_T2RLB_MODE_OFST (11)
++#define RG_SSUSB_RX_SAOSC_EN_OFST (10)
++#define RG_SSUSB_RX_SAOSC_EN_SEL_OFST (9)
++#define RG_SSUSB_RX_DFE_OPTION_OFST (8)
++#define RG_SSUSB_RX_DFE_EN_OFST (7)
++#define RG_SSUSB_RX_DFE_EN_SEL_OFST (6)
++#define RG_SSUSB_RX_EQ_EN_OFST (5)
++#define RG_SSUSB_RX_EQ_EN_SEL_OFST (4)
++#define RG_SSUSB_RX_SAOSC_RST_OFST (3)
++#define RG_SSUSB_RX_SAOSC_RST_SEL_OFST (2)
++#define RG_SSUSB_RX_DFE_RST_OFST (1)
++#define RG_SSUSB_RX_DFE_RST_SEL_OFST (0)
++
++//U3D_PHYD_T2RLB
++#define RG_SSUSB_EQTRAIN_CH_MODE_OFST (28)
++#define RG_SSUSB_PRB_OUT_CPPAT_OFST (27)
++#define RG_SSUSB_BPANSIENC_OFST (26)
++#define RG_SSUSB_VALID_EN_OFST (25)
++#define RG_SSUSB_EBUF_SRST_OFST (24)
++#define RG_SSUSB_K_EMP_OFST (20)
++#define RG_SSUSB_K_FUL_OFST (16)
++#define RG_SSUSB_T2RLB_BDATRST_OFST (12)
++#define RG_SSUSB_P_T2RLB_SKP_EN_OFST (10)
++#define RG_SSUSB_T2RLB_PATMODE_OFST (8)
++#define RG_SSUSB_T2RLB_TSEQCNT_OFST (0)
++
++//U3D_PHYD_CPPAT
++#define RG_SSUSB_CPPAT_PROGRAM_EN_OFST (24)
++#define RG_SSUSB_CPPAT_TOZ_OFST (21)
++#define RG_SSUSB_CPPAT_PRBS_EN_OFST (20)
++#define RG_SSUSB_CPPAT_OUT_TMP2_OFST (16)
++#define RG_SSUSB_CPPAT_OUT_TMP1_OFST (8)
++#define RG_SSUSB_CPPAT_OUT_TMP0_OFST (0)
++
++//U3D_PHYD_MIX3
++#define RG_SSUSB_CDR_TCADJ_MINUS_OFST (31)
++#define RG_SSUSB_P_CDROS_EN_OFST (30)
++#define RG_SSUSB_P_P2_TX_DRV_DIS_OFST (28)
++#define RG_SSUSB_CDR_TCADJ_OFFSET_OFST (24)
++#define RG_SSUSB_PLL_TCADJ_MINUS_OFST (23)
++#define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN_OFST (20)
++#define RG_SSUSB_PLL_BIAS_LPF_EN_OFST (19)
++#define RG_SSUSB_PLL_TCADJ_OFFSET_OFST (16)
++#define RG_SSUSB_FORCE_PLL_SSCEN_OFST (15)
++#define RG_SSUSB_PLL_SSCEN_OFST (14)
++#define RG_SSUSB_FORCE_CDR_PI_PWD_OFST (13)
++#define RG_SSUSB_CDR_PI_PWD_OFST (12)
++#define RG_SSUSB_CDR_PI_MODE_OFST (11)
++#define RG_SSUSB_TXPLL_SSCEN_CYC_OFST (0)
++
++//U3D_PHYD_EBUFCTL
++#define RG_SSUSB_EBUFCTL_OFST (0)
++
++//U3D_PHYD_PIPE0
++#define RG_SSUSB_RXTERMINATION_OFST (30)
++#define RG_SSUSB_RXEQTRAINING_OFST (29)
++#define RG_SSUSB_RXPOLARITY_OFST (28)
++#define RG_SSUSB_TXDEEMPH_OFST (26)
++#define RG_SSUSB_POWERDOWN_OFST (24)
++#define RG_SSUSB_TXONESZEROS_OFST (23)
++#define RG_SSUSB_TXELECIDLE_OFST (22)
++#define RG_SSUSB_TXDETECTRX_OFST (21)
++#define RG_SSUSB_PIPE_SEL_OFST (20)
++#define RG_SSUSB_TXDATAK_OFST (16)
++#define RG_SSUSB_CDR_STABLE_SEL_OFST (15)
++#define RG_SSUSB_CDR_STABLE_OFST (14)
++#define RG_SSUSB_CDR_RSTB_SEL_OFST (13)
++#define RG_SSUSB_CDR_RSTB_OFST (12)
++#define RG_SSUSB_P_ERROR_SEL_OFST (4)
++#define RG_SSUSB_TXMARGIN_OFST (1)
++#define RG_SSUSB_TXCOMPLIANCE_OFST (0)
++
++//U3D_PHYD_PIPE1
++#define RG_SSUSB_TXDATA_OFST (0)
++
++//U3D_PHYD_MIX4
++#define RG_SSUSB_CDROS_CNT_OFST (24)
++#define RG_SSUSB_T2RLB_BER_EN_OFST (16)
++#define RG_SSUSB_T2RLB_BER_RATE_OFST (0)
++
++//U3D_PHYD_CKGEN0
++#define RG_SSUSB_RFIFO_IMPLAT_OFST (27)
++#define RG_SSUSB_TFIFO_PSEL_OFST (24)
++#define RG_SSUSB_CKGEN_PSEL_OFST (8)
++#define RG_SSUSB_RXCK_INV_OFST (0)
++
++//U3D_PHYD_MIX5
++#define RG_SSUSB_PRB_SEL_OFST (16)
++#define RG_SSUSB_RXPLL_STBCYC_OFST (0)
++
++//U3D_PHYD_RESERVED
++#define RG_SSUSB_PHYD_RESERVE_OFST (0)
++//#define RG_SSUSB_RX_SIGDET_SEL_OFST (11)
++//#define RG_SSUSB_RX_SIGDET_EN_OFST (12)
++//#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL_OFST (9)
++//#define RG_SSUSB_RX_PI_CAL_MANUAL_EN_OFST (10)
++
++//U3D_PHYD_CDR0
++#define RG_SSUSB_CDR_BIC_LTR_OFST (28)
++#define RG_SSUSB_CDR_BIC_LTD0_OFST (24)
++#define RG_SSUSB_CDR_BC_LTD1_OFST (16)
++#define RG_SSUSB_CDR_BC_LTR_OFST (8)
++#define RG_SSUSB_CDR_BC_LTD0_OFST (0)
++
++//U3D_PHYD_CDR1
++#define RG_SSUSB_CDR_BIR_LTD1_OFST (24)
++#define RG_SSUSB_CDR_BIR_LTR_OFST (16)
++#define RG_SSUSB_CDR_BIR_LTD0_OFST (8)
++#define RG_SSUSB_CDR_BW_SEL_OFST (6)
++#define RG_SSUSB_CDR_BIC_LTD1_OFST (0)
++
++//U3D_PHYD_PLL_0
++#define RG_SSUSB_FORCE_CDR_BAND_5G_OFST (28)
++#define RG_SSUSB_FORCE_CDR_BAND_2P5G_OFST (27)
++#define RG_SSUSB_FORCE_PLL_BAND_5G_OFST (26)
++#define RG_SSUSB_FORCE_PLL_BAND_2P5G_OFST (25)
++#define RG_SSUSB_P_EQ_T_SEL_OFST (15)
++#define RG_SSUSB_PLL_ISO_EN_CYC_OFST (5)
++#define RG_SSUSB_PLLBAND_RECAL_OFST (4)
++#define RG_SSUSB_PLL_DDS_ISO_EN_OFST (3)
++#define RG_SSUSB_FORCE_PLL_DDS_ISO_EN_OFST (2)
++#define RG_SSUSB_PLL_DDS_PWR_ON_OFST (1)
++#define RG_SSUSB_FORCE_PLL_DDS_PWR_ON_OFST (0)
++
++//U3D_PHYD_PLL_1
++#define RG_SSUSB_CDR_BAND_5G_OFST (24)
++#define RG_SSUSB_CDR_BAND_2P5G_OFST (16)
++#define RG_SSUSB_PLL_BAND_5G_OFST (8)
++#define RG_SSUSB_PLL_BAND_2P5G_OFST (0)
++
++//U3D_PHYD_BCN_DET_1
++#define RG_SSUSB_P_BCN_OBS_PRD_OFST (16)
++#define RG_SSUSB_U_BCN_OBS_PRD_OFST (0)
++
++//U3D_PHYD_BCN_DET_2
++#define RG_SSUSB_P_BCN_OBS_SEL_OFST (16)
++#define RG_SSUSB_BCN_DET_DIS_OFST (12)
++#define RG_SSUSB_U_BCN_OBS_SEL_OFST (0)
++
++//U3D_EQ0
++#define RG_SSUSB_EQ_DLHL_LFI_OFST (24)
++#define RG_SSUSB_EQ_DHHL_LFI_OFST (16)
++#define RG_SSUSB_EQ_DD0HOS_LFI_OFST (8)
++#define RG_SSUSB_EQ_DD0LOS_LFI_OFST (0)
++
++//U3D_EQ1
++#define RG_SSUSB_EQ_DD1HOS_LFI_OFST (24)
++#define RG_SSUSB_EQ_DD1LOS_LFI_OFST (16)
++#define RG_SSUSB_EQ_DE0OS_LFI_OFST (8)
++#define RG_SSUSB_EQ_DE1OS_LFI_OFST (0)
++
++//U3D_EQ2
++#define RG_SSUSB_EQ_DLHLOS_LFI_OFST (24)
++#define RG_SSUSB_EQ_DHHLOS_LFI_OFST (16)
++#define RG_SSUSB_EQ_STOPTIME_OFST (14)
++#define RG_SSUSB_EQ_DHHL_LF_SEL_OFST (11)
++#define RG_SSUSB_EQ_DSAOS_LF_SEL_OFST (8)
++#define RG_SSUSB_EQ_STARTTIME_OFST (6)
++#define RG_SSUSB_EQ_DLEQ_LF_SEL_OFST (3)
++#define RG_SSUSB_EQ_DLHL_LF_SEL_OFST (0)
++
++//U3D_EQ3
++#define RG_SSUSB_EQ_DLEQ_LFI_GEN2_OFST (28)
++#define RG_SSUSB_EQ_DLEQ_LFI_GEN1_OFST (24)
++#define RG_SSUSB_EQ_DEYE0OS_LFI_OFST (16)
++#define RG_SSUSB_EQ_DEYE1OS_LFI_OFST (8)
++#define RG_SSUSB_EQ_TRI_DET_EN_OFST (7)
++#define RG_SSUSB_EQ_TRI_DET_TH_OFST (0)
++
++//U3D_EQ_EYE0
++#define RG_SSUSB_EQ_EYE_XOFFSET_OFST (25)
++#define RG_SSUSB_EQ_EYE_MON_EN_OFST (24)
++#define RG_SSUSB_EQ_EYE0_Y_OFST (16)
++#define RG_SSUSB_EQ_EYE1_Y_OFST (8)
++#define RG_SSUSB_EQ_PILPO_ROUT_OFST (7)
++#define RG_SSUSB_EQ_PI_KPGAIN_OFST (4)
++#define RG_SSUSB_EQ_EYE_CNT_EN_OFST (3)
++
++//U3D_EQ_EYE1
++#define RG_SSUSB_EQ_SIGDET_OFST (24)
++#define RG_SSUSB_EQ_EYE_MASK_OFST (7)
++
++//U3D_EQ_EYE2
++#define RG_SSUSB_EQ_RX500M_CK_SEL_OFST (31)
++#define RG_SSUSB_EQ_SD_CNT1_OFST (24)
++#define RG_SSUSB_EQ_ISIFLAG_SEL_OFST (22)
++#define RG_SSUSB_EQ_SD_CNT0_OFST (16)
++
++//U3D_EQ_DFE0
++#define RG_SSUSB_EQ_LEQMAX_OFST (28)
++#define RG_SSUSB_EQ_DFEX_EN_OFST (27)
++#define RG_SSUSB_EQ_DFEX_LF_SEL_OFST (24)
++#define RG_SSUSB_EQ_CHK_EYE_H_OFST (23)
++#define RG_SSUSB_EQ_PIEYE_INI_OFST (16)
++#define RG_SSUSB_EQ_PI90_INI_OFST (8)
++#define RG_SSUSB_EQ_PI0_INI_OFST (0)
++
++//U3D_EQ_DFE1
++#define RG_SSUSB_EQ_REV_OFST (16)
++#define RG_SSUSB_EQ_DFEYEN_DUR_OFST (12)
++#define RG_SSUSB_EQ_DFEXEN_DUR_OFST (8)
++#define RG_SSUSB_EQ_DFEX_RST_OFST (7)
++#define RG_SSUSB_EQ_GATED_RXD_B_OFST (6)
++#define RG_SSUSB_EQ_PI90CK_SEL_OFST (4)
++#define RG_SSUSB_EQ_DFEX_DIS_OFST (2)
++#define RG_SSUSB_EQ_DFEYEN_STOP_DIS_OFST (1)
++#define RG_SSUSB_EQ_DFEXEN_SEL_OFST (0)
++
++//U3D_EQ_DFE2
++#define RG_SSUSB_EQ_MON_SEL_OFST (24)
++#define RG_SSUSB_EQ_LEQOSC_DLYCNT_OFST (16)
++#define RG_SSUSB_EQ_DLEQOS_LFI_OFST (8)
++#define RG_SSUSB_EQ_LEQ_STOP_TO_OFST (0)
++
++//U3D_EQ_DFE3
++#define RG_SSUSB_EQ_RESERVED_OFST (0)
++
++//U3D_PHYD_MON0
++#define RGS_SSUSB_BERT_BERC_OFST (16)
++#define RGS_SSUSB_LFPS_OFST (12)
++#define RGS_SSUSB_TRAINDEC_OFST (8)
++#define RGS_SSUSB_SCP_PAT_OFST (0)
++
++//U3D_PHYD_MON1
++#define RGS_SSUSB_RX_FL_OUT_OFST (0)
++
++//U3D_PHYD_MON2
++#define RGS_SSUSB_T2RLB_ERRCNT_OFST (16)
++#define RGS_SSUSB_RETRACK_OFST (12)
++#define RGS_SSUSB_RXPLL_LOCK_OFST (10)
++#define RGS_SSUSB_CDR_VCOCAL_CPLT_D_OFST (9)
++#define RGS_SSUSB_PLL_VCOCAL_CPLT_D_OFST (8)
++#define RGS_SSUSB_PDNCTL_OFST (0)
++
++//U3D_PHYD_MON3
++#define RGS_SSUSB_TSEQ_ERRCNT_OFST (16)
++#define RGS_SSUSB_PRBS_ERRCNT_OFST (0)
++
++//U3D_PHYD_MON4
++#define RGS_SSUSB_RX_LSLOCK_CNT_OFST (24)
++#define RGS_SSUSB_SCP_DETCNT_OFST (16)
++#define RGS_SSUSB_TSEQ_DETCNT_OFST (0)
++
++//U3D_PHYD_MON5
++#define RGS_SSUSB_EBUFMSG_OFST (16)
++#define RGS_SSUSB_BERT_LOCK_OFST (15)
++#define RGS_SSUSB_SCP_DET_OFST (14)
++#define RGS_SSUSB_TSEQ_DET_OFST (13)
++#define RGS_SSUSB_EBUF_UDF_OFST (12)
++#define RGS_SSUSB_EBUF_OVF_OFST (11)
++#define RGS_SSUSB_PRBS_PASSTH_OFST (10)
++#define RGS_SSUSB_PRBS_PASS_OFST (9)
++#define RGS_SSUSB_PRBS_LOCK_OFST (8)
++#define RGS_SSUSB_T2RLB_ERR_OFST (6)
++#define RGS_SSUSB_T2RLB_PASSTH_OFST (5)
++#define RGS_SSUSB_T2RLB_PASS_OFST (4)
++#define RGS_SSUSB_T2RLB_LOCK_OFST (3)
++#define RGS_SSUSB_RX_IMPCAL_DONE_OFST (2)
++#define RGS_SSUSB_TX_IMPCAL_DONE_OFST (1)
++#define RGS_SSUSB_RXDETECTED_OFST (0)
++
++//U3D_PHYD_MON6
++#define RGS_SSUSB_SIGCAL_DONE_OFST (30)
++#define RGS_SSUSB_SIGCAL_CAL_OUT_OFST (29)
++#define RGS_SSUSB_SIGCAL_OFFSET_OFST (24)
++#define RGS_SSUSB_RX_IMP_SEL_OFST (16)
++#define RGS_SSUSB_TX_IMP_SEL_OFST (8)
++#define RGS_SSUSB_TFIFO_MSG_OFST (4)
++#define RGS_SSUSB_RFIFO_MSG_OFST (0)
++
++//U3D_PHYD_MON7
++#define RGS_SSUSB_FT_OUT_OFST (8)
++#define RGS_SSUSB_PRB_OUT_OFST (0)
++
++//U3D_PHYA_RX_MON0
++#define RGS_SSUSB_EQ_DCLEQ_OFST (24)
++#define RGS_SSUSB_EQ_DCD0H_OFST (16)
++#define RGS_SSUSB_EQ_DCD0L_OFST (8)
++#define RGS_SSUSB_EQ_DCD1H_OFST (0)
++
++//U3D_PHYA_RX_MON1
++#define RGS_SSUSB_EQ_DCD1L_OFST (24)
++#define RGS_SSUSB_EQ_DCE0_OFST (16)
++#define RGS_SSUSB_EQ_DCE1_OFST (8)
++#define RGS_SSUSB_EQ_DCHHL_OFST (0)
++
++//U3D_PHYA_RX_MON2
++#define RGS_SSUSB_EQ_LEQ_STOP_OFST (31)
++#define RGS_SSUSB_EQ_DCLHL_OFST (24)
++#define RGS_SSUSB_EQ_STATUS_OFST (16)
++#define RGS_SSUSB_EQ_DCEYE0_OFST (8)
++#define RGS_SSUSB_EQ_DCEYE1_OFST (0)
++
++//U3D_PHYA_RX_MON3
++#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST (0)
++
++//U3D_PHYA_RX_MON4
++#define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST (0)
++
++//U3D_PHYA_RX_MON5
++#define RGS_SSUSB_EQ_DCLEQOS_OFST (8)
++#define RGS_SSUSB_EQ_EYE_CNT_RDY_OFST (7)
++#define RGS_SSUSB_EQ_PILPO_OFST (0)
++
++//U3D_PHYD_CPPAT2
++#define RG_SSUSB_CPPAT_OUT_H_TMP2_OFST (16)
++#define RG_SSUSB_CPPAT_OUT_H_TMP1_OFST (8)
++#define RG_SSUSB_CPPAT_OUT_H_TMP0_OFST (0)
++
++//U3D_EQ_EYE3
++#define RG_SSUSB_EQ_LEQ_SHIFT_OFST (24)
++#define RG_SSUSB_EQ_EYE_CNT_OFST (0)
++
++//U3D_KBAND_OUT
++#define RGS_SSUSB_CDR_BAND_5G_OFST (24)
++#define RGS_SSUSB_CDR_BAND_2P5G_OFST (16)
++#define RGS_SSUSB_PLL_BAND_5G_OFST (8)
++#define RGS_SSUSB_PLL_BAND_2P5G_OFST (0)
++
++//U3D_KBAND_OUT1
++#define RGS_SSUSB_CDR_VCOCAL_FAIL_OFST (24)
++#define RGS_SSUSB_CDR_VCOCAL_STATE_OFST (16)
++#define RGS_SSUSB_PLL_VCOCAL_FAIL_OFST (8)
++#define RGS_SSUSB_PLL_VCOCAL_STATE_OFST (0)
++
++
++///////////////////////////////////////////////////////////////////////////////
++
++struct u3phyd_bank2_reg {
++ //0x0
++ PHY_LE32 b2_phyd_top1;
++ PHY_LE32 b2_phyd_top2;
++ PHY_LE32 b2_phyd_top3;
++ PHY_LE32 b2_phyd_top4;
++ //0x10
++ PHY_LE32 b2_phyd_top5;
++ PHY_LE32 b2_phyd_top6;
++ PHY_LE32 b2_phyd_top7;
++ PHY_LE32 b2_phyd_p_sigdet1;
++ //0x20
++ PHY_LE32 b2_phyd_p_sigdet2;
++ PHY_LE32 b2_phyd_p_sigdet_cal1;
++ PHY_LE32 b2_phyd_rxdet1;
++ PHY_LE32 b2_phyd_rxdet2;
++ //0x30
++ PHY_LE32 b2_phyd_misc0;
++ PHY_LE32 b2_phyd_misc2;
++ PHY_LE32 b2_phyd_misc3;
++ PHY_LE32 reserve0;
++ //0x40
++ PHY_LE32 b2_rosc_0;
++ PHY_LE32 b2_rosc_1;
++ PHY_LE32 b2_rosc_2;
++ PHY_LE32 b2_rosc_3;
++ //0x50
++ PHY_LE32 b2_rosc_4;
++ PHY_LE32 b2_rosc_5;
++ PHY_LE32 b2_rosc_6;
++ PHY_LE32 b2_rosc_7;
++ //0x60
++ PHY_LE32 b2_rosc_8;
++ PHY_LE32 b2_rosc_9;
++ PHY_LE32 b2_rosc_a;
++ PHY_LE32 reserve1;
++ //0x70~0xd0
++ PHY_LE32 reserve2[28];
++ //0xe0
++ PHY_LE32 phyd_version;
++ PHY_LE32 phyd_model;
++};
++
++//U3D_B2_PHYD_TOP1
++#define RG_SSUSB_PCIE2_K_EMP (0xf<<28) //31:28
++#define RG_SSUSB_PCIE2_K_FUL (0xf<<24) //27:24
++#define RG_SSUSB_TX_EIDLE_LP_EN (0x1<<17) //17:17
++#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN (0x1<<16) //16:16
++#define RG_SSUSB_SIGDET_EN (0x1<<15) //15:15
++#define RG_SSUSB_FORCE_SIGDET_EN (0x1<<14) //14:14
++#define RG_SSUSB_CLKRX_EN (0x1<<13) //13:13
++#define RG_SSUSB_FORCE_CLKRX_EN (0x1<<12) //12:12
++#define RG_SSUSB_CLKTX_EN (0x1<<11) //11:11
++#define RG_SSUSB_FORCE_CLKTX_EN (0x1<<10) //10:10
++#define RG_SSUSB_CLK_REQ_N_I (0x1<<9) //9:9
++#define RG_SSUSB_FORCE_CLK_REQ_N_I (0x1<<8) //8:8
++#define RG_SSUSB_RATE (0x1<<6) //6:6
++#define RG_SSUSB_FORCE_RATE (0x1<<5) //5:5
++#define RG_SSUSB_PCIE_MODE_SEL (0x1<<4) //4:4
++#define RG_SSUSB_FORCE_PCIE_MODE_SEL (0x1<<3) //3:3
++#define RG_SSUSB_PHY_MODE (0x3<<1) //2:1
++#define RG_SSUSB_FORCE_PHY_MODE (0x1<<0) //0:0
++
++//U3D_B2_PHYD_TOP2
++#define RG_SSUSB_FORCE_IDRV_6DB (0x1<<30) //30:30
++#define RG_SSUSB_IDRV_6DB (0x3f<<24) //29:24
++#define RG_SSUSB_FORCE_IDEM_3P5DB (0x1<<22) //22:22
++#define RG_SSUSB_IDEM_3P5DB (0x3f<<16) //21:16
++#define RG_SSUSB_FORCE_IDRV_3P5DB (0x1<<14) //14:14
++#define RG_SSUSB_IDRV_3P5DB (0x3f<<8) //13:8
++#define RG_SSUSB_FORCE_IDRV_0DB (0x1<<6) //6:6
++#define RG_SSUSB_IDRV_0DB (0x3f<<0) //5:0
++
++//U3D_B2_PHYD_TOP3
++#define RG_SSUSB_TX_BIASI (0x7<<25) //27:25
++#define RG_SSUSB_FORCE_TX_BIASI_EN (0x1<<24) //24:24
++#define RG_SSUSB_TX_BIASI_EN (0x1<<16) //16:16
++#define RG_SSUSB_FORCE_TX_BIASI (0x1<<13) //13:13
++#define RG_SSUSB_FORCE_IDEM_6DB (0x1<<8) //8:8
++#define RG_SSUSB_IDEM_6DB (0x3f<<0) //5:0
++
++//U3D_B2_PHYD_TOP4
++#define RG_SSUSB_G1_CDR_BIC_LTR (0xf<<28) //31:28
++#define RG_SSUSB_G1_CDR_BIC_LTD0 (0xf<<24) //27:24
++#define RG_SSUSB_G1_CDR_BC_LTD1 (0x1f<<16) //20:16
++#define RG_SSUSB_G1_CDR_BC_LTR (0x1f<<8) //12:8
++#define RG_SSUSB_G1_CDR_BC_LTD0 (0x1f<<0) //4:0
++
++//U3D_B2_PHYD_TOP5
++#define RG_SSUSB_G1_CDR_BIR_LTD1 (0x1f<<24) //28:24
++#define RG_SSUSB_G1_CDR_BIR_LTR (0x1f<<16) //20:16
++#define RG_SSUSB_G1_CDR_BIR_LTD0 (0x1f<<8) //12:8
++#define RG_SSUSB_G1_CDR_BIC_LTD1 (0xf<<0) //3:0
++
++//U3D_B2_PHYD_TOP6
++#define RG_SSUSB_G2_CDR_BIC_LTR (0xf<<28) //31:28
++#define RG_SSUSB_G2_CDR_BIC_LTD0 (0xf<<24) //27:24
++#define RG_SSUSB_G2_CDR_BC_LTD1 (0x1f<<16) //20:16
++#define RG_SSUSB_G2_CDR_BC_LTR (0x1f<<8) //12:8
++#define RG_SSUSB_G2_CDR_BC_LTD0 (0x1f<<0) //4:0
++
++//U3D_B2_PHYD_TOP7
++#define RG_SSUSB_G2_CDR_BIR_LTD1 (0x1f<<24) //28:24
++#define RG_SSUSB_G2_CDR_BIR_LTR (0x1f<<16) //20:16
++#define RG_SSUSB_G2_CDR_BIR_LTD0 (0x1f<<8) //12:8
++#define RG_SSUSB_G2_CDR_BIC_LTD1 (0xf<<0) //3:0
++
++//U3D_B2_PHYD_P_SIGDET1
++#define RG_SSUSB_P_SIGDET_FLT_DIS (0x1<<31) //31:31
++#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL (0x7f<<24) //30:24
++#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL (0x7f<<16) //22:16
++#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL (0x7f<<8) //14:8
++#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL (0x7f<<0) //6:0
++
++//U3D_B2_PHYD_P_SIGDET2
++#define RG_SSUSB_P_SIGDET_RX_VAL_S (0x1<<29) //29:29
++#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL (0x1<<28) //28:28
++#define RG_SSUSB_P_SIGDET_L0_EXIT_S (0x1<<27) //27:27
++#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S (0x3<<25) //26:25
++#define RG_SSUSB_P_SIGDET_L0S_EXIT_S (0x1<<24) //24:24
++#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S (0x1<<16) //16:16
++#define RG_SSUSB_P_SIGDET_PRB_SEL (0x1<<10) //10:10
++#define RG_SSUSB_P_SIGDET_BK_SIG_T (0x3<<8) //9:8
++#define RG_SSUSB_P_SIGDET_P2_RXLFPS (0x1<<6) //6:6
++#define RG_SSUSB_P_SIGDET_NON_BK_AD (0x1<<5) //5:5
++#define RG_SSUSB_P_SIGDET_BK_B_RXEQ (0x1<<4) //4:4
++#define RG_SSUSB_P_SIGDET_G2_KO_SEL (0x3<<2) //3:2
++#define RG_SSUSB_P_SIGDET_G1_KO_SEL (0x3<<0) //1:0
++
++//U3D_B2_PHYD_P_SIGDET_CAL1
++#define RG_SSUSB_P_SIGDET_CAL_OFFSET (0x1f<<24) //28:24
++#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET (0x1<<16) //16:16
++#define RG_SSUSB_P_SIGDET_CAL_EN (0x1<<8) //8:8
++#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN (0x1<<3) //3:3
++#define RG_SSUSB_P_SIGDET_FLT_EN (0x1<<2) //2:2
++#define RG_SSUSB_P_SIGDET_SAMPLE_PRD (0x1<<1) //1:1
++#define RG_SSUSB_P_SIGDET_REK (0x1<<0) //0:0
++
++//U3D_B2_PHYD_RXDET1
++#define RG_SSUSB_RXDET_PRB_SEL (0x1<<31) //31:31
++#define RG_SSUSB_FORCE_CMDET (0x1<<30) //30:30
++#define RG_SSUSB_RXDET_EN (0x1<<29) //29:29
++#define RG_SSUSB_FORCE_RXDET_EN (0x1<<28) //28:28
++#define RG_SSUSB_RXDET_K_TWICE (0x1<<27) //27:27
++#define RG_SSUSB_RXDET_STB3_SET (0x1ff<<18) //26:18
++#define RG_SSUSB_RXDET_STB2_SET (0x1ff<<9) //17:9
++#define RG_SSUSB_RXDET_STB1_SET (0x1ff<<0) //8:0
++
++//U3D_B2_PHYD_RXDET2
++#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN (0x1<<31) //31:31
++#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN (0x1<<30) //30:30
++#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN (0x1<<29) //29:29
++#define RG_SSUSB_PDN_T_SEL (0x3<<18) //19:18
++#define RG_SSUSB_RXDET_STB3_SET_P3 (0x1ff<<9) //17:9
++#define RG_SSUSB_RXDET_STB2_SET_P3 (0x1ff<<0) //8:0
++
++//U3D_B2_PHYD_MISC0
++#define RG_SSUSB_FORCE_PLL_DDS_HF_EN (0x1<<22) //22:22
++#define RG_SSUSB_PLL_DDS_HF_EN_MAN (0x1<<21) //21:21
++#define RG_SSUSB_RXLFPS_ENTXDRV (0x1<<20) //20:20
++#define RG_SSUSB_RX_FL_UNLOCKTH (0xf<<16) //19:16
++#define RG_SSUSB_LFPS_PSEL (0x1<<15) //15:15
++#define RG_SSUSB_RX_SIGDET_EN (0x1<<14) //14:14
++#define RG_SSUSB_RX_SIGDET_EN_SEL (0x1<<13) //13:13
++#define RG_SSUSB_RX_PI_CAL_EN (0x1<<12) //12:12
++#define RG_SSUSB_RX_PI_CAL_EN_SEL (0x1<<11) //11:11
++#define RG_SSUSB_P3_CLS_CK_SEL (0x1<<10) //10:10
++#define RG_SSUSB_T2RLB_PSEL (0x3<<8) //9:8
++#define RG_SSUSB_PPCTL_PSEL (0x7<<5) //7:5
++#define RG_SSUSB_PHYD_TX_DATA_INV (0x1<<4) //4:4
++#define RG_SSUSB_BERTLB_PSEL (0x3<<2) //3:2
++#define RG_SSUSB_RETRACK_DIS (0x1<<1) //1:1
++#define RG_SSUSB_PPERRCNT_CLR (0x1<<0) //0:0
++
++//U3D_B2_PHYD_MISC2
++#define RG_SSUSB_FRC_PLL_DDS_PREDIV2 (0x1<<31) //31:31
++#define RG_SSUSB_FRC_PLL_DDS_IADJ (0xf<<27) //30:27
++#define RG_SSUSB_P_SIGDET_125FILTER (0x1<<26) //26:26
++#define RG_SSUSB_P_SIGDET_RST_FILTER (0x1<<25) //25:25
++#define RG_SSUSB_P_SIGDET_EID_USE_RAW (0x1<<24) //24:24
++#define RG_SSUSB_P_SIGDET_LTD_USE_RAW (0x1<<23) //23:23
++#define RG_SSUSB_EIDLE_BF_RXDET (0x1<<22) //22:22
++#define RG_SSUSB_EIDLE_LP_STBCYC (0x1ff<<13) //21:13
++#define RG_SSUSB_TX_EIDLE_LP_POSTDLY (0x3f<<7) //12:7
++#define RG_SSUSB_TX_EIDLE_LP_PREDLY (0x3f<<1) //6:1
++#define RG_SSUSB_TX_EIDLE_LP_EN_ADV (0x1<<0) //0:0
++
++//U3D_B2_PHYD_MISC3
++#define RGS_SSUSB_DDS_CALIB_C_STATE (0x7<<16) //18:16
++#define RGS_SSUSB_PPERRCNT (0xffff<<0) //15:0
++
++//U3D_B2_ROSC_0
++#define RG_SSUSB_RING_OSC_CNTEND (0x1ff<<23) //31:23
++#define RG_SSUSB_XTAL_OSC_CNTEND (0x7f<<16) //22:16
++#define RG_SSUSB_RING_OSC_EN (0x1<<3) //3:3
++#define RG_SSUSB_RING_OSC_FORCE_EN (0x1<<2) //2:2
++#define RG_SSUSB_FRC_RING_BYPASS_DET (0x1<<1) //1:1
++#define RG_SSUSB_RING_BYPASS_DET (0x1<<0) //0:0
++
++//U3D_B2_ROSC_1
++#define RG_SSUSB_RING_OSC_FRC_P3 (0x1<<20) //20:20
++#define RG_SSUSB_RING_OSC_P3 (0x1<<19) //19:19
++#define RG_SSUSB_RING_OSC_FRC_RECAL (0x3<<17) //18:17
++#define RG_SSUSB_RING_OSC_RECAL (0x1<<16) //16:16
++#define RG_SSUSB_RING_OSC_SEL (0xff<<8) //15:8
++#define RG_SSUSB_RING_OSC_FRC_SEL (0x1<<0) //0:0
++
++//U3D_B2_ROSC_2
++#define RG_SSUSB_RING_DET_STRCYC2 (0xffff<<16) //31:16
++#define RG_SSUSB_RING_DET_STRCYC1 (0xffff<<0) //15:0
++
++//U3D_B2_ROSC_3
++#define RG_SSUSB_RING_DET_DETWIN1 (0xffff<<16) //31:16
++#define RG_SSUSB_RING_DET_STRCYC3 (0xffff<<0) //15:0
++
++//U3D_B2_ROSC_4
++#define RG_SSUSB_RING_DET_DETWIN3 (0xffff<<16) //31:16
++#define RG_SSUSB_RING_DET_DETWIN2 (0xffff<<0) //15:0
++
++//U3D_B2_ROSC_5
++#define RG_SSUSB_RING_DET_LBOND1 (0xffff<<16) //31:16
++#define RG_SSUSB_RING_DET_UBOND1 (0xffff<<0) //15:0
++
++//U3D_B2_ROSC_6
++#define RG_SSUSB_RING_DET_LBOND2 (0xffff<<16) //31:16
++#define RG_SSUSB_RING_DET_UBOND2 (0xffff<<0) //15:0
++
++//U3D_B2_ROSC_7
++#define RG_SSUSB_RING_DET_LBOND3 (0xffff<<16) //31:16
++#define RG_SSUSB_RING_DET_UBOND3 (0xffff<<0) //15:0
++
++//U3D_B2_ROSC_8
++#define RG_SSUSB_RING_RESERVE (0xffff<<16) //31:16
++#define RG_SSUSB_ROSC_PROB_SEL (0xf<<2) //5:2
++#define RG_SSUSB_RING_FREQMETER_EN (0x1<<1) //1:1
++#define RG_SSUSB_RING_DET_BPS_UBOND (0x1<<0) //0:0
++
++//U3D_B2_ROSC_9
++#define RGS_FM_RING_CNT (0xffff<<16) //31:16
++#define RGS_SSUSB_RING_OSC_STATE (0x3<<10) //11:10
++#define RGS_SSUSB_RING_OSC_STABLE (0x1<<9) //9:9
++#define RGS_SSUSB_RING_OSC_CAL_FAIL (0x1<<8) //8:8
++#define RGS_SSUSB_RING_OSC_CAL (0xff<<0) //7:0
++
++//U3D_B2_ROSC_A
++#define RGS_SSUSB_ROSC_PROB_OUT (0xff<<0) //7:0
++
++//U3D_PHYD_VERSION
++#define RGS_SSUSB_PHYD_VERSION (0xffffffff<<0) //31:0
++
++//U3D_PHYD_MODEL
++#define RGS_SSUSB_PHYD_MODEL (0xffffffff<<0) //31:0
++
++
++/* OFFSET */
++
++//U3D_B2_PHYD_TOP1
++#define RG_SSUSB_PCIE2_K_EMP_OFST (28)
++#define RG_SSUSB_PCIE2_K_FUL_OFST (24)
++#define RG_SSUSB_TX_EIDLE_LP_EN_OFST (17)
++#define RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST (16)
++#define RG_SSUSB_SIGDET_EN_OFST (15)
++#define RG_SSUSB_FORCE_SIGDET_EN_OFST (14)
++#define RG_SSUSB_CLKRX_EN_OFST (13)
++#define RG_SSUSB_FORCE_CLKRX_EN_OFST (12)
++#define RG_SSUSB_CLKTX_EN_OFST (11)
++#define RG_SSUSB_FORCE_CLKTX_EN_OFST (10)
++#define RG_SSUSB_CLK_REQ_N_I_OFST (9)
++#define RG_SSUSB_FORCE_CLK_REQ_N_I_OFST (8)
++#define RG_SSUSB_RATE_OFST (6)
++#define RG_SSUSB_FORCE_RATE_OFST (5)
++#define RG_SSUSB_PCIE_MODE_SEL_OFST (4)
++#define RG_SSUSB_FORCE_PCIE_MODE_SEL_OFST (3)
++#define RG_SSUSB_PHY_MODE_OFST (1)
++#define RG_SSUSB_FORCE_PHY_MODE_OFST (0)
++
++//U3D_B2_PHYD_TOP2
++#define RG_SSUSB_FORCE_IDRV_6DB_OFST (30)
++#define RG_SSUSB_IDRV_6DB_OFST (24)
++#define RG_SSUSB_FORCE_IDEM_3P5DB_OFST (22)
++#define RG_SSUSB_IDEM_3P5DB_OFST (16)
++#define RG_SSUSB_FORCE_IDRV_3P5DB_OFST (14)
++#define RG_SSUSB_IDRV_3P5DB_OFST (8)
++#define RG_SSUSB_FORCE_IDRV_0DB_OFST (6)
++#define RG_SSUSB_IDRV_0DB_OFST (0)
++
++//U3D_B2_PHYD_TOP3
++#define RG_SSUSB_TX_BIASI_OFST (25)
++#define RG_SSUSB_FORCE_TX_BIASI_EN_OFST (24)
++#define RG_SSUSB_TX_BIASI_EN_OFST (16)
++#define RG_SSUSB_FORCE_TX_BIASI_OFST (13)
++#define RG_SSUSB_FORCE_IDEM_6DB_OFST (8)
++#define RG_SSUSB_IDEM_6DB_OFST (0)
++
++//U3D_B2_PHYD_TOP4
++#define RG_SSUSB_G1_CDR_BIC_LTR_OFST (28)
++#define RG_SSUSB_G1_CDR_BIC_LTD0_OFST (24)
++#define RG_SSUSB_G1_CDR_BC_LTD1_OFST (16)
++#define RG_SSUSB_G1_CDR_BC_LTR_OFST (8)
++#define RG_SSUSB_G1_CDR_BC_LTD0_OFST (0)
++
++//U3D_B2_PHYD_TOP5
++#define RG_SSUSB_G1_CDR_BIR_LTD1_OFST (24)
++#define RG_SSUSB_G1_CDR_BIR_LTR_OFST (16)
++#define RG_SSUSB_G1_CDR_BIR_LTD0_OFST (8)
++#define RG_SSUSB_G1_CDR_BIC_LTD1_OFST (0)
++
++//U3D_B2_PHYD_TOP6
++#define RG_SSUSB_G2_CDR_BIC_LTR_OFST (28)
++#define RG_SSUSB_G2_CDR_BIC_LTD0_OFST (24)
++#define RG_SSUSB_G2_CDR_BC_LTD1_OFST (16)
++#define RG_SSUSB_G2_CDR_BC_LTR_OFST (8)
++#define RG_SSUSB_G2_CDR_BC_LTD0_OFST (0)
++
++//U3D_B2_PHYD_TOP7
++#define RG_SSUSB_G2_CDR_BIR_LTD1_OFST (24)
++#define RG_SSUSB_G2_CDR_BIR_LTR_OFST (16)
++#define RG_SSUSB_G2_CDR_BIR_LTD0_OFST (8)
++#define RG_SSUSB_G2_CDR_BIC_LTD1_OFST (0)
++
++//U3D_B2_PHYD_P_SIGDET1
++#define RG_SSUSB_P_SIGDET_FLT_DIS_OFST (31)
++#define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL_OFST (24)
++#define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL_OFST (16)
++#define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL_OFST (8)
++#define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL_OFST (0)
++
++//U3D_B2_PHYD_P_SIGDET2
++#define RG_SSUSB_P_SIGDET_RX_VAL_S_OFST (29)
++#define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL_OFST (28)
++#define RG_SSUSB_P_SIGDET_L0_EXIT_S_OFST (27)
++#define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S_OFST (25)
++#define RG_SSUSB_P_SIGDET_L0S_EXIT_S_OFST (24)
++#define RG_SSUSB_P_SIGDET_L0S_ENTRY_S_OFST (16)
++#define RG_SSUSB_P_SIGDET_PRB_SEL_OFST (10)
++#define RG_SSUSB_P_SIGDET_BK_SIG_T_OFST (8)
++#define RG_SSUSB_P_SIGDET_P2_RXLFPS_OFST (6)
++#define RG_SSUSB_P_SIGDET_NON_BK_AD_OFST (5)
++#define RG_SSUSB_P_SIGDET_BK_B_RXEQ_OFST (4)
++#define RG_SSUSB_P_SIGDET_G2_KO_SEL_OFST (2)
++#define RG_SSUSB_P_SIGDET_G1_KO_SEL_OFST (0)
++
++//U3D_B2_PHYD_P_SIGDET_CAL1
++#define RG_SSUSB_P_SIGDET_CAL_OFFSET_OFST (24)
++#define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET_OFST (16)
++#define RG_SSUSB_P_SIGDET_CAL_EN_OFST (8)
++#define RG_SSUSB_P_FORCE_SIGDET_CAL_EN_OFST (3)
++#define RG_SSUSB_P_SIGDET_FLT_EN_OFST (2)
++#define RG_SSUSB_P_SIGDET_SAMPLE_PRD_OFST (1)
++#define RG_SSUSB_P_SIGDET_REK_OFST (0)
++
++//U3D_B2_PHYD_RXDET1
++#define RG_SSUSB_RXDET_PRB_SEL_OFST (31)
++#define RG_SSUSB_FORCE_CMDET_OFST (30)
++#define RG_SSUSB_RXDET_EN_OFST (29)
++#define RG_SSUSB_FORCE_RXDET_EN_OFST (28)
++#define RG_SSUSB_RXDET_K_TWICE_OFST (27)
++#define RG_SSUSB_RXDET_STB3_SET_OFST (18)
++#define RG_SSUSB_RXDET_STB2_SET_OFST (9)
++#define RG_SSUSB_RXDET_STB1_SET_OFST (0)
++
++//U3D_B2_PHYD_RXDET2
++#define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN_OFST (31)
++#define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN_OFST (30)
++#define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN_OFST (29)
++#define RG_SSUSB_PDN_T_SEL_OFST (18)
++#define RG_SSUSB_RXDET_STB3_SET_P3_OFST (9)
++#define RG_SSUSB_RXDET_STB2_SET_P3_OFST (0)
++
++//U3D_B2_PHYD_MISC0
++#define RG_SSUSB_FORCE_PLL_DDS_HF_EN_OFST (22)
++#define RG_SSUSB_PLL_DDS_HF_EN_MAN_OFST (21)
++#define RG_SSUSB_RXLFPS_ENTXDRV_OFST (20)
++#define RG_SSUSB_RX_FL_UNLOCKTH_OFST (16)
++#define RG_SSUSB_LFPS_PSEL_OFST (15)
++#define RG_SSUSB_RX_SIGDET_EN_OFST (14)
++#define RG_SSUSB_RX_SIGDET_EN_SEL_OFST (13)
++#define RG_SSUSB_RX_PI_CAL_EN_OFST (12)
++#define RG_SSUSB_RX_PI_CAL_EN_SEL_OFST (11)
++#define RG_SSUSB_P3_CLS_CK_SEL_OFST (10)
++#define RG_SSUSB_T2RLB_PSEL_OFST (8)
++#define RG_SSUSB_PPCTL_PSEL_OFST (5)
++#define RG_SSUSB_PHYD_TX_DATA_INV_OFST (4)
++#define RG_SSUSB_BERTLB_PSEL_OFST (2)
++#define RG_SSUSB_RETRACK_DIS_OFST (1)
++#define RG_SSUSB_PPERRCNT_CLR_OFST (0)
++
++//U3D_B2_PHYD_MISC2
++#define RG_SSUSB_FRC_PLL_DDS_PREDIV2_OFST (31)
++#define RG_SSUSB_FRC_PLL_DDS_IADJ_OFST (27)
++#define RG_SSUSB_P_SIGDET_125FILTER_OFST (26)
++#define RG_SSUSB_P_SIGDET_RST_FILTER_OFST (25)
++#define RG_SSUSB_P_SIGDET_EID_USE_RAW_OFST (24)
++#define RG_SSUSB_P_SIGDET_LTD_USE_RAW_OFST (23)
++#define RG_SSUSB_EIDLE_BF_RXDET_OFST (22)
++#define RG_SSUSB_EIDLE_LP_STBCYC_OFST (13)
++#define RG_SSUSB_TX_EIDLE_LP_POSTDLY_OFST (7)
++#define RG_SSUSB_TX_EIDLE_LP_PREDLY_OFST (1)
++#define RG_SSUSB_TX_EIDLE_LP_EN_ADV_OFST (0)
++
++//U3D_B2_PHYD_MISC3
++#define RGS_SSUSB_DDS_CALIB_C_STATE_OFST (16)
++#define RGS_SSUSB_PPERRCNT_OFST (0)
++
++//U3D_B2_ROSC_0
++#define RG_SSUSB_RING_OSC_CNTEND_OFST (23)
++#define RG_SSUSB_XTAL_OSC_CNTEND_OFST (16)
++#define RG_SSUSB_RING_OSC_EN_OFST (3)
++#define RG_SSUSB_RING_OSC_FORCE_EN_OFST (2)
++#define RG_SSUSB_FRC_RING_BYPASS_DET_OFST (1)
++#define RG_SSUSB_RING_BYPASS_DET_OFST (0)
++
++//U3D_B2_ROSC_1
++#define RG_SSUSB_RING_OSC_FRC_P3_OFST (20)
++#define RG_SSUSB_RING_OSC_P3_OFST (19)
++#define RG_SSUSB_RING_OSC_FRC_RECAL_OFST (17)
++#define RG_SSUSB_RING_OSC_RECAL_OFST (16)
++#define RG_SSUSB_RING_OSC_SEL_OFST (8)
++#define RG_SSUSB_RING_OSC_FRC_SEL_OFST (0)
++
++//U3D_B2_ROSC_2
++#define RG_SSUSB_RING_DET_STRCYC2_OFST (16)
++#define RG_SSUSB_RING_DET_STRCYC1_OFST (0)
++
++//U3D_B2_ROSC_3
++#define RG_SSUSB_RING_DET_DETWIN1_OFST (16)
++#define RG_SSUSB_RING_DET_STRCYC3_OFST (0)
++
++//U3D_B2_ROSC_4
++#define RG_SSUSB_RING_DET_DETWIN3_OFST (16)
++#define RG_SSUSB_RING_DET_DETWIN2_OFST (0)
++
++//U3D_B2_ROSC_5
++#define RG_SSUSB_RING_DET_LBOND1_OFST (16)
++#define RG_SSUSB_RING_DET_UBOND1_OFST (0)
++
++//U3D_B2_ROSC_6
++#define RG_SSUSB_RING_DET_LBOND2_OFST (16)
++#define RG_SSUSB_RING_DET_UBOND2_OFST (0)
++
++//U3D_B2_ROSC_7
++#define RG_SSUSB_RING_DET_LBOND3_OFST (16)
++#define RG_SSUSB_RING_DET_UBOND3_OFST (0)
++
++//U3D_B2_ROSC_8
++#define RG_SSUSB_RING_RESERVE_OFST (16)
++#define RG_SSUSB_ROSC_PROB_SEL_OFST (2)
++#define RG_SSUSB_RING_FREQMETER_EN_OFST (1)
++#define RG_SSUSB_RING_DET_BPS_UBOND_OFST (0)
++
++//U3D_B2_ROSC_9
++#define RGS_FM_RING_CNT_OFST (16)
++#define RGS_SSUSB_RING_OSC_STATE_OFST (10)
++#define RGS_SSUSB_RING_OSC_STABLE_OFST (9)
++#define RGS_SSUSB_RING_OSC_CAL_FAIL_OFST (8)
++#define RGS_SSUSB_RING_OSC_CAL_OFST (0)
++
++//U3D_B2_ROSC_A
++#define RGS_SSUSB_ROSC_PROB_OUT_OFST (0)
++
++//U3D_PHYD_VERSION
++#define RGS_SSUSB_PHYD_VERSION_OFST (0)
++
++//U3D_PHYD_MODEL
++#define RGS_SSUSB_PHYD_MODEL_OFST (0)
++
++
++///////////////////////////////////////////////////////////////////////////////
++
++struct sifslv_chip_reg {
++ PHY_LE32 xtalbias;
++ PHY_LE32 syspll1;
++ PHY_LE32 gpio_ctla;
++ PHY_LE32 gpio_ctlb;
++ PHY_LE32 gpio_ctlc;
++};
++
++//U3D_GPIO_CTLA
++#define RG_C60802_GPIO_CTLA (0xffffffff<<0) //31:0
++
++//U3D_GPIO_CTLB
++#define RG_C60802_GPIO_CTLB (0xffffffff<<0) //31:0
++
++//U3D_GPIO_CTLC
++#define RG_C60802_GPIO_CTLC (0xffffffff<<0) //31:0
++
++/* OFFSET */
++
++//U3D_GPIO_CTLA
++#define RG_C60802_GPIO_CTLA_OFST (0)
++
++//U3D_GPIO_CTLB
++#define RG_C60802_GPIO_CTLB_OFST (0)
++
++//U3D_GPIO_CTLC
++#define RG_C60802_GPIO_CTLC_OFST (0)
++
++///////////////////////////////////////////////////////////////////////////////
++
++struct sifslv_fm_feg {
++ //0x0
++ PHY_LE32 fmcr0;
++ PHY_LE32 fmcr1;
++ PHY_LE32 fmcr2;
++ PHY_LE32 fmmonr0;
++ //0x10
++ PHY_LE32 fmmonr1;
++};
++
++//U3D_FMCR0
++#define RG_LOCKTH (0xf<<28) //31:28
++#define RG_MONCLK_SEL (0x3<<26) //27:26
++#define RG_FM_MODE (0x1<<25) //25:25
++#define RG_FREQDET_EN (0x1<<24) //24:24
++#define RG_CYCLECNT (0xffffff<<0) //23:0
++
++//U3D_FMCR1
++#define RG_TARGET (0xffffffff<<0) //31:0
++
++//U3D_FMCR2
++#define RG_OFFSET (0xffffffff<<0) //31:0
++
++//U3D_FMMONR0
++#define USB_FM_OUT (0xffffffff<<0) //31:0
++
++//U3D_FMMONR1
++#define RG_MONCLK_SEL_3 (0x1<<9) //9:9
++#define RG_FRCK_EN (0x1<<8) //8:8
++#define USBPLL_LOCK (0x1<<1) //1:1
++#define USB_FM_VLD (0x1<<0) //0:0
++
++
++/* OFFSET */
++
++//U3D_FMCR0
++#define RG_LOCKTH_OFST (28)
++#define RG_MONCLK_SEL_OFST (26)
++#define RG_FM_MODE_OFST (25)
++#define RG_FREQDET_EN_OFST (24)
++#define RG_CYCLECNT_OFST (0)
++
++//U3D_FMCR1
++#define RG_TARGET_OFST (0)
++
++//U3D_FMCR2
++#define RG_OFFSET_OFST (0)
++
++//U3D_FMMONR0
++#define USB_FM_OUT_OFST (0)
++
++//U3D_FMMONR1
++#define RG_MONCLK_SEL_3_OFST (9)
++#define RG_FRCK_EN_OFST (8)
++#define USBPLL_LOCK_OFST (1)
++#define USB_FM_VLD_OFST (0)
++
++
++///////////////////////////////////////////////////////////////////////////////
++
++PHY_INT32 phy_init(struct u3phy_info *info);
++PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
++PHY_INT32 eyescan_init(struct u3phy_info *info);
++PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
++ , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
++PHY_INT32 u2_save_cur_en(struct u3phy_info *info);
++PHY_INT32 u2_save_cur_re(struct u3phy_info *info);
++PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info);
++
++#endif
++#endif
+--- /dev/null
++++ b/drivers/usb/host/mtk-phy-ahb.c
+@@ -0,0 +1,58 @@
++#include "mtk-phy.h"
++#ifdef CONFIG_U3D_HAL_SUPPORT
++#include "mu3d_hal_osal.h"
++#endif
++
++#ifdef CONFIG_U3_PHY_AHB_SUPPORT
++#include <linux/gfp.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++
++#ifndef CONFIG_U3D_HAL_SUPPORT
++#define os_writel(addr,data) {\
++ (*((volatile PHY_UINT32*)(addr)) = data);\
++ }
++#define os_readl(addr) *((volatile PHY_UINT32*)(addr))
++#define os_writelmsk(addr, data, msk) \
++ { os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk)))); \
++ }
++#define os_setmsk(addr, msk) \
++ { os_writel(addr, os_readl(addr) | msk); \
++ }
++#define os_clrmsk(addr, msk) \
++ { os_writel(addr, os_readl(addr) &~ msk); \
++ }
++/*msk the data first, then umsk with the umsk.*/
++#define os_writelmskumsk(addr, data, msk, umsk) \
++{\
++ os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk))) & (umsk));\
++}
++
++#endif
++
++PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data)
++{
++ os_writel(addr, data);
++
++ return 0;
++}
++
++PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr)
++{
++ return os_readl(addr);
++}
++
++PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data)
++{
++ os_writelmsk(addr&0xfffffffc, data<<((addr%4)*8), 0xff<<((addr%4)*8));
++
++ return 0;
++}
++
++PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr)
++{
++ return ((os_readl(addr)>>((addr%4)*8))&0xff);
++}
++
++#endif
++
+--- /dev/null
++++ b/drivers/usb/host/mtk-phy.c
+@@ -0,0 +1,102 @@
++#include <linux/gfp.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#define U3_PHY_LIB
++#include "mtk-phy.h"
++#ifdef CONFIG_PROJECT_7621
++#include "mtk-phy-7621.h"
++#endif
++#ifdef CONFIG_PROJECT_PHY
++static struct u3phy_operator project_operators = {
++ .init = phy_init,
++ .change_pipe_phase = phy_change_pipe_phase,
++ .eyescan_init = eyescan_init,
++ .eyescan = phy_eyescan,
++ .u2_slew_rate_calibration = u2_slew_rate_calibration,
++};
++#endif
++
++
++PHY_INT32 u3phy_init(){
++#ifndef CONFIG_PROJECT_PHY
++ PHY_INT32 u3phy_version;
++#endif
++
++ if(u3phy != NULL){
++ return PHY_TRUE;
++ }
++
++ u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
++#endif
++#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
++ u3phy->phyd_version_addr = 0x2000e4;
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ u3phy_p1->phyd_version_addr = 0x2000e4;
++#endif
++#else
++ u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4;
++#endif
++#endif
++
++#ifdef CONFIG_PROJECT_PHY
++
++ u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE;
++ u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE;
++ u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE;
++ u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE;
++ u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE;
++ u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
++ u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
++ u3phy_ops = &project_operators;
++
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1;
++ u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1;
++ u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1;
++ u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1;
++ u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1;
++ u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
++ u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
++#endif
++#endif
++
++ return PHY_TRUE;
++}
++
++PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
++ PHY_INT8 cur_value;
++ PHY_INT8 new_value;
++
++ cur_value = U3PhyReadReg8(addr);
++ new_value = (cur_value & (~mask)) | (value << offset);
++ //udelay(i2cdelayus);
++ U3PhyWriteReg8(addr, new_value);
++ return PHY_TRUE;
++}
++
++PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
++ PHY_INT32 cur_value;
++ PHY_INT32 new_value;
++
++ cur_value = U3PhyReadReg32(addr);
++ new_value = (cur_value & (~mask)) | ((value << offset) & mask);
++ U3PhyWriteReg32(addr, new_value);
++ //DRV_MDELAY(100);
++
++ return PHY_TRUE;
++}
++
++PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){
++
++ return ((U3PhyReadReg8(addr) & mask) >> offset);
++}
++
++PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){
++
++ return ((U3PhyReadReg32(addr) & mask) >> offset);
++}
++
+--- /dev/null
++++ b/drivers/usb/host/mtk-phy.h
+@@ -0,0 +1,179 @@
++#ifndef __MTK_PHY_NEW_H
++#define __MTK_PHY_NEW_H
++
++//#define CONFIG_U3D_HAL_SUPPORT
++
++/* include system library */
++#include <linux/gfp.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++
++/* Choose PHY R/W implementation */
++//#define CONFIG_U3_PHY_GPIO_SUPPORT //SW I2C implemented by GPIO
++#define CONFIG_U3_PHY_AHB_SUPPORT //AHB, only on SoC
++
++/* Choose PHY version */
++//Select your project by defining one of the followings
++#define CONFIG_PROJECT_7621 //7621
++#define CONFIG_PROJECT_PHY
++
++/* BASE ADDRESS DEFINE, should define this on ASIC */
++#define PHY_BASE 0xBE1D0000
++#define SIFSLV_FM_FEG_BASE (PHY_BASE+0x100)
++#define SIFSLV_CHIP_BASE (PHY_BASE+0x700)
++#define U2_PHY_BASE (PHY_BASE+0x800)
++#define U3_PHYD_BASE (PHY_BASE+0x900)
++#define U3_PHYD_B2_BASE (PHY_BASE+0xa00)
++#define U3_PHYA_BASE (PHY_BASE+0xb00)
++#define U3_PHYA_DA_BASE (PHY_BASE+0xc00)
++
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++#define SIFSLV_FM_FEG_BASE_P1 (PHY_BASE+0x100)
++#define SIFSLV_CHIP_BASE_P1 (PHY_BASE+0x700)
++#define U2_PHY_BASE_P1 (PHY_BASE+0x1000)
++#define U3_PHYD_BASE_P1 (PHY_BASE+0x1100)
++#define U3_PHYD_B2_BASE_P1 (PHY_BASE+0x1200)
++#define U3_PHYA_BASE_P1 (PHY_BASE+0x1300)
++#define U3_PHYA_DA_BASE_P1 (PHY_BASE+0x1400)
++#endif
++
++/*
++
++0x00000100 MODULE ssusb_sifslv_fmreg ssusb_sifslv_fmreg
++0x00000700 MODULE ssusb_sifslv_ippc ssusb_sifslv_ippc
++0x00000800 MODULE ssusb_sifslv_u2phy_com ssusb_sifslv_u2_phy_com_T28
++0x00000900 MODULE ssusb_sifslv_u3phyd ssusb_sifslv_u3phyd_T28
++0x00000a00 MODULE ssusb_sifslv_u3phyd_bank2 ssusb_sifslv_u3phyd_bank2_T28
++0x00000b00 MODULE ssusb_sifslv_u3phya ssusb_sifslv_u3phya_T28
++0x00000c00 MODULE ssusb_sifslv_u3phya_da ssusb_sifslv_u3phya_da_T28
++*/
++
++
++/* TYPE DEFINE */
++typedef unsigned int PHY_UINT32;
++typedef int PHY_INT32;
++typedef unsigned short PHY_UINT16;
++typedef short PHY_INT16;
++typedef unsigned char PHY_UINT8;
++typedef char PHY_INT8;
++
++typedef PHY_UINT32 __bitwise PHY_LE32;
++
++/* CONSTANT DEFINE */
++#define PHY_FALSE 0
++#define PHY_TRUE 1
++
++/* MACRO DEFINE */
++#define DRV_WriteReg32(addr,data) ((*(volatile PHY_UINT32 *)(addr)) = (unsigned long)(data))
++#define DRV_Reg32(addr) (*(volatile PHY_UINT32 *)(addr))
++
++#define DRV_MDELAY mdelay
++#define DRV_MSLEEP msleep
++#define DRV_UDELAY udelay
++#define DRV_USLEEP usleep
++
++/* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
++PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data);
++PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr);
++PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data);
++PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr);
++
++/* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
++PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
++PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
++PHY_INT32 U3PhyReadField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
++PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
++
++struct u3phy_info {
++ PHY_INT32 phy_version;
++ PHY_INT32 phyd_version_addr;
++
++#ifdef CONFIG_PROJECT_PHY
++ struct u2phy_reg *u2phy_regs;
++ struct u3phya_reg *u3phya_regs;
++ struct u3phya_da_reg *u3phya_da_regs;
++ struct u3phyd_reg *u3phyd_regs;
++ struct u3phyd_bank2_reg *u3phyd_bank2_regs;
++ struct sifslv_chip_reg *sifslv_chip_regs;
++ struct sifslv_fm_feg *sifslv_fm_regs;
++#endif
++};
++
++struct u3phy_operator {
++ PHY_INT32 (*init) (struct u3phy_info *info);
++ PHY_INT32 (*change_pipe_phase) (struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
++ PHY_INT32 (*eyescan_init) (struct u3phy_info *info);
++ PHY_INT32 (*eyescan) (struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
++ PHY_INT32 (*u2_save_current_entry) (struct u3phy_info *info);
++ PHY_INT32 (*u2_save_current_recovery) (struct u3phy_info *info);
++ PHY_INT32 (*u2_slew_rate_calibration) (struct u3phy_info *info);
++};
++
++#ifdef U3_PHY_LIB
++#define AUTOEXT
++#else
++#define AUTOEXT extern
++#endif
++
++AUTOEXT struct u3phy_info *u3phy;
++AUTOEXT struct u3phy_info *u3phy_p1;
++AUTOEXT struct u3phy_operator *u3phy_ops;
++
++/*********eye scan required*********/
++
++#define LO_BYTE(x) ((PHY_UINT8)((x) & 0xFF))
++#define HI_BYTE(x) ((PHY_UINT8)(((x) & 0xFF00) >> 8))
++
++typedef enum
++{
++ SCAN_UP,
++ SCAN_DN
++} enumScanDir;
++
++struct strucScanRegion
++{
++ PHY_INT8 bX_tl;
++ PHY_INT8 bY_tl;
++ PHY_INT8 bX_br;
++ PHY_INT8 bY_br;
++ PHY_INT8 bDeltaX;
++ PHY_INT8 bDeltaY;
++};
++
++struct strucTestCycle
++{
++ PHY_UINT16 wEyeCnt;
++ PHY_INT8 bNumOfEyeCnt;
++ PHY_INT8 bPICalEn;
++ PHY_INT8 bNumOfIgnoreCnt;
++};
++
++#define ERRCNT_MAX 128
++#define CYCLE_COUNT_MAX 15
++
++/// the map resolution is 128 x 128 pts
++#define MAX_X 127
++#define MAX_Y 127
++#define MIN_X 0
++#define MIN_Y 0
++
++PHY_INT32 u3phy_init(void);
++
++AUTOEXT struct strucScanRegion _rEye1;
++AUTOEXT struct strucScanRegion _rEye2;
++AUTOEXT struct strucTestCycle _rTestCycle;
++AUTOEXT PHY_UINT8 _bXcurr;
++AUTOEXT PHY_UINT8 _bYcurr;
++AUTOEXT enumScanDir _eScanDir;
++AUTOEXT PHY_INT8 _fgXChged;
++AUTOEXT PHY_INT8 _bPIResult;
++/* use local variable instead to save memory use */
++#if 0
++AUTOEXT PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
++AUTOEXT PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
++#endif
++
++/***********************************/
++#endif
++
+--- a/drivers/usb/host/pci-quirks.h
++++ b/drivers/usb/host/pci-quirks.h
+@@ -1,7 +1,7 @@
+ #ifndef __LINUX_USB_PCI_QUIRKS_H
+ #define __LINUX_USB_PCI_QUIRKS_H
+
+-#ifdef CONFIG_PCI
++#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
+ int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
+ #endif /* CONFIG_PCI */
+--- a/drivers/usb/host/xhci-dbg.c
++++ b/drivers/usb/host/xhci-dbg.c
+@@ -21,6 +21,9 @@
+ */
+
+ #include "xhci.h"
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++#include "xhci-mtk.h"
++#endif
+
+ #define XHCI_INIT_VALUE 0x0
+
+--- a/drivers/usb/host/xhci-mem.c
++++ b/drivers/usb/host/xhci-mem.c
+@@ -65,6 +65,9 @@ static struct xhci_segment *xhci_segment
+
+ static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
+ {
++ if (!seg)
++ return;
++
+ if (seg->trbs) {
+ dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
+ seg->trbs = NULL;
+@@ -1446,9 +1449,17 @@ int xhci_endpoint_init(struct xhci_hcd *
+ max_burst = (usb_endpoint_maxp(&ep->desc)
+ & 0x1800) >> 11;
+ }
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
++ max_packet += 2;
++#endif
+ break;
+ case USB_SPEED_FULL:
+ case USB_SPEED_LOW:
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
++ max_packet += 2;
++#endif
+ break;
+ default:
+ BUG();
+--- /dev/null
++++ b/drivers/usb/host/xhci-mtk-power.c
+@@ -0,0 +1,115 @@
++#include "xhci-mtk.h"
++#include "xhci-mtk-power.h"
++#include "xhci.h"
++#include <linux/kernel.h> /* printk() */
++#include <linux/slab.h>
++#include <linux/delay.h>
++
++static int g_num_u3_port;
++static int g_num_u2_port;
++
++
++void enableXhciAllPortPower(struct xhci_hcd *xhci){
++ int i;
++ u32 port_id, temp;
++ u32 __iomem *addr;
++
++ g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
++ g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
++
++ for(i=1; i<=g_num_u3_port; i++){
++ port_id=i;
++ addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
++ temp = xhci_readl(xhci, addr);
++ temp = xhci_port_state_to_neutral(temp);
++ temp |= PORT_POWER;
++ xhci_writel(xhci, temp, addr);
++ }
++ for(i=1; i<=g_num_u2_port; i++){
++ port_id=i+g_num_u3_port;
++ addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
++ temp = xhci_readl(xhci, addr);
++ temp = xhci_port_state_to_neutral(temp);
++ temp |= PORT_POWER;
++ xhci_writel(xhci, temp, addr);
++ }
++}
++
++void enableAllClockPower(){
++
++ int i;
++ u32 temp;
++
++ g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
++ g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
++
++ //2. Enable xHC
++ writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
++ writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
++ writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
++
++ //1. Enable target ports
++ for(i=0; i<g_num_u3_port; i++){
++ temp = readl(SSUSB_U3_CTRL(i));
++ temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
++ writel(temp, SSUSB_U3_CTRL(i));
++ }
++ for(i=0; i<g_num_u2_port; i++){
++ temp = readl(SSUSB_U2_CTRL(i));
++ temp = temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
++ writel(temp, SSUSB_U2_CTRL(i));
++ }
++ msleep(100);
++}
++
++
++//(X)disable clock/power of a port
++//(X)if all ports are disabled, disable IP ctrl power
++//disable all ports and IP clock/power, this is just mention HW that the power/clock of port
++//and IP could be disable if suspended.
++//If doesn't not disable all ports at first, the IP clock/power will never be disabled
++//(some U2 and U3 ports are binded to the same connection, that is, they will never enter suspend at the same time
++//port_index: port number
++//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
++void disablePortClockPower(void){
++ int i;
++ u32 temp;
++
++ g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
++ g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
++
++ for(i=0; i<g_num_u3_port; i++){
++ temp = readl(SSUSB_U3_CTRL(i));
++ temp = temp | (SSUSB_U3_PORT_PDN);
++ writel(temp, SSUSB_U3_CTRL(i));
++ }
++ for(i=0; i<g_num_u2_port; i++){
++ temp = readl(SSUSB_U2_CTRL(i));
++ temp = temp | (SSUSB_U2_PORT_PDN);
++ writel(temp, SSUSB_U2_CTRL(i));
++ }
++ writel(readl(SSUSB_IP_PW_CTRL_1) | (SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
++}
++
++//if IP ctrl power is disabled, enable it
++//enable clock/power of a port
++//port_index: port number
++//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
++void enablePortClockPower(int port_index, int port_rev){
++ int i;
++ u32 temp;
++
++ writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
++
++ if(port_rev == 0x3){
++ temp = readl(SSUSB_U3_CTRL(port_index));
++ temp = temp & (~SSUSB_U3_PORT_PDN);
++ writel(temp, SSUSB_U3_CTRL(port_index));
++ }
++ else if(port_rev == 0x2){
++ temp = readl(SSUSB_U2_CTRL(port_index));
++ temp = temp & (~SSUSB_U2_PORT_PDN);
++ writel(temp, SSUSB_U2_CTRL(port_index));
++ }
++}
++
+--- /dev/null
++++ b/drivers/usb/host/xhci-mtk-power.h
+@@ -0,0 +1,13 @@
++#ifndef _XHCI_MTK_POWER_H
++#define _XHCI_MTK_POWER_H
++
++#include <linux/usb.h>
++#include "xhci.h"
++#include "xhci-mtk.h"
++
++void enableXhciAllPortPower(struct xhci_hcd *xhci);
++void enableAllClockPower(void);
++void disablePortClockPower(void);
++void enablePortClockPower(int port_index, int port_rev);
++
++#endif
+--- /dev/null
++++ b/drivers/usb/host/xhci-mtk-scheduler.c
+@@ -0,0 +1,608 @@
++#include "xhci-mtk-scheduler.h"
++#include <linux/kernel.h> /* printk() */
++
++static struct sch_ep **ss_out_eps[MAX_EP_NUM];
++static struct sch_ep **ss_in_eps[MAX_EP_NUM];
++static struct sch_ep **hs_eps[MAX_EP_NUM]; //including tt isoc
++static struct sch_ep **tt_intr_eps[MAX_EP_NUM];
++
++
++int mtk_xhci_scheduler_init(void){
++ int i;
++
++ for(i=0; i<MAX_EP_NUM; i++){
++ ss_out_eps[i] = NULL;
++ }
++ for(i=0; i<MAX_EP_NUM; i++){
++ ss_in_eps[i] = NULL;
++ }
++ for(i=0; i<MAX_EP_NUM; i++){
++ hs_eps[i] = NULL;
++ }
++ for(i=0; i<MAX_EP_NUM; i++){
++ tt_intr_eps[i] = NULL;
++ }
++ return 0;
++}
++
++int add_sch_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
++ , int mult, int offset, int repeat, int pkts, int cs_count, int burst_mode
++ , int bw_cost, mtk_u32 *ep, struct sch_ep *tmp_ep){
++
++ struct sch_ep **ep_array;
++ int i;
++
++ if(is_in && dev_speed == USB_SPEED_SUPER ){
++ ep_array = (struct sch_ep **)ss_in_eps;
++ }
++ else if(dev_speed == USB_SPEED_SUPER){
++ ep_array = (struct sch_ep **)ss_out_eps;
++ }
++ else if(dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)){
++ ep_array = (struct sch_ep **)hs_eps;
++ }
++ else{
++ ep_array = (struct sch_ep **)tt_intr_eps;
++ }
++ for(i=0; i<MAX_EP_NUM; i++){
++ if(ep_array[i] == NULL){
++ tmp_ep->dev_speed = dev_speed;
++ tmp_ep->isTT = isTT;
++ tmp_ep->is_in = is_in;
++ tmp_ep->ep_type = ep_type;
++ tmp_ep->maxp = maxp;
++ tmp_ep->interval = interval;
++ tmp_ep->burst = burst;
++ tmp_ep->mult = mult;
++ tmp_ep->offset = offset;
++ tmp_ep->repeat = repeat;
++ tmp_ep->pkts = pkts;
++ tmp_ep->cs_count = cs_count;
++ tmp_ep->burst_mode = burst_mode;
++ tmp_ep->bw_cost = bw_cost;
++ tmp_ep->ep = ep;
++ ep_array[i] = tmp_ep;
++ return SCH_SUCCESS;
++ }
++ }
++ return SCH_FAIL;
++}
++
++int count_ss_bw(int is_in, int ep_type, int maxp, int interval, int burst, int mult, int offset, int repeat
++ , int td_size){
++ int i, j, k;
++ int bw_required[3];
++ int final_bw_required;
++ int bw_required_per_repeat;
++ int tmp_bw_required;
++ struct sch_ep *cur_sch_ep;
++ struct sch_ep **ep_array;
++ int cur_offset;
++ int cur_ep_offset;
++ int tmp_offset;
++ int tmp_interval;
++ int ep_offset;
++ int ep_interval;
++ int ep_repeat;
++ int ep_mult;
++
++ if(is_in){
++ ep_array = (struct sch_ep **)ss_in_eps;
++ }
++ else{
++ ep_array = (struct sch_ep **)ss_out_eps;
++ }
++
++ bw_required[0] = 0;
++ bw_required[1] = 0;
++ bw_required[2] = 0;
++
++ if(repeat == 0){
++ final_bw_required = 0;
++ for(i=0; i<MAX_EP_NUM; i++){
++ cur_sch_ep = ep_array[i];
++ if(cur_sch_ep == NULL){
++ continue;
++ }
++ ep_interval = cur_sch_ep->interval;
++ ep_offset = cur_sch_ep->offset;
++ if(cur_sch_ep->repeat == 0){
++ if(ep_interval >= interval){
++ tmp_offset = ep_offset + ep_interval - offset;
++ tmp_interval = interval;
++ }
++ else{
++ tmp_offset = offset + interval - ep_offset;
++ tmp_interval = ep_interval;
++ }
++ if(tmp_offset % tmp_interval == 0){
++ final_bw_required += cur_sch_ep->bw_cost;
++ }
++ }
++ else{
++ ep_repeat = cur_sch_ep->repeat;
++ ep_mult = cur_sch_ep->mult;
++ for(k=0; k<=ep_mult; k++){
++ cur_ep_offset = ep_offset+(k*ep_mult);
++ if(ep_interval >= interval){
++ tmp_offset = cur_ep_offset + ep_interval - offset;
++ tmp_interval = interval;
++ }
++ else{
++ tmp_offset = offset + interval - cur_ep_offset;
++ tmp_interval = ep_interval;
++ }
++ if(tmp_offset % tmp_interval == 0){
++ final_bw_required += cur_sch_ep->bw_cost;
++ break;
++ }
++ }
++ }
++ }
++ final_bw_required += td_size;
++ }
++ else{
++ bw_required_per_repeat = maxp * (burst+1);
++ for(j=0; j<=mult; j++){
++ tmp_bw_required = 0;
++ cur_offset = offset+(j*repeat);
++ for(i=0; i<MAX_EP_NUM; i++){
++ cur_sch_ep = ep_array[i];
++ if(cur_sch_ep == NULL){
++ continue;
++ }
++ ep_interval = cur_sch_ep->interval;
++ ep_offset = cur_sch_ep->offset;
++ if(cur_sch_ep->repeat == 0){
++ if(ep_interval >= interval){
++ tmp_offset = ep_offset + ep_interval - cur_offset;
++ tmp_interval = interval;
++ }
++ else{
++ tmp_offset = cur_offset + interval - ep_offset;
++ tmp_interval = ep_interval;
++ }
++ if(tmp_offset % tmp_interval == 0){
++ tmp_bw_required += cur_sch_ep->bw_cost;
++ }
++ }
++ else{
++ ep_repeat = cur_sch_ep->repeat;
++ ep_mult = cur_sch_ep->mult;
++ for(k=0; k<=ep_mult; k++){
++ cur_ep_offset = ep_offset+(k*ep_repeat);
++ if(ep_interval >= interval){
++ tmp_offset = cur_ep_offset + ep_interval - cur_offset;
++ tmp_interval = interval;
++ }
++ else{
++ tmp_offset = cur_offset + interval - cur_ep_offset;
++ tmp_interval = ep_interval;
++ }
++ if(tmp_offset % tmp_interval == 0){
++ tmp_bw_required += cur_sch_ep->bw_cost;
++ break;
++ }
++ }
++ }
++ }
++ bw_required[j] = tmp_bw_required;
++ }
++ final_bw_required = SS_BW_BOUND;
++ for(j=0; j<=mult; j++){
++ if(bw_required[j] < final_bw_required){
++ final_bw_required = bw_required[j];
++ }
++ }
++ final_bw_required += bw_required_per_repeat;
++ }
++ return final_bw_required;
++}
++
++int count_hs_bw(int ep_type, int maxp, int interval, int offset, int td_size){
++ int i;
++ int bw_required;
++ struct sch_ep *cur_sch_ep;
++ int tmp_offset;
++ int tmp_interval;
++ int ep_offset;
++ int ep_interval;
++ int cur_tt_isoc_interval; //for isoc tt check
++
++ bw_required = 0;
++ for(i=0; i<MAX_EP_NUM; i++){
++
++ cur_sch_ep = (struct sch_ep *)hs_eps[i];
++ if(cur_sch_ep == NULL){
++ continue;
++ }
++ ep_offset = cur_sch_ep->offset;
++ ep_interval = cur_sch_ep->interval;
++
++ if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
++ cur_tt_isoc_interval = ep_interval<<3;
++ if(ep_interval >= interval){
++ tmp_offset = ep_offset + cur_tt_isoc_interval - offset;
++ tmp_interval = interval;
++ }
++ else{
++ tmp_offset = offset + interval - ep_offset;
++ tmp_interval = cur_tt_isoc_interval;
++ }
++ if(cur_sch_ep->is_in){
++ if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
++ bw_required += 188;
++ }
++ }
++ else{
++ if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
++ bw_required += 188;
++ }
++ }
++ }
++ else{
++ if(ep_interval >= interval){
++ tmp_offset = ep_offset + ep_interval - offset;
++ tmp_interval = interval;
++ }
++ else{
++ tmp_offset = offset + interval - ep_offset;
++ tmp_interval = ep_interval;
++ }
++ if(tmp_offset%tmp_interval == 0){
++ bw_required += cur_sch_ep->bw_cost;
++ }
++ }
++ }
++ bw_required += td_size;
++ return bw_required;
++}
++
++int count_tt_isoc_bw(int is_in, int maxp, int interval, int offset, int td_size){
++ char is_cs;
++ int mframe_idx, frame_idx, s_frame, s_mframe, cur_mframe;
++ int bw_required, max_bw;
++ int ss_cs_count;
++ int cs_mframe;
++ int max_frame;
++ int i,j;
++ struct sch_ep *cur_sch_ep;
++ int ep_offset;
++ int ep_interval;
++ int ep_cs_count;
++ int tt_isoc_interval; //for isoc tt check
++ int cur_tt_isoc_interval; //for isoc tt check
++ int tmp_offset;
++ int tmp_interval;
++
++ is_cs = 0;
++
++ tt_isoc_interval = interval<<3; //frame to mframe
++ if(is_in){
++ is_cs = 1;
++ }
++ s_frame = offset/8;
++ s_mframe = offset%8;
++ ss_cs_count = (maxp + (188 - 1))/188;
++ if(is_cs){
++ cs_mframe = offset%8 + 2 + ss_cs_count;
++ if (cs_mframe <= 6)
++ ss_cs_count += 2;
++ else if (cs_mframe == 7)
++ ss_cs_count++;
++ else if (cs_mframe > 8)
++ return -1;
++ }
++ max_bw = 0;
++ if(is_in){
++ i=2;
++ }
++ for(cur_mframe = offset+i; i<ss_cs_count; cur_mframe++, i++){
++ bw_required = 0;
++ for(j=0; j<MAX_EP_NUM; j++){
++ cur_sch_ep = (struct sch_ep *)hs_eps[j];
++ if(cur_sch_ep == NULL){
++ continue;
++ }
++ ep_offset = cur_sch_ep->offset;
++ ep_interval = cur_sch_ep->interval;
++ if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
++ //isoc tt
++ //check if mframe offset overlap
++ //if overlap, add 188 to the bw
++ cur_tt_isoc_interval = ep_interval<<3;
++ if(cur_tt_isoc_interval >= tt_isoc_interval){
++ tmp_offset = (ep_offset+cur_tt_isoc_interval) - cur_mframe;
++ tmp_interval = tt_isoc_interval;
++ }
++ else{
++ tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
++ tmp_interval = cur_tt_isoc_interval;
++ }
++ if(cur_sch_ep->is_in){
++ if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
++ bw_required += 188;
++ }
++ }
++ else{
++ if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
++ bw_required += 188;
++ }
++ }
++
++ }
++ else if(cur_sch_ep->ep_type == USB_EP_INT || cur_sch_ep->ep_type == USB_EP_ISOC){
++ //check if mframe
++ if(ep_interval >= tt_isoc_interval){
++ tmp_offset = (ep_offset+ep_interval) - cur_mframe;
++ tmp_interval = tt_isoc_interval;
++ }
++ else{
++ tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
++ tmp_interval = ep_interval;
++ }
++ if(tmp_offset%tmp_interval == 0){
++ bw_required += cur_sch_ep->bw_cost;
++ }
++ }
++ }
++ bw_required += 188;
++ if(bw_required > max_bw){
++ max_bw = bw_required;
++ }
++ }
++ return max_bw;
++}
++
++int count_tt_intr_bw(int interval, int frame_offset){
++ //check all eps in tt_intr_eps
++ int ret;
++ int i,j;
++ int ep_offset;
++ int ep_interval;
++ int tmp_offset;
++ int tmp_interval;
++ ret = SCH_SUCCESS;
++ struct sch_ep *cur_sch_ep;
++
++ for(i=0; i<MAX_EP_NUM; i++){
++ cur_sch_ep = (struct sch_ep *)tt_intr_eps[i];
++ if(cur_sch_ep == NULL){
++ continue;
++ }
++ ep_offset = cur_sch_ep->offset;
++ ep_interval = cur_sch_ep->interval;
++ if(ep_interval >= interval){
++ tmp_offset = ep_offset + ep_interval - frame_offset;
++ tmp_interval = interval;
++ }
++ else{
++ tmp_offset = frame_offset + interval - ep_offset;
++ tmp_interval = ep_interval;
++ }
++
++ if(tmp_offset%tmp_interval==0){
++ return SCH_FAIL;
++ }
++ }
++ return SCH_SUCCESS;
++}
++
++struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep){
++ int i;
++ struct sch_ep **ep_array;
++ struct sch_ep *cur_ep;
++
++ if (is_in && dev_speed == USB_SPEED_SUPER) {
++ ep_array = (struct sch_ep **)ss_in_eps;
++ }
++ else if (dev_speed == USB_SPEED_SUPER) {
++ ep_array = (struct sch_ep **)ss_out_eps;
++ }
++ else if (dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)) {
++ ep_array = (struct sch_ep **)hs_eps;
++ }
++ else {
++ ep_array = (struct sch_ep **)tt_intr_eps;
++ }
++ for (i = 0; i < MAX_EP_NUM; i++) {
++ cur_ep = (struct sch_ep *)ep_array[i];
++ if(cur_ep != NULL && cur_ep->ep == ep){
++ ep_array[i] = NULL;
++ return cur_ep;
++ }
++ }
++ return NULL;
++}
++
++int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
++ , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep){
++ mtk_u32 bPkts = 0;
++ mtk_u32 bCsCount = 0;
++ mtk_u32 bBm = 1;
++ mtk_u32 bOffset = 0;
++ mtk_u32 bRepeat = 0;
++ int ret;
++ struct mtk_xhci_ep_ctx *temp_ep_ctx;
++ int td_size;
++ int mframe_idx, frame_idx;
++ int bw_cost;
++ int cur_bw, best_bw, best_bw_idx,repeat, max_repeat, best_bw_repeat;
++ int cur_offset, cs_mframe;
++ int break_out;
++ int frame_interval;
++
++ printk(KERN_ERR "add_ep parameters, dev_speed %d, is_in %d, isTT %d, ep_type %d, maxp %d, interval %d, burst %d, mult %d, ep 0x%x, ep_ctx 0x%x, sch_ep 0x%x\n", dev_speed, is_in, isTT, ep_type, maxp
++ , interval, burst, mult, ep, ep_ctx, sch_ep);
++ if(isTT && ep_type == USB_EP_INT && ((dev_speed == USB_SPEED_LOW) || (dev_speed == USB_SPEED_FULL))){
++ frame_interval = interval >> 3;
++ for(frame_idx=0; frame_idx<frame_interval; frame_idx++){
++ printk(KERN_ERR "check tt_intr_bw interval %d, frame_idx %d\n", frame_interval, frame_idx);
++ if(count_tt_intr_bw(frame_interval, frame_idx) == SCH_SUCCESS){
++ printk(KERN_ERR "check OK............\n");
++ bOffset = frame_idx<<3;
++ bPkts = 1;
++ bCsCount = 3;
++ bw_cost = maxp;
++ bRepeat = 0;
++ if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, frame_interval, burst, mult
++ , bOffset, bRepeat, bPkts, bCsCount, bBm, maxp, ep, sch_ep) == SCH_FAIL){
++ return SCH_FAIL;
++ }
++ ret = SCH_SUCCESS;
++ break;
++ }
++ }
++ }
++ else if(isTT && ep_type == USB_EP_ISOC){
++ best_bw = HS_BW_BOUND;
++ best_bw_idx = -1;
++ cur_bw = 0;
++ td_size = maxp;
++ break_out = 0;
++ frame_interval = interval>>3;
++ for(frame_idx=0; frame_idx<frame_interval && !break_out; frame_idx++){
++ for(mframe_idx=0; mframe_idx<8; mframe_idx++){
++ cur_offset = (frame_idx*8) + mframe_idx;
++ cur_bw = count_tt_isoc_bw(is_in, maxp, frame_interval, cur_offset, td_size);
++ if(cur_bw > 0 && cur_bw < best_bw){
++ best_bw_idx = cur_offset;
++ best_bw = cur_bw;
++ if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
++ break_out = 1;
++ break;
++ }
++ }
++ }
++ }
++ if(best_bw_idx == -1){
++ return SCH_FAIL;
++ }
++ else{
++ bOffset = best_bw_idx;
++ bPkts = 1;
++ bCsCount = (maxp + (188 - 1)) / 188;
++ if(is_in){
++ cs_mframe = bOffset%8 + 2 + bCsCount;
++ if (cs_mframe <= 6)
++ bCsCount += 2;
++ else if (cs_mframe == 7)
++ bCsCount++;
++ }
++ bw_cost = 188;
++ bRepeat = 0;
++ if(add_sch_ep( dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
++ , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
++ return SCH_FAIL;
++ }
++ ret = SCH_SUCCESS;
++ }
++ }
++ else if((dev_speed == USB_SPEED_FULL || dev_speed == USB_SPEED_LOW) && ep_type == USB_EP_INT){
++ bPkts = 1;
++ ret = SCH_SUCCESS;
++ }
++ else if(dev_speed == USB_SPEED_FULL && ep_type == USB_EP_ISOC){
++ bPkts = 1;
++ ret = SCH_SUCCESS;
++ }
++ else if(dev_speed == USB_SPEED_HIGH && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
++ best_bw = HS_BW_BOUND;
++ best_bw_idx = -1;
++ cur_bw = 0;
++ td_size = maxp*(burst+1);
++ for(cur_offset = 0; cur_offset<interval; cur_offset++){
++ cur_bw = count_hs_bw(ep_type, maxp, interval, cur_offset, td_size);
++ if(cur_bw > 0 && cur_bw < best_bw){
++ best_bw_idx = cur_offset;
++ best_bw = cur_bw;
++ if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
++ break;
++ }
++ }
++ }
++ if(best_bw_idx == -1){
++ return SCH_FAIL;
++ }
++ else{
++ bOffset = best_bw_idx;
++ bPkts = burst + 1;
++ bCsCount = 0;
++ bw_cost = td_size;
++ bRepeat = 0;
++ if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
++ , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
++ return SCH_FAIL;
++ }
++ ret = SCH_SUCCESS;
++ }
++ }
++ else if(dev_speed == USB_SPEED_SUPER && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
++ best_bw = SS_BW_BOUND;
++ best_bw_idx = -1;
++ cur_bw = 0;
++ td_size = maxp * (mult+1) * (burst+1);
++ if(mult == 0){
++ max_repeat = 0;
++ }
++ else{
++ max_repeat = (interval-1)/(mult+1);
++ }
++ break_out = 0;
++ for(frame_idx = 0; (frame_idx < interval) && !break_out; frame_idx++){
++ for(repeat = max_repeat; repeat >= 0; repeat--){
++ cur_bw = count_ss_bw(is_in, ep_type, maxp, interval, burst, mult, frame_idx
++ , repeat, td_size);
++ printk(KERN_ERR "count_ss_bw, frame_idx %d, repeat %d, td_size %d, result bw %d\n"
++ , frame_idx, repeat, td_size, cur_bw);
++ if(cur_bw > 0 && cur_bw < best_bw){
++ best_bw_idx = frame_idx;
++ best_bw_repeat = repeat;
++ best_bw = cur_bw;
++ if(cur_bw <= td_size || cur_bw < (HS_BW_BOUND>>1)){
++ break_out = 1;
++ break;
++ }
++ }
++ }
++ }
++ printk(KERN_ERR "final best idx %d, best repeat %d\n", best_bw_idx, best_bw_repeat);
++ if(best_bw_idx == -1){
++ return SCH_FAIL;
++ }
++ else{
++ bOffset = best_bw_idx;
++ bCsCount = 0;
++ bRepeat = best_bw_repeat;
++ if(bRepeat == 0){
++ bw_cost = (burst+1)*(mult+1)*maxp;
++ bPkts = (burst+1)*(mult+1);
++ }
++ else{
++ bw_cost = (burst+1)*maxp;
++ bPkts = (burst+1);
++ }
++ if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
++ , bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
++ return SCH_FAIL;
++ }
++ ret = SCH_SUCCESS;
++ }
++ }
++ else{
++ bPkts = 1;
++ ret = SCH_SUCCESS;
++ }
++ if(ret == SCH_SUCCESS){
++ temp_ep_ctx = (struct mtk_xhci_ep_ctx *)ep_ctx;
++ temp_ep_ctx->reserved[0] |= (BPKTS(bPkts) | BCSCOUNT(bCsCount) | BBM(bBm));
++ temp_ep_ctx->reserved[1] |= (BOFFSET(bOffset) | BREPEAT(bRepeat));
++
++ printk(KERN_DEBUG "[DBG] BPKTS: %x, BCSCOUNT: %x, BBM: %x\n", bPkts, bCsCount, bBm);
++ printk(KERN_DEBUG "[DBG] BOFFSET: %x, BREPEAT: %x\n", bOffset, bRepeat);
++ return SCH_SUCCESS;
++ }
++ else{
++ return SCH_FAIL;
++ }
++}
+--- /dev/null
++++ b/drivers/usb/host/xhci-mtk-scheduler.h
+@@ -0,0 +1,77 @@
++#ifndef _XHCI_MTK_SCHEDULER_H
++#define _XHCI_MTK_SCHEDULER_H
++
++#define MTK_SCH_NEW 1
++
++#define SCH_SUCCESS 1
++#define SCH_FAIL 0
++
++#define MAX_EP_NUM 64
++#define SS_BW_BOUND 51000
++#define HS_BW_BOUND 6144
++
++#define USB_EP_CONTROL 0
++#define USB_EP_ISOC 1
++#define USB_EP_BULK 2
++#define USB_EP_INT 3
++
++#define USB_SPEED_LOW 1
++#define USB_SPEED_FULL 2
++#define USB_SPEED_HIGH 3
++#define USB_SPEED_SUPER 5
++
++/* mtk scheduler bitmasks */
++#define BPKTS(p) ((p) & 0x3f)
++#define BCSCOUNT(p) (((p) & 0x7) << 8)
++#define BBM(p) ((p) << 11)
++#define BOFFSET(p) ((p) & 0x3fff)
++#define BREPEAT(p) (((p) & 0x7fff) << 16)
++
++
++#if 1
++typedef unsigned int mtk_u32;
++typedef unsigned long long mtk_u64;
++#endif
++
++#define NULL ((void *)0)
++
++struct mtk_xhci_ep_ctx {
++ mtk_u32 ep_info;
++ mtk_u32 ep_info2;
++ mtk_u64 deq;
++ mtk_u32 tx_info;
++ /* offset 0x14 - 0x1f reserved for HC internal use */
++ mtk_u32 reserved[3];
++};
++
++
++struct sch_ep
++{
++ //device info
++ int dev_speed;
++ int isTT;
++ //ep info
++ int is_in;
++ int ep_type;
++ int maxp;
++ int interval;
++ int burst;
++ int mult;
++ //scheduling info
++ int offset;
++ int repeat;
++ int pkts;
++ int cs_count;
++ int burst_mode;
++ //other
++ int bw_cost; //bandwidth cost in each repeat; including overhead
++ mtk_u32 *ep; //address of usb_endpoint pointer
++};
++
++int mtk_xhci_scheduler_init(void);
++int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
++ , int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep);
++struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep);
++
++
++#endif
+--- /dev/null
++++ b/drivers/usb/host/xhci-mtk.c
+@@ -0,0 +1,265 @@
++#include "xhci-mtk.h"
++#include "xhci-mtk-power.h"
++#include "xhci.h"
++#include "mtk-phy.h"
++#ifdef CONFIG_C60802_SUPPORT
++#include "mtk-phy-c60802.h"
++#endif
++#include "xhci-mtk-scheduler.h"
++#include <linux/kernel.h> /* printk() */
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <asm/uaccess.h>
++#include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
++
++void setInitialReg(void )
++{
++ __u32 __iomem *addr;
++ u32 temp;
++
++ /* set SSUSB DMA burst size to 128B */
++ addr = SSUSB_U3_XHCI_BASE + SSUSB_HDMA_CFG;
++ temp = SSUSB_HDMA_CFG_MT7621_VALUE;
++ writel(temp, addr);
++
++ /* extend U3 LTSSM Polling.LFPS timeout value */
++ addr = SSUSB_U3_XHCI_BASE + U3_LTSSM_TIMING_PARAMETER3;
++ temp = U3_LTSSM_TIMING_PARAMETER3_VALUE;
++ writel(temp, addr);
++
++ /* EOF */
++ addr = SSUSB_U3_XHCI_BASE + SYNC_HS_EOF;
++ temp = SYNC_HS_EOF_VALUE;
++ writel(temp, addr);
++
++#if defined (CONFIG_PERIODIC_ENP)
++ /* HSCH_CFG1: SCH2_FIFO_DEPTH */
++ addr = SSUSB_U3_XHCI_BASE + HSCH_CFG1;
++ temp = readl(addr);
++ temp &= ~(0x3 << SCH2_FIFO_DEPTH_OFFSET);
++ writel(temp, addr);
++#endif
++
++ /* Doorbell handling */
++ addr = SIFSLV_IPPC + SSUSB_IP_SPAR0;
++ temp = 0x1;
++ writel(temp, addr);
++
++ /* Set SW PLL Stable mode to 1 for U2 LPM device remote wakeup */
++ /* Port 0 */
++ addr = U2_PHY_BASE + U2_PHYD_CR1;
++ temp = readl(addr);
++ temp &= ~(0x3 << 18);
++ temp |= (1 << 18);
++ writel(temp, addr);
++
++ /* Port 1 */
++ addr = U2_PHY_BASE_P1 + U2_PHYD_CR1;
++ temp = readl(addr);
++ temp &= ~(0x3 << 18);
++ temp |= (1 << 18);
++ writel(temp, addr);
++}
++
++
++void setLatchSel(void){
++ __u32 __iomem *latch_sel_addr;
++ u32 latch_sel_value;
++ latch_sel_addr = U3_PIPE_LATCH_SEL_ADD;
++ latch_sel_value = ((U3_PIPE_LATCH_TX)<<2) | (U3_PIPE_LATCH_RX);
++ writel(latch_sel_value, latch_sel_addr);
++}
++
++void reinitIP(void){
++ __u32 __iomem *ip_reset_addr;
++ u32 ip_reset_value;
++
++ enableAllClockPower();
++ mtk_xhci_scheduler_init();
++}
++
++void dbg_prb_out(void){
++ mtk_probe_init(0x0f0f0f0f);
++ mtk_probe_out(0xffffffff);
++ mtk_probe_out(0x01010101);
++ mtk_probe_out(0x02020202);
++ mtk_probe_out(0x04040404);
++ mtk_probe_out(0x08080808);
++ mtk_probe_out(0x10101010);
++ mtk_probe_out(0x20202020);
++ mtk_probe_out(0x40404040);
++ mtk_probe_out(0x80808080);
++ mtk_probe_out(0x55555555);
++ mtk_probe_out(0xaaaaaaaa);
++}
++
++
++
++///////////////////////////////////////////////////////////////////////////////
++
++#define RET_SUCCESS 0
++#define RET_FAIL 1
++
++static int dbg_u3w(int argc, char**argv)
++{
++ int u4TimingValue;
++ char u1TimingValue;
++ int u4TimingAddress;
++
++ if (argc<3)
++ {
++ printk(KERN_ERR "Arg: address value\n");
++ return RET_FAIL;
++ }
++ u3phy_init();
++
++ u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
++ u4TimingValue = (int)simple_strtol(argv[2], &argv[2], 16);
++ u1TimingValue = u4TimingValue & 0xff;
++ /* access MMIO directly */
++ writel(u1TimingValue, u4TimingAddress);
++ printk(KERN_ERR "Write done\n");
++ return RET_SUCCESS;
++
++}
++
++static int dbg_u3r(int argc, char**argv)
++{
++ char u1ReadTimingValue;
++ int u4TimingAddress;
++ if (argc<2)
++ {
++ printk(KERN_ERR "Arg: address\n");
++ return 0;
++ }
++ u3phy_init();
++ mdelay(500);
++ u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
++ /* access MMIO directly */
++ u1ReadTimingValue = readl(u4TimingAddress);
++ printk(KERN_ERR "Value = 0x%x\n", u1ReadTimingValue);
++ return 0;
++}
++
++static int dbg_u3init(int argc, char**argv)
++{
++ int ret;
++ ret = u3phy_init();
++ printk(KERN_ERR "phy registers and operations initial done\n");
++ if(u3phy_ops->u2_slew_rate_calibration){
++ u3phy_ops->u2_slew_rate_calibration(u3phy);
++ }
++ else{
++ printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
++ }
++ if(u3phy_ops->init(u3phy) == PHY_TRUE)
++ return RET_SUCCESS;
++ return RET_FAIL;
++}
++
++void dbg_setU1U2(int argc, char**argv){
++ struct xhci_hcd *xhci;
++ int u1_value;
++ int u2_value;
++ u32 port_id, temp;
++ u32 __iomem *addr;
++
++ if (argc<3)
++ {
++ printk(KERN_ERR "Arg: u1value u2value\n");
++ return RET_FAIL;
++ }
++
++ u1_value = (int)simple_strtol(argv[1], &argv[1], 10);
++ u2_value = (int)simple_strtol(argv[2], &argv[2], 10);
++ addr = (SSUSB_U3_XHCI_BASE + 0x424);
++ temp = readl(addr);
++ temp = temp & (~(0x0000ffff));
++ temp = temp | u1_value | (u2_value<<8);
++ writel(temp, addr);
++}
++///////////////////////////////////////////////////////////////////////////////
++
++int call_function(char *buf)
++{
++ int i;
++ int argc;
++ char *argv[80];
++
++ argc = 0;
++ do
++ {
++ argv[argc] = strsep(&buf, " ");
++ printk(KERN_DEBUG "[%d] %s\r\n", argc, argv[argc]);
++ argc++;
++ } while (buf);
++ if (!strcmp("dbg.r", argv[0]))
++ dbg_prb_out();
++ else if (!strcmp("dbg.u3w", argv[0]))
++ dbg_u3w(argc, argv);
++ else if (!strcmp("dbg.u3r", argv[0]))
++ dbg_u3r(argc, argv);
++ else if (!strcmp("dbg.u3i", argv[0]))
++ dbg_u3init(argc, argv);
++ else if (!strcmp("pw.u1u2", argv[0]))
++ dbg_setU1U2(argc, argv);
++ return 0;
++}
++
++long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++ char w_buf[200];
++ char r_buf[200] = "this is a test";
++ int len = 200;
++
++ switch (cmd) {
++ case IOCTL_READ:
++ copy_to_user((char *) arg, r_buf, len);
++ printk(KERN_DEBUG "IOCTL_READ: %s\r\n", r_buf);
++ break;
++ case IOCTL_WRITE:
++ copy_from_user(w_buf, (char *) arg, len);
++ printk(KERN_DEBUG "IOCTL_WRITE: %s\r\n", w_buf);
++
++ //invoke function
++ return call_function(w_buf);
++ break;
++ default:
++ return -ENOTTY;
++ }
++
++ return len;
++}
++
++int xhci_mtk_test_open(struct inode *inode, struct file *file)
++{
++
++ printk(KERN_DEBUG "xhci_mtk_test open: successful\n");
++ return 0;
++}
++
++int xhci_mtk_test_release(struct inode *inode, struct file *file)
++{
++
++ printk(KERN_DEBUG "xhci_mtk_test release: successful\n");
++ return 0;
++}
++
++ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr)
++{
++
++ printk(KERN_DEBUG "xhci_mtk_test read: returning zero bytes\n");
++ return 0;
++}
++
++ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos)
++{
++
++ printk(KERN_DEBUG "xhci_mtk_test write: accepting zero bytes\n");
++ return 0;
++}
++
++
++
++
+--- /dev/null
++++ b/drivers/usb/host/xhci-mtk.h
+@@ -0,0 +1,120 @@
++#ifndef _XHCI_MTK_H
++#define _XHCI_MTK_H
++
++#include <linux/usb.h>
++#include "xhci.h"
++
++#define SSUSB_U3_XHCI_BASE 0xBE1C0000
++#define SSUSB_U3_MAC_BASE 0xBE1C2400
++#define SSUSB_U3_SYS_BASE 0xBE1C2600
++#define SSUSB_U2_SYS_BASE 0xBE1C3400
++#define SSUB_SIF_SLV_TOP 0xBE1D0000
++#define SIFSLV_IPPC (SSUB_SIF_SLV_TOP + 0x700)
++
++#define U3_PIPE_LATCH_SEL_ADD SSUSB_U3_MAC_BASE + 0x130
++#define U3_PIPE_LATCH_TX 0
++#define U3_PIPE_LATCH_RX 0
++
++#define U3_UX_EXIT_LFPS_TIMING_PAR 0xa0
++#define U3_REF_CK_PAR 0xb0
++#define U3_RX_UX_EXIT_LFPS_REF_OFFSET 8
++#define U3_RX_UX_EXIT_LFPS_REF 3
++#define U3_REF_CK_VAL 10
++
++#define U3_TIMING_PULSE_CTRL 0xb4
++#define CNT_1US_VALUE 63 //62.5MHz:63, 70MHz:70, 80MHz:80, 100MHz:100, 125MHz:125
++
++#define USB20_TIMING_PARAMETER 0x40
++#define TIME_VALUE_1US 63 //62.5MHz:63, 80MHz:80, 100MHz:100, 125MHz:125
++
++#define LINK_PM_TIMER 0x8
++#define PM_LC_TIMEOUT_VALUE 3
++
++#define XHCI_IMOD 0x624
++#define XHCI_IMOD_MT7621_VALUE 0x10
++
++#define SSUSB_HDMA_CFG 0x950
++#define SSUSB_HDMA_CFG_MT7621_VALUE 0x10E0E0C
++
++#define U3_LTSSM_TIMING_PARAMETER3 0x2514
++#define U3_LTSSM_TIMING_PARAMETER3_VALUE 0x3E8012C
++
++#define U2_PHYD_CR1 0x64
++
++#define SSUSB_IP_SPAR0 0xC8
++
++#define SYNC_HS_EOF 0x938
++#define SYNC_HS_EOF_VALUE 0x201F3
++
++#define HSCH_CFG1 0x960
++#define SCH2_FIFO_DEPTH_OFFSET 16
++
++
++#define SSUSB_IP_PW_CTRL (SIFSLV_IPPC+0x0)
++#define SSUSB_IP_SW_RST (1<<0)
++#define SSUSB_IP_PW_CTRL_1 (SIFSLV_IPPC+0x4)
++#define SSUSB_IP_PDN (1<<0)
++#define SSUSB_U3_CTRL(p) (SIFSLV_IPPC+0x30+(p*0x08))
++#define SSUSB_U3_PORT_DIS (1<<0)
++#define SSUSB_U3_PORT_PDN (1<<1)
++#define SSUSB_U3_PORT_HOST_SEL (1<<2)
++#define SSUSB_U3_PORT_CKBG_EN (1<<3)
++#define SSUSB_U3_PORT_MAC_RST (1<<4)
++#define SSUSB_U3_PORT_PHYD_RST (1<<5)
++#define SSUSB_U2_CTRL(p) (SIFSLV_IPPC+(0x50)+(p*0x08))
++#define SSUSB_U2_PORT_DIS (1<<0)
++#define SSUSB_U2_PORT_PDN (1<<1)
++#define SSUSB_U2_PORT_HOST_SEL (1<<2)
++#define SSUSB_U2_PORT_CKBG_EN (1<<3)
++#define SSUSB_U2_PORT_MAC_RST (1<<4)
++#define SSUSB_U2_PORT_PHYD_RST (1<<5)
++#define SSUSB_IP_CAP (SIFSLV_IPPC+0x024)
++
++#define SSUSB_U3_PORT_NUM(p) (p & 0xff)
++#define SSUSB_U2_PORT_NUM(p) ((p>>8) & 0xff)
++
++
++#define XHCI_MTK_TEST_MAJOR 234
++#define DEVICE_NAME "xhci_mtk_test"
++
++#define CLI_MAGIC 'CLI'
++#define IOCTL_READ _IOR(CLI_MAGIC, 0, int)
++#define IOCTL_WRITE _IOW(CLI_MAGIC, 1, int)
++
++void reinitIP(void);
++void setInitialReg(void);
++void dbg_prb_out(void);
++int call_function(char *buf);
++
++long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
++int xhci_mtk_test_open(struct inode *inode, struct file *file);
++int xhci_mtk_test_release(struct inode *inode, struct file *file);
++ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr);
++ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos);
++
++/*
++ mediatek probe out
++*/
++/************************************************************************************/
++
++#define SW_PRB_OUT_ADDR (SIFSLV_IPPC+0xc0)
++#define PRB_MODULE_SEL_ADDR (SIFSLV_IPPC+0xbc)
++
++static inline void mtk_probe_init(const u32 byte){
++ __u32 __iomem *ptr = (__u32 __iomem *) PRB_MODULE_SEL_ADDR;
++ writel(byte, ptr);
++}
++
++static inline void mtk_probe_out(const u32 value){
++ __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
++ writel(value, ptr);
++}
++
++static inline u32 mtk_probe_value(void){
++ __u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
++
++ return readl(ptr);
++}
++
++
++#endif
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -25,6 +25,13 @@ static void xhci_plat_quirks(struct devi
+ * dev struct in order to setup MSI
+ */
+ xhci->quirks |= XHCI_PLAT;
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ /* MTK host controller gives a spurious successful event after a
++ * short transfer. Ignore it.
++ */
++ xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
++ xhci->quirks |= XHCI_LPM_SUPPORT;
++#endif
+ }
+
+ /* called during probe() after chip reset completes */
+@@ -96,20 +103,32 @@ static int xhci_plat_probe(struct platfo
+
+ driver = &xhci_plat_xhci_driver;
+
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ irq = XHC_IRQ;
++#else
+ irq = platform_get_irq(pdev, 0);
++#endif
++
+ if (irq < 0)
+ return -ENODEV;
+
++#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
++#endif
+
+ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
+ if (!hcd)
+ return -ENOMEM;
+
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ hcd->rsrc_start = (uint32_t)XHC_IO_START;
++ hcd->rsrc_len = XHC_IO_LENGTH;
++#else
+ hcd->rsrc_start = res->start;
+ hcd->rsrc_len = resource_size(res);
++#endif
+
+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
+ driver->description)) {
+--- a/drivers/usb/host/xhci-ring.c
++++ b/drivers/usb/host/xhci-ring.c
+@@ -236,7 +236,6 @@ static void inc_enq(struct xhci_hcd *xhc
+ */
+ if (!chain && !more_trbs_coming)
+ break;
+-
+ /* If we're not dealing with 0.95 hardware or
+ * isoc rings on AMD 0.96 host,
+ * carry over the chain bit of the previous TRB
+@@ -273,16 +272,20 @@ static void inc_enq(struct xhci_hcd *xhc
+ static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
+ unsigned int num_trbs)
+ {
++#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ int num_trbs_in_deq_seg;
++#endif
+
+ if (ring->num_trbs_free < num_trbs)
+ return 0;
+
++#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
+ num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
+ if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
+ return 0;
+ }
++#endif
+
+ return 1;
+ }
+@@ -2910,6 +2913,7 @@ static int prepare_ring(struct xhci_hcd
+ next = ring->enqueue;
+
+ while (last_trb(xhci, ring, ring->enq_seg, next)) {
++#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ /* If we're not dealing with 0.95 hardware or isoc rings
+ * on AMD 0.96 host, clear the chain bit.
+ */
+@@ -2919,7 +2923,9 @@ static int prepare_ring(struct xhci_hcd
+ next->link.control &= cpu_to_le32(~TRB_CHAIN);
+ else
+ next->link.control |= cpu_to_le32(TRB_CHAIN);
+-
++#else
++ next->link.control &= cpu_to_le32(~TRB_CHAIN);
++#endif
+ wmb();
+ next->link.control ^= cpu_to_le32(TRB_CYCLE);
+
+@@ -3049,6 +3055,9 @@ static void giveback_first_trb(struct xh
+ start_trb->field[3] |= cpu_to_le32(start_cycle);
+ else
+ start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ wmb();
++#endif
+ xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
+ }
+
+@@ -3108,6 +3117,29 @@ static u32 xhci_td_remainder(unsigned in
+ return (remainder >> 10) << 17;
+ }
+
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++static u32 mtk_xhci_td_remainder(unsigned int td_transfer_size, unsigned int td_running_total, unsigned int maxp, unsigned trb_buffer_length)
++{
++ u32 max = 31;
++ int remainder, td_packet_count, packet_transferred;
++
++ //0 for the last TRB
++ //FIXME: need to workaround if there is ZLP in this TD
++ if (td_running_total + trb_buffer_length == td_transfer_size)
++ return 0;
++
++ //FIXME: need to take care of high-bandwidth (MAX_ESIT)
++ packet_transferred = (td_running_total /*+ trb_buffer_length*/) / maxp;
++ td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp);
++ remainder = td_packet_count - packet_transferred;
++
++ if (remainder > max)
++ return max << 17;
++ else
++ return remainder << 17;
++}
++#endif
++
+ /*
+ * For xHCI 1.0 host controllers, TD size is the number of max packet sized
+ * packets remaining in the TD (*not* including this TRB).
+@@ -3245,6 +3277,7 @@ static int queue_bulk_sg_tx(struct xhci_
+ }
+
+ /* Set the TRB length, TD size, and interrupter fields. */
++#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ if (xhci->hci_version < 0x100) {
+ remainder = xhci_td_remainder(
+ urb->transfer_buffer_length -
+@@ -3254,6 +3287,13 @@ static int queue_bulk_sg_tx(struct xhci_
+ trb_buff_len, total_packet_count, urb,
+ num_trbs - 1);
+ }
++#else
++ if (num_trbs > 1)
++ remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length,
++ running_total, urb->ep->desc.wMaxPacketSize, trb_buff_len);
++#endif
++
++
+ length_field = TRB_LEN(trb_buff_len) |
+ remainder |
+ TRB_INTR_TARGET(0);
+@@ -3316,6 +3356,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+ int running_total, trb_buff_len, ret;
+ unsigned int total_packet_count;
+ u64 addr;
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ int max_packet;
++#endif
+
+ if (urb->num_sgs)
+ return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
+@@ -3341,6 +3384,25 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+ running_total += TRB_MAX_BUFF_SIZE;
+ }
+ /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ switch(urb->dev->speed){
++ case USB_SPEED_SUPER:
++ max_packet = urb->ep->desc.wMaxPacketSize;
++ break;
++ case USB_SPEED_HIGH:
++ case USB_SPEED_FULL:
++ case USB_SPEED_LOW:
++ case USB_SPEED_WIRELESS:
++ case USB_SPEED_UNKNOWN:
++ default:
++ max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
++ break;
++ }
++ if((urb->transfer_flags & URB_ZERO_PACKET)
++ && ((urb->transfer_buffer_length % max_packet) == 0)){
++ num_trbs++;
++ }
++#endif
+
+ ret = prepare_transfer(xhci, xhci->devs[slot_id],
+ ep_index, urb->stream_id,
+@@ -3400,6 +3462,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+ field |= TRB_ISP;
+
+ /* Set the TRB length, TD size, and interrupter fields. */
++#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ if (xhci->hci_version < 0x100) {
+ remainder = xhci_td_remainder(
+ urb->transfer_buffer_length -
+@@ -3409,6 +3472,10 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+ trb_buff_len, total_packet_count, urb,
+ num_trbs - 1);
+ }
++#else
++ remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
++#endif
++
+ length_field = TRB_LEN(trb_buff_len) |
+ remainder |
+ TRB_INTR_TARGET(0);
+@@ -3498,7 +3565,11 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
+ field |= 0x1;
+
+ /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ if (1) {
++#else
+ if (xhci->hci_version == 0x100) {
++#endif
+ if (urb->transfer_buffer_length > 0) {
+ if (setup->bRequestType & USB_DIR_IN)
+ field |= TRB_TX_TYPE(TRB_DATA_IN);
+@@ -3522,7 +3593,12 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
+ field = TRB_TYPE(TRB_DATA);
+
+ length_field = TRB_LEN(urb->transfer_buffer_length) |
++#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ xhci_td_remainder(urb->transfer_buffer_length) |
++#else
++ //CC: MTK style, no scatter-gather for control transfer
++ 0 |
++#endif
+ TRB_INTR_TARGET(0);
+ if (urb->transfer_buffer_length > 0) {
+ if (setup->bRequestType & USB_DIR_IN)
+@@ -3533,7 +3609,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
+ length_field,
+ field | ep_ring->cycle_state);
+ }
+-
++
+ /* Save the DMA address of the last TRB in the TD */
+ td->last_trb = ep_ring->enqueue;
+
+@@ -3645,6 +3721,9 @@ static int xhci_queue_isoc_tx(struct xhc
+ u64 start_addr, addr;
+ int i, j;
+ bool more_trbs_coming;
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ int max_packet;
++#endif
+
+ ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
+
+@@ -3658,6 +3737,21 @@ static int xhci_queue_isoc_tx(struct xhc
+ start_trb = &ep_ring->enqueue->generic;
+ start_cycle = ep_ring->cycle_state;
+
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ switch(urb->dev->speed){
++ case USB_SPEED_SUPER:
++ max_packet = urb->ep->desc.wMaxPacketSize;
++ break;
++ case USB_SPEED_HIGH:
++ case USB_SPEED_FULL:
++ case USB_SPEED_LOW:
++ case USB_SPEED_WIRELESS:
++ case USB_SPEED_UNKNOWN:
++ max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
++ break;
++ }
++#endif
++
+ urb_priv = urb->hcpriv;
+ /* Queue the first TRB, even if it's zero-length */
+ for (i = 0; i < num_tds; i++) {
+@@ -3729,9 +3823,13 @@ static int xhci_queue_isoc_tx(struct xhc
+ } else {
+ td->last_trb = ep_ring->enqueue;
+ field |= TRB_IOC;
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ if (!(xhci->quirks & XHCI_AVOID_BEI)) {
++#else
+ if (xhci->hci_version == 0x100 &&
+ !(xhci->quirks &
+ XHCI_AVOID_BEI)) {
++#endif
+ /* Set BEI bit except for the last td */
+ if (i < num_tds - 1)
+ field |= TRB_BEI;
+@@ -3746,6 +3844,7 @@ static int xhci_queue_isoc_tx(struct xhc
+ trb_buff_len = td_remain_len;
+
+ /* Set the TRB length, TD size, & interrupter fields. */
++#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ if (xhci->hci_version < 0x100) {
+ remainder = xhci_td_remainder(
+ td_len - running_total);
+@@ -3755,6 +3854,10 @@ static int xhci_queue_isoc_tx(struct xhc
+ total_packet_count, urb,
+ (trbs_per_td - j - 1));
+ }
++#else
++ remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
++#endif
++
+ length_field = TRB_LEN(trb_buff_len) |
+ remainder |
+ TRB_INTR_TARGET(0);
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -30,6 +30,16 @@
+
+ #include "xhci.h"
+
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++#include <asm/uaccess.h>
++#include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
++#include "mtk-phy.h"
++#include "xhci-mtk-scheduler.h"
++#include "xhci-mtk-power.h"
++#include "xhci-mtk.h"
++#endif
++
+ #define DRIVER_AUTHOR "Sarah Sharp"
+ #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
+
+@@ -38,6 +48,18 @@ static int link_quirk;
+ module_param(link_quirk, int, S_IRUGO | S_IWUSR);
+ MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
+
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
++static struct file_operations xhci_mtk_test_fops = {
++ .owner = THIS_MODULE,
++ .read = xhci_mtk_test_read,
++ .write = xhci_mtk_test_write,
++ .unlocked_ioctl = xhci_mtk_test_unlock_ioctl,
++ .open = xhci_mtk_test_open,
++ .release = xhci_mtk_test_release,
++};
++#endif
++
+ /* TODO: copied from ehci-hcd.c - can this be refactored? */
+ /*
+ * xhci_handshake - spin reading hc until handshake completes or fails
+@@ -189,7 +211,7 @@ int xhci_reset(struct xhci_hcd *xhci)
+ return ret;
+ }
+
+-#ifdef CONFIG_PCI
++#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ static int xhci_free_msi(struct xhci_hcd *xhci)
+ {
+ int i;
+@@ -389,6 +411,7 @@ static int xhci_try_enable_msi(struct us
+ return ret;
+ }
+ hcd->irq = pdev->irq;
++
+ return 0;
+ }
+
+@@ -430,6 +453,11 @@ static void compliance_mode_recovery(uns
+ xhci_dbg(xhci, "Attempting compliance mode recovery\n");
+ hcd = xhci->shared_hcd;
+
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ temp |= (1 << 31);
++ xhci_writel(xhci, temp, xhci->usb3_ports[i]);
++#endif
++
+ if (hcd->state == HC_STATE_SUSPENDED)
+ usb_hcd_resume_root_hub(hcd);
+
+@@ -478,6 +506,9 @@ bool xhci_compliance_mode_recovery_timer
+ {
+ const char *dmi_product_name, *dmi_sys_vendor;
+
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ return true;
++#endif
+ dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
+ dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
+ if (!dmi_product_name || !dmi_sys_vendor)
+@@ -521,6 +552,10 @@ int xhci_init(struct usb_hcd *hcd)
+ } else {
+ xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
+ }
++
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ mtk_xhci_scheduler_init();
++#endif
+ retval = xhci_mem_init(xhci, GFP_KERNEL);
+ xhci_dbg(xhci, "Finished xhci_init\n");
+
+@@ -664,7 +699,11 @@ int xhci_run(struct usb_hcd *hcd)
+ xhci_dbg(xhci, "// Set the interrupt modulation register\n");
+ temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
+ temp &= ~ER_IRQ_INTERVAL_MASK;
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ temp |= (u32) 16;
++#else
+ temp |= (u32) 160;
++#endif
+ xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
+
+ /* Set the HCD state before we enable the irqs */
+@@ -685,6 +724,9 @@ int xhci_run(struct usb_hcd *hcd)
+ xhci_queue_vendor_command(xhci, 0, 0, 0,
+ TRB_TYPE(TRB_NEC_GET_FW));
+
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ enableXhciAllPortPower(xhci);
++#endif
+ xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
+ return 0;
+ }
+@@ -1002,7 +1044,6 @@ int xhci_resume(struct xhci_hcd *xhci, b
+
+ /* If restore operation fails, re-initialize the HC during resume */
+ if ((temp & STS_SRE) || hibernated) {
+-
+ if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
+ !(xhci_all_ports_seen_u0(xhci))) {
+ del_timer_sync(&xhci->comp_mode_recovery_timer);
+@@ -1586,6 +1627,13 @@ int xhci_drop_endpoint(struct usb_hcd *h
+ u32 drop_flag;
+ u32 new_add_flags, new_drop_flags, new_slot_info;
+ int ret;
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++#if MTK_SCH_NEW
++ struct sch_ep *sch_ep = NULL;
++ int isTT;
++ int ep_type;
++#endif
++#endif
+
+ ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
+ if (ret <= 0)
+@@ -1637,6 +1685,40 @@ int xhci_drop_endpoint(struct usb_hcd *h
+
+ xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
+
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++#if MTK_SCH_NEW
++ slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[udev->slot_id]->out_ctx);
++ if ((slot_ctx->tt_info & 0xff) > 0) {
++ isTT = 1;
++ }
++ else {
++ isTT = 0;
++ }
++ if (usb_endpoint_xfer_int(&ep->desc)) {
++ ep_type = USB_EP_INT;
++ }
++ else if (usb_endpoint_xfer_isoc(&ep->desc)) {
++ ep_type = USB_EP_ISOC;
++ }
++ else if (usb_endpoint_xfer_bulk(&ep->desc)) {
++ ep_type = USB_EP_BULK;
++ }
++ else
++ ep_type = USB_EP_CONTROL;
++
++ sch_ep = mtk_xhci_scheduler_remove_ep(udev->speed, usb_endpoint_dir_in(&ep->desc)
++ , isTT, ep_type, (mtk_u32 *)ep);
++ if (sch_ep != NULL) {
++ kfree(sch_ep);
++ }
++ else {
++ xhci_dbg(xhci, "[MTK]Doesn't find ep_sch instance when removing endpoint\n");
++ }
++#else
++ mtk_xhci_scheduler_remove_ep(xhci, udev, ep);
++#endif
++#endif
++
+ xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
+ (unsigned int) ep->desc.bEndpointAddress,
+ udev->slot_id,
+@@ -1672,6 +1754,18 @@ int xhci_add_endpoint(struct usb_hcd *hc
+ u32 new_add_flags, new_drop_flags, new_slot_info;
+ struct xhci_virt_device *virt_dev;
+ int ret = 0;
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ struct xhci_ep_ctx *in_ep_ctx;
++#if MTK_SCH_NEW
++ struct sch_ep *sch_ep;
++ int isTT;
++ int ep_type;
++ int maxp = 0;
++ int burst = 0;
++ int mult = 0;
++ int interval;
++#endif
++#endif
+
+ ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
+ if (ret <= 0) {
+@@ -1734,6 +1828,56 @@ int xhci_add_endpoint(struct usb_hcd *hc
+ return -ENOMEM;
+ }
+
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
++#if MTK_SCH_NEW
++ slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
++ if ((slot_ctx->tt_info & 0xff) > 0) {
++ isTT = 1;
++ }
++ else {
++ isTT = 0;
++ }
++ if (usb_endpoint_xfer_int(&ep->desc)) {
++ ep_type = USB_EP_INT;
++ }
++ else if (usb_endpoint_xfer_isoc(&ep->desc)) {
++ ep_type = USB_EP_ISOC;
++ }
++ else if (usb_endpoint_xfer_bulk(&ep->desc)) {
++ ep_type = USB_EP_BULK;
++ }
++ else
++ ep_type = USB_EP_CONTROL;
++
++ if (udev->speed == USB_SPEED_FULL || udev->speed == USB_SPEED_HIGH
++ || udev->speed == USB_SPEED_LOW) {
++ maxp = ep->desc.wMaxPacketSize & 0x7FF;
++ burst = ep->desc.wMaxPacketSize >> 11;
++ mult = 0;
++ }
++ else if (udev->speed == USB_SPEED_SUPER) {
++ maxp = ep->desc.wMaxPacketSize & 0x7FF;
++ burst = ep->ss_ep_comp.bMaxBurst;
++ mult = ep->ss_ep_comp.bmAttributes & 0x3;
++ }
++ interval = (1 << ((in_ep_ctx->ep_info >> 16) & 0xff));
++ sch_ep = kmalloc(sizeof(struct sch_ep), GFP_KERNEL);
++ if (mtk_xhci_scheduler_add_ep(udev->speed, usb_endpoint_dir_in(&ep->desc),
++ isTT, ep_type, maxp, interval, burst, mult, (mtk_u32 *)ep
++ , (mtk_u32 *)in_ep_ctx, sch_ep) != SCH_SUCCESS) {
++ xhci_err(xhci, "[MTK] not enough bandwidth\n");
++
++ return -ENOSPC;
++ }
++#else
++ if (mtk_xhci_scheduler_add_ep(xhci, udev, ep, in_ep_ctx) != SCH_SUCCESS) {
++ xhci_err(xhci, "[MTK] not enough bandwidth\n");
++
++ return -ENOSPC;
++ }
++#endif
++#endif
+ ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
+ new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
+
+@@ -2697,7 +2841,7 @@ int xhci_check_bandwidth(struct usb_hcd
+ if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
+ ctrl_ctx->drop_flags == 0)
+ return 0;
+-
++
+ xhci_dbg(xhci, "New Input Control Context:\n");
+ slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
+ xhci_dbg_ctx(xhci, virt_dev->in_ctx,
+@@ -4233,10 +4377,14 @@ static u16 xhci_call_host_update_timeout
+ u16 *timeout)
+ {
+ if (state == USB3_LPM_U1) {
++#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ if (xhci->quirks & XHCI_INTEL_HOST)
++#endif
+ return xhci_calculate_intel_u1_timeout(udev, desc);
+ } else {
++#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ if (xhci->quirks & XHCI_INTEL_HOST)
++#endif
+ return xhci_calculate_intel_u2_timeout(udev, desc);
+ }
+
+@@ -4662,7 +4810,9 @@ int xhci_gen_setup(struct usb_hcd *hcd,
+ /* Accept arbitrarily long scatter-gather lists */
+ hcd->self.sg_tablesize = ~0;
+ /* XHCI controllers don't stop the ep queue on short packets :| */
++#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ hcd->self.no_stop_on_short = 1;
++#endif
+
+ if (usb_hcd_is_primary_hcd(hcd)) {
+ xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
+@@ -4731,6 +4881,10 @@ int xhci_gen_setup(struct usb_hcd *hcd,
+ goto error;
+ xhci_dbg(xhci, "Reset complete\n");
+
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ setInitialReg();
++#endif
++
+ temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
+ if (HCC_64BIT_ADDR(temp)) {
+ xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
+@@ -4755,8 +4909,21 @@ MODULE_DESCRIPTION(DRIVER_DESC);
+ MODULE_AUTHOR(DRIVER_AUTHOR);
+ MODULE_LICENSE("GPL");
+
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++static struct platform_device xhci_platform_dev = {
++ .name = "xhci-hcd",
++ .id = -1,
++ .dev = {
++ .coherent_dma_mask = 0xffffffff,
++ },
++};
++#endif
++
+ static int __init xhci_hcd_init(void)
+ {
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ struct platform_device *pPlatformDev;
++#endif
+ int retval;
+
+ retval = xhci_register_pci();
+@@ -4769,6 +4936,33 @@ static int __init xhci_hcd_init(void)
+ printk(KERN_DEBUG "Problem registering platform driver.");
+ goto unreg_pci;
+ }
++
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++ retval = register_chrdev(XHCI_MTK_TEST_MAJOR, DEVICE_NAME, &xhci_mtk_test_fops);
++
++ u3phy_init();
++ if (u3phy_ops->u2_slew_rate_calibration) {
++ u3phy_ops->u2_slew_rate_calibration(u3phy);
++ u3phy_ops->u2_slew_rate_calibration(u3phy_p1);
++ }
++ else{
++ printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
++ }
++ u3phy_ops->init(u3phy);
++ reinitIP();
++
++ pPlatformDev = &xhci_platform_dev;
++ memset(pPlatformDev, 0, sizeof(struct platform_device));
++ pPlatformDev->name = "xhci-hcd";
++ pPlatformDev->id = -1;
++ pPlatformDev->dev.coherent_dma_mask = 0xffffffff;
++ pPlatformDev->dev.dma_mask = &pPlatformDev->dev.coherent_dma_mask;
++
++ retval = platform_device_register(&xhci_platform_dev);
++ if (retval < 0)
++ xhci_unregister_plat();
++#endif
++
+ /*
+ * Check the compiler generated sizes of structures that must be laid
+ * out in specific ways for hardware access.
+@@ -4786,6 +4980,7 @@ static int __init xhci_hcd_init(void)
+ BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
+ /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
+ BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
++
+ return 0;
+ unreg_pci:
+ xhci_unregister_pci();
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -29,9 +29,24 @@
+ #include <linux/usb/hcd.h>
+
+ /* Code sharing between pci-quirks and xhci hcd */
+-#include "xhci-ext-caps.h"
++#include "xhci-ext-caps.h"
+ #include "pci-quirks.h"
+
++#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
++#define XHC_IRQ (22 + 8)
++#define XHC_IO_START 0x1E1C0000
++#define XHC_IO_LENGTH 0x10000
++/* mtk scheduler bitmasks */
++#define BPKTS(p) ((p) & 0x3f)
++#define BCSCOUNT(p) (((p) & 0x7) << 8)
++#define BBM(p) ((p) << 11)
++#define BOFFSET(p) ((p) & 0x3fff)
++#define BREPEAT(p) (((p) & 0x7fff) << 16)
++#endif
++
++
++
++
+ /* xHCI PCI Configuration Registers */
+ #define XHCI_SBRN_OFFSET (0x60)
+
+@@ -1536,8 +1551,12 @@ struct xhci_hcd {
+ /* Compliance Mode Recovery Data */
+ struct timer_list comp_mode_recovery_timer;
+ u32 port_status_u0;
++#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
++#define COMP_MODE_RCVRY_MSECS 5000
++#else
+ /* Compliance Mode Timer Triggered every 2 seconds */
+ #define COMP_MODE_RCVRY_MSECS 2000
++#endif
+ };
+
+ /* convert between an HCD pointer and the corresponding EHCI_HCD */
+@@ -1703,7 +1722,7 @@ void xhci_urb_free_priv(struct xhci_hcd
+ void xhci_free_command(struct xhci_hcd *xhci,
+ struct xhci_command *command);
+
+-#ifdef CONFIG_PCI
++#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ /* xHCI PCI glue */
+ int xhci_register_pci(void);
+ void xhci_unregister_pci(void);
diff --git a/target/linux/ramips/patches-3.10/0500-spi-mt7621.patch b/target/linux/ramips/patches-3.10/0215-SPI-ralink-add-mt7621-support.patch
similarity index 87%
rename from target/linux/ramips/patches-3.10/0500-spi-mt7621.patch
rename to target/linux/ramips/patches-3.10/0215-SPI-ralink-add-mt7621-support.patch
index b54c6e96dd..ec20066bf3 100644
--- a/target/linux/ramips/patches-3.10/0500-spi-mt7621.patch
+++ b/target/linux/ramips/patches-3.10/0215-SPI-ralink-add-mt7621-support.patch
@@ -1,6 +1,16 @@
+From 1a961f146e65e2716dbe9065baa4c0931fcb6b3e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 05:34:11 +0000
+Subject: [PATCH 215/215] SPI: ralink: add mt7621 support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/spi/spi-rt2880.c | 218 +++++++++++++++++++++++++++++++++++++++++++---
+ 1 file changed, 205 insertions(+), 13 deletions(-)
+
--- a/drivers/spi/spi-rt2880.c
+++ b/drivers/spi/spi-rt2880.c
-@@ -21,8 +21,11 @@
+@@ -21,8 +21,13 @@
#include <linux/io.h>
#include <linux/reset.h>
#include <linux/spi/spi.h>
@@ -8,11 +18,13 @@
#include <linux/platform_device.h>
+#include <ralink_regs.h>
++
++#define SPI_BPW_MASK(bits) BIT((bits) - 1)
+
#define DRIVER_NAME "spi-rt2880"
/* only one slave is supported*/
#define RALINK_NUM_CHIPSELECTS 1
-@@ -63,6 +66,25 @@
+@@ -63,6 +68,25 @@
/* SPIFIFOSTAT register bit field */
#define SPIFIFOSTAT_TXFULL BIT(17)
@@ -38,7 +50,7 @@
struct rt2880_spi {
struct spi_master *master;
void __iomem *base;
-@@ -70,6 +92,8 @@ struct rt2880_spi {
+@@ -70,6 +94,8 @@ struct rt2880_spi {
unsigned int speed;
struct clk *clk;
spinlock_t lock;
@@ -47,7 +59,7 @@
};
static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
-@@ -149,6 +173,17 @@ static int rt2880_spi_baudrate_set(struc
+@@ -149,6 +175,17 @@ static int rt2880_spi_baudrate_set(struc
return 0;
}
@@ -65,7 +77,7 @@
/*
* called only when no transfer is active on the bus
*/
-@@ -164,7 +199,7 @@ rt2880_spi_setup_transfer(struct spi_dev
+@@ -164,7 +201,7 @@ rt2880_spi_setup_transfer(struct spi_dev
if (rs->speed != speed) {
dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
@@ -74,7 +86,7 @@
if (rc)
return rc;
}
-@@ -180,6 +215,17 @@ static void rt2880_spi_set_cs(struct rt2
+@@ -180,6 +217,17 @@ static void rt2880_spi_set_cs(struct rt2
rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
}
@@ -92,7 +104,7 @@
static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
{
int i;
-@@ -198,8 +244,26 @@ static inline int rt2880_spi_wait_till_r
+@@ -198,8 +246,26 @@ static inline int rt2880_spi_wait_till_r
return -ETIMEDOUT;
}
@@ -120,7 +132,7 @@
{
struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
unsigned count = 0;
-@@ -239,6 +303,100 @@ out:
+@@ -239,6 +305,100 @@ out:
return count;
}
@@ -221,7 +233,7 @@
static int rt2880_spi_transfer_one_message(struct spi_master *master,
struct spi_message *m)
{
-@@ -280,25 +438,25 @@ static int rt2880_spi_transfer_one_messa
+@@ -280,25 +440,25 @@ static int rt2880_spi_transfer_one_messa
}
if (!cs_active) {
@@ -251,7 +263,7 @@
m->status = status;
spi_finalize_current_message(master);
-@@ -334,8 +492,41 @@ static void rt2880_spi_reset(struct rt28
+@@ -334,8 +494,41 @@ static void rt2880_spi_reset(struct rt28
rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
}
@@ -293,7 +305,7 @@
struct spi_master *master;
struct rt2880_spi *rs;
unsigned long flags;
-@@ -344,6 +535,10 @@ static int rt2880_spi_probe(struct platf
+@@ -344,6 +537,10 @@ static int rt2880_spi_probe(struct platf
int status = 0;
struct clk *clk;
@@ -304,7 +316,7 @@
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, r);
if (IS_ERR(base))
-@@ -382,12 +577,13 @@ static int rt2880_spi_probe(struct platf
+@@ -382,12 +579,13 @@ static int rt2880_spi_probe(struct platf
rs->clk = clk;
rs->master = master;
rs->sys_freq = clk_get_rate(rs->clk);
@@ -319,7 +331,7 @@
return spi_register_master(master);
}
-@@ -408,12 +604,6 @@ static int rt2880_spi_remove(struct plat
+@@ -408,12 +606,6 @@ static int rt2880_spi_remove(struct plat
MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/target/linux/ramips/patches-3.10/0216-NET-ralink-add-mt7621-SDK-ethernet-driver.patch b/target/linux/ramips/patches-3.10/0216-NET-ralink-add-mt7621-SDK-ethernet-driver.patch
new file mode 100644
index 0000000000..a3a5ec282d
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0216-NET-ralink-add-mt7621-SDK-ethernet-driver.patch
@@ -0,0 +1,6045 @@
+From 6e10c9b7ab93cb105dc2779769c48949ebc60ee7 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 08:51:14 +0000
+Subject: [PATCH 1/3] foo
+
+---
+ drivers/net/ethernet/raeth/Kconfig | 343 +++++++
+ drivers/net/ethernet/raeth/Makefile | 7 +
+ drivers/net/ethernet/raeth/ethtool_readme.txt | 44 +
+ drivers/net/ethernet/raeth/mii_mgr.c | 166 ++++
+ drivers/net/ethernet/raeth/ra2882ethreg.h | 1268 +++++++++++++++++++++++++
+ drivers/net/ethernet/raeth/ra_ioctl.h | 92 ++
+ drivers/net/ethernet/raeth/ra_mac.c | 93 ++
+ drivers/net/ethernet/raeth/ra_mac.h | 35 +
+ drivers/net/ethernet/raeth/raether.c | 663 +++++++++++++
+ drivers/net/ethernet/raeth/raether.h | 92 ++
+ drivers/net/ethernet/raeth/raether_pdma.c | 202 ++++
+ drivers/net/ethernet/raeth/raether_qdma.c | 805 ++++++++++++++++
+ drivers/net/ethernet/ralink/gsw_mt7620a.c | 15 +-
+ drivers/net/ethernet/ralink/mt7530.c | 2 +-
+ drivers/net/ethernet/ralink/mt7621.c | 253 +++++
+ drivers/net/ethernet/ralink/mt762x.c | 295 ++++++
+ drivers/net/ethernet/ralink/mt762x.h | 38 +
+ drivers/net/ethernet/ralink/ralink_soc_eth.c | 25 +-
+ drivers/net/ethernet/ralink/ralink_soc_eth.h | 9 +-
+ drivers/net/ethernet/ralink/soc_mt7621.c | 5 +-
+ 20 files changed, 4429 insertions(+), 23 deletions(-)
+ create mode 100644 drivers/net/ethernet/raeth/Kconfig
+ create mode 100644 drivers/net/ethernet/raeth/Makefile
+ create mode 100644 drivers/net/ethernet/raeth/ethtool_readme.txt
+ create mode 100644 drivers/net/ethernet/raeth/mii_mgr.c
+ create mode 100644 drivers/net/ethernet/raeth/ra2882ethreg.h
+ create mode 100644 drivers/net/ethernet/raeth/ra_ioctl.h
+ create mode 100644 drivers/net/ethernet/raeth/ra_mac.c
+ create mode 100644 drivers/net/ethernet/raeth/ra_mac.h
+ create mode 100644 drivers/net/ethernet/raeth/raether.c
+ create mode 100644 drivers/net/ethernet/raeth/raether.h
+ create mode 100755 drivers/net/ethernet/raeth/raether_pdma.c
+ create mode 100644 drivers/net/ethernet/raeth/raether_qdma.c
+ create mode 100644 drivers/net/ethernet/ralink/mt7621.c
+ create mode 100644 drivers/net/ethernet/ralink/mt762x.c
+ create mode 100644 drivers/net/ethernet/ralink/mt762x.h
+
+--- /dev/null
++++ b/drivers/net/ethernet/raeth/Kconfig
+@@ -0,0 +1,344 @@
++
++config RA_NAT_NONE
++ bool
++ default y
++ depends on RALINK
++
++config MT7621_ASIC
++ bool
++ default y
++ depends on SOC_MT7621
++
++config RALINK_MT7621
++ bool
++ default y
++ depends on SOC_MT7621
++
++config RAETH
++ tristate "Ralink GMAC"
++ depends on SOC_MT7621
++ ---help---
++ This driver supports Ralink gigabit ethernet family of
++ adapters.
++
++config PDMA_NEW
++ bool
++ default y if (RALINK_MT7620 || RALINK_MT7621)
++ depends on RAETH
++
++config RAETH_SCATTER_GATHER_RX_DMA
++ bool
++ default y if (RALINK_MT7620 || RALINK_MT7621)
++ depends on RAETH
++
++
++choice
++ prompt "Network BottomHalves"
++ depends on RAETH
++ default RA_NETWORK_WORKQUEUE_BH
++
++ config RA_NETWORK_TASKLET_BH
++ bool "Tasklet"
++
++ config RA_NETWORK_WORKQUEUE_BH
++ bool "Work Queue"
++
++ config RAETH_NAPI
++ bool "NAPI"
++
++endchoice
++
++#config TASKLET_WORKQUEUE_SW
++# bool "Tasklet and Workqueue switch"
++# depends on RA_NETWORK_TASKLET_BH
++
++config RAETH_SKB_RECYCLE_2K
++ bool "SKB Recycling"
++ depends on RAETH
++
++config RAETH_SPECIAL_TAG
++ bool "Ralink Special Tag (0x810x)"
++ depends on RAETH && RT_3052_ESW
++
++#config RAETH_JUMBOFRAME
++# bool "Jumbo Frame up to 4K bytes"
++# depends on RAETH && !(RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_MT7628)
++
++config RAETH_CHECKSUM_OFFLOAD
++ bool "TCP/UDP/IP checksum offload"
++ default y
++ depends on RAETH && !RALINK_RT2880
++
++#config RAETH_SW_FC
++# bool "When TX ring is full, inform kernel stop transmit and stop RX handler"
++# default n
++# depends on RAETH
++
++config 32B_DESC
++ bool "32bytes TX/RX description"
++ default n
++ depends on RAETH && (RALINK_MT7620 || RALINK_MT7621)
++ ---help---
++ At this moment, you cannot enable 32B description with Multiple RX ring at the same time.
++
++config RAETH_LRO
++ bool "LRO (Large Receive Offload )"
++ select INET_LRO
++ depends on RAETH && (RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621)
++
++config RAETH_HW_VLAN_TX
++ bool "Transmit VLAN HW (DoubleVLAN is not supported)"
++ depends on RAETH && !(RALINK_RT5350 || RALINK_MT7628)
++ ---help---
++ Please disable HW_VLAN_TX if you need double vlan
++
++config RAETH_HW_VLAN_RX
++ bool "Receive VLAN HW (DoubleVLAN is not supported)"
++ depends on RAETH && RALINK_MT7621
++ ---help---
++ Please disable HW_VLAN_RX if you need double vlan
++
++config RAETH_TSO
++ bool "TSOV4 (Tcp Segmentaton Offload)"
++ depends on (RAETH_HW_VLAN_TX && (RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)) || RALINK_MT7621
++
++config RAETH_TSOV6
++ bool "TSOV6 (Tcp Segmentaton Offload)"
++ depends on RAETH_TSO
++
++config RAETH_RW_PDMAPTR_FROM_VAR
++ bool
++ default y if RALINK_RT6855A || RALINK_MT7620
++ depends on RAETH
++
++#config RAETH_QOS
++# bool "QoS Feature"
++# depends on RAETH && !RALINK_RT2880 && !RALINK_MT7620 && !RALINK_MT7621 && !RAETH_TSO
++
++choice
++ prompt "QoS Type"
++ depends on RAETH_QOS
++ default DSCP_QOS_DSCP
++
++config RAETH_QOS_DSCP_BASED
++ bool "DSCP-based"
++ depends on RAETH_QOS
++
++config RAETH_QOS_VPRI_BASED
++ bool "VPRI-based"
++ depends on RAETH_QOS
++
++endchoice
++
++config RAETH_QDMA
++ bool "Choose QDMA instead PDMA"
++ default n
++ depends on RAETH && RALINK_MT7621
++
++choice
++ prompt "GMAC is connected to"
++ depends on RAETH
++ default GE1_RGMII_FORCE_1000
++
++config GE1_MII_FORCE_100
++ bool "MII_FORCE_100 (10/100M Switch)"
++ depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
++
++config GE1_MII_AN
++ bool "MII_AN (100Phy)"
++ depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
++
++config GE1_RVMII_FORCE_100
++ bool "RvMII_FORCE_100 (CPU)"
++ depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
++
++config GE1_RGMII_FORCE_1000
++ bool "RGMII_FORCE_1000 (GigaSW, CPU)"
++ depends on (RALINK_RT2880 || RALINK_RT3883)
++ select RALINK_SPI
++
++config GE1_RGMII_FORCE_1000
++ bool "RGMII_FORCE_1000 (GigaSW, CPU)"
++ depends on (RALINK_MT7621)
++ select RT_3052_ESW
++
++config GE1_TRGMII_FORCE_1200
++ bool "TRGMII_FORCE_1200 (GigaSW, CPU)"
++ depends on (RALINK_MT7621)
++ select RT_3052_ESW
++
++config GE1_RGMII_AN
++ bool "RGMII_AN (GigaPhy)"
++ depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
++
++config GE1_RGMII_NONE
++ bool "NONE (NO CONNECT)"
++ depends on (RALINK_MT7621)
++
++endchoice
++
++config RT_3052_ESW
++ bool "Ralink Embedded Switch"
++ default y
++ depends on (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628)
++
++config LAN_WAN_SUPPORT
++ bool "LAN/WAN Partition"
++ depends on RAETH_ROUTER || RT_3052_ESW
++
++choice
++ prompt "Switch Board Layout Type"
++ depends on LAN_WAN_SUPPORT || P5_RGMII_TO_MAC_MODE || GE1_RGMII_FORCE_1000 || GE1_TRGMII_FORCE_1200 || GE2_RGMII_FORCE_1000
++ default WAN_AT_P0
++
++ config WAN_AT_P4
++ bool "LLLL/W"
++
++ config WAN_AT_P0
++ bool "W/LLLL"
++endchoice
++
++config RALINK_VISTA_BASIC
++ bool 'Vista Basic Logo for IC+ 175C'
++ depends on LAN_WAN_SUPPORT && (RALINK_RT2880 || RALINK_RT3883)
++
++config ESW_DOUBLE_VLAN_TAG
++ bool
++ default y if RT_3052_ESW
++
++config RAETH_HAS_PORT4
++ bool "Port 4 Support"
++ depends on RAETH && RALINK_MT7620
++choice
++ prompt "Target Mode"
++ depends on RAETH_HAS_PORT4
++ default P4_RGMII_TO_MAC_MODE
++
++ config P4_MAC_TO_PHY_MODE
++ bool "Giga_Phy (RGMII)"
++ config GE_RGMII_MT7530_P0_AN
++ bool "GE_RGMII_MT7530_P0_AN (MT7530 Internal GigaPhy)"
++ config GE_RGMII_MT7530_P4_AN
++ bool "GE_RGMII_MT7530_P4_AN (MT7530 Internal GigaPhy)"
++ config P4_RGMII_TO_MAC_MODE
++ bool "Giga_SW/iNIC (RGMII)"
++ config P4_MII_TO_MAC_MODE
++ bool "External_CPU (MII_RvMII)"
++ config P4_RMII_TO_MAC_MODE
++ bool "External_CPU (RvMII_MII)"
++endchoice
++
++config MAC_TO_GIGAPHY_MODE_ADDR2
++ hex "Port4 Phy Address"
++ default 0x4
++ depends on P4_MAC_TO_PHY_MODE
++
++config RAETH_HAS_PORT5
++ bool "Port 5 Support"
++ depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)
++choice
++ prompt "Target Mode"
++ depends on RAETH_HAS_PORT5
++ default P5_RGMII_TO_MAC_MODE
++
++ config P5_MAC_TO_PHY_MODE
++ bool "Giga_Phy (RGMII)"
++ config P5_RGMII_TO_MAC_MODE
++ bool "Giga_SW/iNIC (RGMII)"
++ config P5_RGMII_TO_MT7530_MODE
++ bool "MT7530 Giga_SW (RGMII)"
++ depends on RALINK_MT7620
++ config P5_MII_TO_MAC_MODE
++ bool "External_CPU (MII_RvMII)"
++ config P5_RMII_TO_MAC_MODE
++ bool "External_CPU (RvMII_MII)"
++endchoice
++
++config MAC_TO_GIGAPHY_MODE_ADDR
++ hex "GE1 Phy Address"
++ default 0x1F
++ depends on GE1_MII_AN || GE1_RGMII_AN
++
++config MAC_TO_GIGAPHY_MODE_ADDR
++ hex "Port5 Phy Address"
++ default 0x5
++ depends on P5_MAC_TO_PHY_MODE
++
++config RAETH_GMAC2
++ bool "GMAC2 Support"
++ depends on RAETH && (RALINK_RT3883 || RALINK_MT7621)
++
++choice
++ prompt "GMAC2 is connected to"
++ depends on RAETH_GMAC2
++ default GE2_RGMII_AN
++
++config GE2_MII_FORCE_100
++ bool "MII_FORCE_100 (10/100M Switch)"
++ depends on RAETH_GMAC2
++
++config GE2_MII_AN
++ bool "MII_AN (100Phy)"
++ depends on RAETH_GMAC2
++
++config GE2_RVMII_FORCE_100
++ bool "RvMII_FORCE_100 (CPU)"
++ depends on RAETH_GMAC2
++
++config GE2_RGMII_FORCE_1000
++ bool "RGMII_FORCE_1000 (GigaSW, CPU)"
++ depends on RAETH_GMAC2
++ select RALINK_SPI
++
++config GE2_RGMII_AN
++ bool "RGMII_AN (GigaPhy)"
++ depends on RAETH_GMAC2
++
++config GE2_INTERNAL_GPHY
++ bool "Internal GigaPHY"
++ depends on RAETH_GMAC2
++ select LAN_WAN_SUPPORT
++
++endchoice
++
++config GE_RGMII_INTERNAL_P0_AN
++ bool
++ depends on GE2_INTERNAL_GPHY
++ default y if WAN_AT_P0
++
++config GE_RGMII_INTERNAL_P4_AN
++ bool
++ depends on GE2_INTERNAL_GPHY
++ default y if WAN_AT_P4
++
++config MAC_TO_GIGAPHY_MODE_ADDR2
++ hex
++ default 0 if GE_RGMII_INTERNAL_P0_AN
++ default 4 if GE_RGMII_INTERNAL_P4_AN
++ depends on GE_RGMII_INTERNAL_P0_AN || GE_RGMII_INTERNAL_P4_AN
++
++config MAC_TO_GIGAPHY_MODE_ADDR2
++ hex "GE2 Phy Address"
++ default 0x1E
++ depends on GE2_MII_AN || GE2_RGMII_AN
++
++#force 100M
++config RAETH_ROUTER
++bool
++default y if GE1_MII_FORCE_100 || GE2_MII_FORCE_100 || GE1_RVMII_FORCE_100 || GE2_RVMII_FORCE_100
++
++#force 1000M
++config MAC_TO_MAC_MODE
++bool
++default y if GE1_RGMII_FORCE_1000 || GE2_RGMII_FORCE_1000
++depends on (RALINK_RT2880 || RALINK_RT3883)
++
++#AN
++config GIGAPHY
++bool
++default y if GE1_RGMII_AN || GE2_RGMII_AN
++
++#AN
++config 100PHY
++bool
++default y if GE1_MII_AN || GE2_MII_AN
+--- /dev/null
++++ b/drivers/net/ethernet/raeth/Makefile
+@@ -0,0 +1,7 @@
++obj-$(CONFIG_RAETH) += raeth.o
++raeth-objs := ra_mac.o mii_mgr.o
++raeth-objs += raether_pdma.o
++EXTRA_CFLAGS += -DWORKQUEUE_BH
++#EXTRA_CFLAGS += -DCONFIG_RAETH_MULTIPLE_RX_RING
++
++raeth-objs += raether.o
+--- /dev/null
++++ b/drivers/net/ethernet/raeth/ethtool_readme.txt
+@@ -0,0 +1,44 @@
++
++Ethtool readme for selecting different PHY address.
++
++Before doing any ethtool command you should make sure the current PHY
++address is expected. The default PHY address is 1(port 1).
++
++You can change current PHY address to X(0~4) by doing follow command:
++# echo X > /proc/rt2880/gmac
++
++Ethtool command also would show the current PHY address as following.
++
++# ethtool eth2
++Settings for eth2:
++ Supported ports: [ TP MII ]
++ Supported link modes: 10baseT/Half 10baseT/Full
++ 100baseT/Half 100baseT/Full
++ Supports auto-negotiation: Yes
++ Advertised link modes: 10baseT/Half 10baseT/Full
++ 100baseT/Half 100baseT/Full
++ Advertised auto-negotiation: No
++ Speed: 10Mb/s
++ Duplex: Full
++ Port: MII
++ PHYAD: 1
++ Transceiver: internal
++ Auto-negotiation: off
++ Current message level: 0x00000000 (0)
++ Link detected: no
++
++
++The "PHYAD" field shows the current PHY address.
++
++
++
++Usage example
++1) show port1 info
++# echo 1 > /proc/rt2880/gmac # change phy address to 1
++# ethtool eth2
++
++2) show port0 info
++# echo 0 > /proc/rt2880/gmac # change phy address to 0
++# ethtool eth2
++
++
+--- /dev/null
++++ b/drivers/net/ethernet/raeth/mii_mgr.c
+@@ -0,0 +1,166 @@
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/netdevice.h>
++
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
++#include <asm/rt2880/rt_mmap.h>
++#endif
++
++#include "ra2882ethreg.h"
++#include "raether.h"
++
++
++#define PHY_CONTROL_0 0x0004
++#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
++#define enable_mdio(x)
++
++
++u32 __mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
++{
++ u32 volatile status = 0;
++ u32 rc = 0;
++ unsigned long volatile t_start = jiffies;
++ u32 volatile data = 0;
++
++ /* We enable mdio gpio purpose register, and disable it when exit. */
++ enable_mdio(1);
++
++ // make sure previous read operation is complete
++ while (1) {
++ // 0 : Read/write operation complete
++ if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
++ {
++ break;
++ }
++ else if (time_after(jiffies, t_start + 5*HZ)) {
++ enable_mdio(0);
++ printk("\n MDIO Read operation is ongoing !!\n");
++ return rc;
++ }
++ }
++
++ data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
++ sysRegWrite(MDIO_PHY_CONTROL_0, data);
++ data |= (1<<31);
++ sysRegWrite(MDIO_PHY_CONTROL_0, data);
++ //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
++
++
++ // make sure read operation is complete
++ t_start = jiffies;
++ while (1) {
++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
++ status = sysRegRead(MDIO_PHY_CONTROL_0);
++ *read_data = (u32)(status & 0x0000FFFF);
++
++ enable_mdio(0);
++ return 1;
++ }
++ else if (time_after(jiffies, t_start+5*HZ)) {
++ enable_mdio(0);
++ printk("\n MDIO Read operation is ongoing and Time Out!!\n");
++ return 0;
++ }
++ }
++}
++
++u32 __mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
++{
++ unsigned long volatile t_start=jiffies;
++ u32 volatile data;
++
++ enable_mdio(1);
++
++ // make sure previous write operation is complete
++ while(1) {
++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
++ {
++ break;
++ }
++ else if (time_after(jiffies, t_start + 5 * HZ)) {
++ enable_mdio(0);
++ printk("\n MDIO Write operation ongoing\n");
++ return 0;
++ }
++ }
++ /*add 1 us delay to make sequencial write more robus*/
++ udelay(1);
++
++ data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
++ sysRegWrite(MDIO_PHY_CONTROL_0, data);
++ data |= (1<<31);
++ sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
++ //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
++
++ t_start = jiffies;
++
++ // make sure write operation is complete
++ while (1) {
++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
++ {
++ enable_mdio(0);
++ return 1;
++ }
++ else if (time_after(jiffies, t_start + 5 * HZ)) {
++ enable_mdio(0);
++ printk("\n MDIO Write operation Time Out\n");
++ return 0;
++ }
++ }
++}
++
++u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
++{
++ u32 low_word;
++ u32 high_word;
++ if(phy_addr==31)
++ {
++ //phase1: write page address phase
++ if(__mii_mgr_write(phy_addr, 0x1f, ((phy_register >> 6) & 0x3FF))) {
++ //phase2: write address & read low word phase
++ if(__mii_mgr_read(phy_addr, (phy_register >> 2) & 0xF, &low_word)) {
++ //phase3: write address & read high word phase
++ if(__mii_mgr_read(phy_addr, (0x1 << 4), &high_word)) {
++ *read_data = (high_word << 16) | (low_word & 0xFFFF);
++ return 1;
++ }
++ }
++ }
++ } else
++ {
++ if(__mii_mgr_read(phy_addr, phy_register, read_data)) {
++ return 1;
++ }
++ }
++
++ return 0;
++}
++
++u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
++{
++ if(phy_addr == 31)
++ {
++ //phase1: write page address phase
++ if(__mii_mgr_write(phy_addr, 0x1f, (phy_register >> 6) & 0x3FF)) {
++ //phase2: write address & read low word phase
++ if(__mii_mgr_write(phy_addr, ((phy_register >> 2) & 0xF), write_data & 0xFFFF)) {
++ //phase3: write address & read high word phase
++ if(__mii_mgr_write(phy_addr, (0x1 << 4), write_data >> 16)) {
++ return 1;
++ }
++ }
++ }
++ } else
++ {
++ if(__mii_mgr_write(phy_addr, phy_register, write_data)) {
++ return 1;
++ }
++ }
++
++ return 0;
++}
++
++EXPORT_SYMBOL(mii_mgr_write);
++EXPORT_SYMBOL(mii_mgr_read);
+--- /dev/null
++++ b/drivers/net/ethernet/raeth/ra2882ethreg.h
+@@ -0,0 +1,1268 @@
++#ifndef RA2882ETHREG_H
++#define RA2882ETHREG_H
++
++#include <linux/mii.h> // for struct mii_if_info in ra2882ethreg.h
++#include <linux/version.h> /* check linux version for 2.4 and 2.6 compatibility */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
++#include <asm/rt2880/rt_mmap.h>
++#endif
++#include "raether.h"
++
++#ifdef WORKQUEUE_BH
++#include <linux/workqueue.h>
++#endif // WORKQUEUE_BH //
++#ifdef CONFIG_RAETH_LRO
++#include <linux/inet_lro.h>
++#endif
++
++#define MAX_PACKET_SIZE 1514
++#define MIN_PACKET_SIZE 60
++
++#define phys_to_bus(a) (a & 0x1FFFFFFF)
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
++#define BIT(x) ((1 << x))
++#endif
++#define ETHER_ADDR_LEN 6
++
++/* Phy Vender ID list */
++
++#define EV_ICPLUS_PHY_ID0 0x0243
++#define EV_ICPLUS_PHY_ID1 0x0D90
++#define EV_MARVELL_PHY_ID0 0x0141
++#define EV_MARVELL_PHY_ID1 0x0CC2
++#define EV_VTSS_PHY_ID0 0x0007
++#define EV_VTSS_PHY_ID1 0x0421
++
++/*
++ FE_INT_STATUS
++*/
++#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
++ defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
++
++#define RX_COHERENT BIT(31)
++#define RX_DLY_INT BIT(30)
++#define TX_COHERENT BIT(29)
++#define TX_DLY_INT BIT(28)
++
++#define RX_DONE_INT1 BIT(17)
++#define RX_DONE_INT0 BIT(16)
++
++#define TX_DONE_INT3 BIT(3)
++#define TX_DONE_INT2 BIT(2)
++#define TX_DONE_INT1 BIT(1)
++#define TX_DONE_INT0 BIT(0)
++
++#if defined (CONFIG_RALINK_MT7621)
++#define RLS_COHERENT BIT(29)
++#define RLS_DLY_INT BIT(28)
++#define RLS_DONE_INT BIT(0)
++#endif
++
++#else
++//#define CNT_PPE_AF BIT(31)
++//#define CNT_GDM_AF BIT(29)
++#define PSE_P2_FC BIT(26)
++#define GDM_CRC_DROP BIT(25)
++#define PSE_BUF_DROP BIT(24)
++#define GDM_OTHER_DROP BIT(23)
++#define PSE_P1_FC BIT(22)
++#define PSE_P0_FC BIT(21)
++#define PSE_FQ_EMPTY BIT(20)
++#define GE1_STA_CHG BIT(18)
++#define TX_COHERENT BIT(17)
++#define RX_COHERENT BIT(16)
++
++#define TX_DONE_INT3 BIT(11)
++#define TX_DONE_INT2 BIT(10)
++#define TX_DONE_INT1 BIT(9)
++#define TX_DONE_INT0 BIT(8)
++#define RX_DONE_INT1 RX_DONE_INT0
++#define RX_DONE_INT0 BIT(2)
++#define TX_DLY_INT BIT(1)
++#define RX_DLY_INT BIT(0)
++#endif
++
++#define FE_INT_ALL (TX_DONE_INT3 | TX_DONE_INT2 | \
++ TX_DONE_INT1 | TX_DONE_INT0 | \
++ RX_DONE_INT0 )
++
++#if defined (CONFIG_RALINK_MT7621)
++#define QFE_INT_ALL (RLS_DONE_INT | RX_DONE_INT0 | RX_DONE_INT1)
++#define QFE_INT_DLY_INIT (RLS_DLY_INT | RX_DLY_INT)
++
++#define NUM_QDMA_PAGE 256
++#define QDMA_PAGE_SIZE 2048
++#endif
++/*
++ * SW_INT_STATUS
++ */
++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
++#define PORT0_QUEUE_FULL BIT(14) //port0 queue full
++#define PORT1_QUEUE_FULL BIT(15) //port1 queue full
++#define PORT2_QUEUE_FULL BIT(16) //port2 queue full
++#define PORT3_QUEUE_FULL BIT(17) //port3 queue full
++#define PORT4_QUEUE_FULL BIT(18) //port4 queue full
++#define PORT5_QUEUE_FULL BIT(19) //port5 queue full
++#define PORT6_QUEUE_FULL BIT(20) //port6 queue full
++#define SHARED_QUEUE_FULL BIT(23) //shared queue full
++#define QUEUE_EXHAUSTED BIT(24) //global queue is used up and all packets are dropped
++#define BC_STROM BIT(25) //the device is undergoing broadcast storm
++#define PORT_ST_CHG BIT(26) //Port status change
++#define UNSECURED_ALERT BIT(27) //Intruder alert
++#define ABNORMAL_ALERT BIT(28) //Abnormal
++
++#define ESW_ISR (RALINK_ETH_SW_BASE + 0x00)
++#define ESW_IMR (RALINK_ETH_SW_BASE + 0x04)
++#define ESW_INT_ALL (PORT_ST_CHG)
++
++#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
++ defined (CONFIG_RALINK_MT7620)
++#define MIB_INT BIT(25)
++#define ACL_INT BIT(24)
++#define P5_LINK_CH BIT(5)
++#define P4_LINK_CH BIT(4)
++#define P3_LINK_CH BIT(3)
++#define P2_LINK_CH BIT(2)
++#define P1_LINK_CH BIT(1)
++#define P0_LINK_CH BIT(0)
++
++#define RX_GOCT_CNT BIT(4)
++#define RX_GOOD_CNT BIT(6)
++#define TX_GOCT_CNT BIT(17)
++#define TX_GOOD_CNT BIT(19)
++
++#define MSK_RX_GOCT_CNT BIT(4)
++#define MSK_RX_GOOD_CNT BIT(6)
++#define MSK_TX_GOCT_CNT BIT(17)
++#define MSK_TX_GOOD_CNT BIT(19)
++#define MSK_CNT_INT_ALL (MSK_RX_GOCT_CNT | MSK_RX_GOOD_CNT | MSK_TX_GOCT_CNT | MSK_TX_GOOD_CNT)
++//#define MSK_CNT_INT_ALL (MSK_RX_GOOD_CNT | MSK_TX_GOOD_CNT)
++
++
++#define ESW_IMR (RALINK_ETH_SW_BASE + 0x7000 + 0x8)
++#define ESW_ISR (RALINK_ETH_SW_BASE + 0x7000 + 0xC)
++#define ESW_INT_ALL (P0_LINK_CH | P1_LINK_CH | P2_LINK_CH | P3_LINK_CH | P4_LINK_CH | P5_LINK_CH | ACL_INT | MIB_INT)
++#define ESW_AISR (RALINK_ETH_SW_BASE + 0x8)
++#define ESW_P0_IntSn (RALINK_ETH_SW_BASE + 0x4004)
++#define ESW_P1_IntSn (RALINK_ETH_SW_BASE + 0x4104)
++#define ESW_P2_IntSn (RALINK_ETH_SW_BASE + 0x4204)
++#define ESW_P3_IntSn (RALINK_ETH_SW_BASE + 0x4304)
++#define ESW_P4_IntSn (RALINK_ETH_SW_BASE + 0x4404)
++#define ESW_P5_IntSn (RALINK_ETH_SW_BASE + 0x4504)
++#define ESW_P6_IntSn (RALINK_ETH_SW_BASE + 0x4604)
++#define ESW_P0_IntMn (RALINK_ETH_SW_BASE + 0x4008)
++#define ESW_P1_IntMn (RALINK_ETH_SW_BASE + 0x4108)
++#define ESW_P2_IntMn (RALINK_ETH_SW_BASE + 0x4208)
++#define ESW_P3_IntMn (RALINK_ETH_SW_BASE + 0x4308)
++#define ESW_P4_IntMn (RALINK_ETH_SW_BASE + 0x4408)
++#define ESW_P5_IntMn (RALINK_ETH_SW_BASE + 0x4508)
++#define ESW_P6_IntMn (RALINK_ETH_SW_BASE + 0x4608)
++
++#if defined (CONFIG_RALINK_MT7620)
++#define ESW_P7_IntSn (RALINK_ETH_SW_BASE + 0x4704)
++#define ESW_P7_IntMn (RALINK_ETH_SW_BASE + 0x4708)
++#endif
++
++
++#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x7000)
++
++#elif defined (CONFIG_RALINK_MT7621)
++
++#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x0000)
++
++#define P5_LINK_CH BIT(5)
++#define P4_LINK_CH BIT(4)
++#define P3_LINK_CH BIT(3)
++#define P2_LINK_CH BIT(2)
++#define P1_LINK_CH BIT(1)
++#define P0_LINK_CH BIT(0)
++
++
++#endif // CONFIG_RALINK_RT3052 || CONFIG_RALINK_RT3352 || CONFIG_RALINK_RT5350 || defined (CONFIG_RALINK_MT7628)//
++
++#define RX_BUF_ALLOC_SIZE 2000
++#define FASTPATH_HEADROOM 64
++
++#define ETHER_BUFFER_ALIGN 32 ///// Align on a cache line
++
++#define ETHER_ALIGNED_RX_SKB_ADDR(addr) \
++ ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \
++ ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
++
++#ifdef CONFIG_PSEUDO_SUPPORT
++typedef struct _PSEUDO_ADAPTER {
++ struct net_device *RaethDev;
++ struct net_device *PseudoDev;
++ struct net_device_stats stat;
++#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
++ struct mii_if_info mii_info;
++#endif
++
++} PSEUDO_ADAPTER, PPSEUDO_ADAPTER;
++
++#define MAX_PSEUDO_ENTRY 1
++#endif
++
++
++
++/* Register Categories Definition */
++#define RAFRAMEENGINE_OFFSET 0x0000
++#define RAGDMA_OFFSET 0x0020
++#define RAPSE_OFFSET 0x0040
++#define RAGDMA2_OFFSET 0x0060
++#define RACDMA_OFFSET 0x0080
++#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
++ defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
++
++#define RAPDMA_OFFSET 0x0800
++#define SDM_OFFSET 0x0C00
++#else
++#define RAPDMA_OFFSET 0x0100
++#endif
++#define RAPPE_OFFSET 0x0200
++#define RACMTABLE_OFFSET 0x0400
++#define RAPOLICYTABLE_OFFSET 0x1000
++
++
++/* Register Map Detail */
++/* RT3883 */
++#define SYSCFG1 (RALINK_SYSCTL_BASE + 0x14)
++
++#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
++
++/* 1. PDMA */
++#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x000)
++#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x004)
++#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x008)
++#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00C)
++
++#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x010)
++#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x014)
++#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x018)
++#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x01C)
++
++#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x020)
++#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x024)
++#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x028)
++#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x02C)
++
++#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x030)
++#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x034)
++#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x038)
++#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x03C)
++
++#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x100)
++#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x104)
++#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x108)
++#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10C)
++
++#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x110)
++#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x114)
++#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x118)
++#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x11C)
++
++#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x200)
++#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x204)
++#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x208)
++#define PDMA_RST_CFG (PDMA_RST_IDX)
++#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20C)
++#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x210)
++#define INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x220)
++#define FE_INT_STATUS (INT_STATUS)
++#define INT_MASK (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x228)
++#define FE_INT_ENABLE (INT_MASK)
++#define PDMA_WRR (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
++#define PDMA_SCH_CFG (PDMA_WRR)
++
++#define SDM_CON (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x00) //Switch DMA configuration
++#define SDM_RRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x04) //Switch DMA Rx Ring
++#define SDM_TRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x08) //Switch DMA Tx Ring
++#define SDM_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x0C) //Switch MAC address LSB
++#define SDM_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10) //Switch MAC Address MSB
++#define SDM_TPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x100) //Switch DMA Tx packet count
++#define SDM_TBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x104) //Switch DMA Tx byte count
++#define SDM_RPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x108) //Switch DMA rx packet count
++#define SDM_RBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10C) //Switch DMA rx byte count
++#define SDM_CS_ERR (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x110) //Switch DMA rx checksum error count
++
++#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
++ defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
++
++/* Old FE with New PDMA */
++#define PDMA_RELATED 0x0800
++/* 1. PDMA */
++#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x000)
++#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x004)
++#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x008)
++#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x00C)
++
++#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x010)
++#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x014)
++#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x018)
++#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x01C)
++
++#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x020)
++#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x024)
++#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x028)
++#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x02C)
++
++#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x030)
++#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x034)
++#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x038)
++#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x03C)
++
++#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x100)
++#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x104)
++#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x108)
++#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x10C)
++
++#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x110)
++#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x114)
++#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x118)
++#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x11C)
++
++#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x200)
++#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x204)
++#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x208)
++#define PDMA_RST_CFG (PDMA_RST_IDX)
++#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x20C)
++#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x210)
++#define INT_STATUS (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x220)
++#define FE_INT_STATUS (INT_STATUS)
++#define INT_MASK (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x228)
++#define FE_INT_ENABLE (INT_MASK)
++#define SCH_Q01_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
++#define SCH_Q23_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x284)
++
++#define FE_GLO_CFG RALINK_FRAME_ENGINE_BASE + 0x00
++#define FE_RST_GL RALINK_FRAME_ENGINE_BASE + 0x04
++#define FE_INT_STATUS2 RALINK_FRAME_ENGINE_BASE + 0x08
++#define FE_INT_ENABLE2 RALINK_FRAME_ENGINE_BASE + 0x0c
++//#define FC_DROP_STA RALINK_FRAME_ENGINE_BASE + 0x18
++#define FOE_TS_T RALINK_FRAME_ENGINE_BASE + 0x10
++
++#if defined (CONFIG_RALINK_MT7620)
++#define GDMA1_RELATED 0x0600
++#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
++#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
++#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
++#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
++#elif defined (CONFIG_RALINK_MT7621)
++#define GDMA1_RELATED 0x0500
++#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
++#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
++#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
++#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
++
++#define GDMA2_RELATED 0x1500
++#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
++#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
++#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
++#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
++#else
++#define GDMA1_RELATED 0x0020
++#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
++#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
++#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
++#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
++#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x10)
++
++#define GDMA2_RELATED 0x0060
++#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
++#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
++#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
++#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
++#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x10)
++#endif
++
++#if defined (CONFIG_RALINK_MT7620)
++#define PSE_RELATED 0x0500
++#define PSE_FQFC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
++#define PSE_IQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
++#define PSE_QUE_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
++#else
++#define PSE_RELATED 0x0040
++#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
++#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
++#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
++#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x0C)
++#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x10)
++#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x14)
++#define GDMA2_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x18)
++#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x1C)
++#endif
++
++
++#if defined (CONFIG_RALINK_MT7620)
++#define CDMA_RELATED 0x0400
++#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
++#define SMACCR0 (RALINK_ETH_SW_BASE + 0x3FE4)
++#define SMACCR1 (RALINK_ETH_SW_BASE + 0x3FE8)
++#define CKGCR (RALINK_ETH_SW_BASE + 0x3FF0)
++#elif defined (CONFIG_RALINK_MT7621)
++#define CDMA_RELATED 0x0400
++#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) //fake definition
++#define CDMP_IG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
++#define CDMP_EG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
++#else
++#define CDMA_RELATED 0x0080
++#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
++#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
++#define SMACCR0 (RALINK_ETH_SW_BASE + 0x30E4)
++#define SMACCR1 (RALINK_ETH_SW_BASE + 0x30E8)
++#define CKGCR (RALINK_ETH_SW_BASE + 0x30F0)
++#endif
++
++#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x100)
++
++
++#if defined (CONFIG_RALINK_MT7621)
++/*kurtis: add QDMA define*/
++
++#define CLK_CFG_0 (RALINK_SYSCTL_BASE + 0x2C)
++#define PAD_RGMII2_MDIO_CFG (RALINK_SYSCTL_BASE + 0x58)
++
++#define QDMA_RELATED 0x1800
++#define QTX_CFG_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x000)
++#define QTX_SCH_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x004)
++#define QTX_HEAD_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x008)
++#define QTX_TAIL_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x00C)
++#define QTX_CFG_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x010)
++#define QTX_SCH_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x014)
++#define QTX_HEAD_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x018)
++#define QTX_TAIL_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x01C)
++#define QTX_CFG_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x020)
++#define QTX_SCH_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x024)
++#define QTX_HEAD_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x028)
++#define QTX_TAIL_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x02C)
++#define QTX_CFG_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x030)
++#define QTX_SCH_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x034)
++#define QTX_HEAD_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x038)
++#define QTX_TAIL_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x03C)
++#define QTX_CFG_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x040)
++#define QTX_SCH_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x044)
++#define QTX_HEAD_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x048)
++#define QTX_TAIL_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x04C)
++#define QTX_CFG_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x050)
++#define QTX_SCH_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x054)
++#define QTX_HEAD_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x058)
++#define QTX_TAIL_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x05C)
++#define QTX_CFG_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x060)
++#define QTX_SCH_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x064)
++#define QTX_HEAD_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x068)
++#define QTX_TAIL_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x06C)
++#define QTX_CFG_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x070)
++#define QTX_SCH_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x074)
++#define QTX_HEAD_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x078)
++#define QTX_TAIL_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x07C)
++#define QTX_CFG_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x080)
++#define QTX_SCH_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x084)
++#define QTX_HEAD_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x088)
++#define QTX_TAIL_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x08C)
++#define QTX_CFG_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x090)
++#define QTX_SCH_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x094)
++#define QTX_HEAD_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x098)
++#define QTX_TAIL_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x09C)
++#define QTX_CFG_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A0)
++#define QTX_SCH_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A4)
++#define QTX_HEAD_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A8)
++#define QTX_TAIL_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0AC)
++#define QTX_CFG_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B0)
++#define QTX_SCH_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B4)
++#define QTX_HEAD_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B8)
++#define QTX_TAIL_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0BC)
++#define QTX_CFG_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C0)
++#define QTX_SCH_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C4)
++#define QTX_HEAD_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C8)
++#define QTX_TAIL_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0CC)
++#define QTX_CFG_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D0)
++#define QTX_SCH_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D4)
++#define QTX_HEAD_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D8)
++#define QTX_TAIL_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0DC)
++#define QTX_CFG_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E0)
++#define QTX_SCH_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E4)
++#define QTX_HEAD_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E8)
++#define QTX_TAIL_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0EC)
++#define QTX_CFG_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F0)
++#define QTX_SCH_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F4)
++#define QTX_HEAD_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F8)
++#define QTX_TAIL_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0FC)
++#define QRX_BASE_PTR_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x100)
++#define QRX_MAX_CNT_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x104)
++#define QRX_CRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x108)
++#define QRX_DRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x10C)
++#define QRX_BASE_PTR_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x110)
++#define QRX_MAX_CNT_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x114)
++#define QRX_CRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x118)
++#define QRX_DRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x11C)
++#define QDMA_INFO (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x200)
++#define QDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x204)
++#define QDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x208)
++#define QDMA_RST_CFG (QDMA_RST_IDX)
++#define QDMA_DELAY_INT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x20C)
++#define QDMA_FC_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x210)
++#define QDMA_TX_SCH (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x214)
++#define QDMA_INT_STS (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x218)
++#define QFE_INT_STATUS (QDMA_INT_STS)
++#define QDMA_INT_MASK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x21C)
++#define QFE_INT_ENABLE (QDMA_INT_MASK)
++#define QDMA_TRTCM (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x220)
++#define QDMA_DATA0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x224)
++#define QDMA_DATA1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x228)
++#define QDMA_RED_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x22C)
++#define QDMA_TEST (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x230)
++#define QDMA_DMA (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x234)
++#define QDMA_BMU (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x238)
++#define QDMA_HRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x240)
++#define QDMA_HRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x244)
++#define QDMA_SRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x248)
++#define QDMA_SRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x24C)
++#define QTX_CTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x300)
++#define QTX_DTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x304)
++#define QTX_FWD_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x308)
++#define QTX_CRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x310)
++#define QTX_DRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x314)
++#define QTX_RLS_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x318)
++#define QDMA_FQ_HEAD (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x320)
++#define QDMA_FQ_TAIL (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x324)
++#define QDMA_FQ_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x328)
++#define QDMA_FQ_BLEN (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x32C)
++#define QTX_Q0MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x350)
++#define QTX_Q1MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x354)
++#define QTX_Q2MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x358)
++#define QTX_Q3MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x35C)
++#define QTX_Q0MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x360)
++#define QTX_Q1MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x364)
++#define QTX_Q2MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x368)
++#define QTX_Q3MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x36C)
++
++
++#endif/*MT7621 QDMA*/
++
++#else
++
++/* 1. Frame Engine Global Registers */
++#define MDIO_ACCESS (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x00)
++#define MDIO_CFG (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x04)
++#define FE_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x08)
++#define FE_RST_GL (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x0C)
++#define FE_INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x10)
++#define FE_INT_ENABLE (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x14)
++#define MDIO_CFG2 (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x18) //Original:FC_DROP_STA
++#define FOC_TS_T (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x1C)
++
++
++/* 2. GDMA Registers */
++#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x00)
++#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x04)
++#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x08)
++#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x0C)
++#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x10)
++
++#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x00)
++#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x04)
++#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x08)
++#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x0C)
++#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x10)
++
++/* 3. PSE */
++#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x00)
++#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x04)
++#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x08)
++#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x0C)
++#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x1f0)
++
++/* 4. CDMA */
++#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x00)
++#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x04)
++/* skip ppoe sid and vlan id definition */
++
++
++/* 5. PDMA */
++#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00)
++#define PDMA_RST_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x04)
++#define PDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x08)
++
++#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x0C)
++
++#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10)
++#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x14)
++#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x18)
++#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x1C)
++
++#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20)
++#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x24)
++#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x28)
++#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x2C)
++
++#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40)
++#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44)
++#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48)
++#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C)
++
++#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x50)
++#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x54)
++#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x58)
++#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x5C)
++
++#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x30)
++#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x34)
++#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x38)
++#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x3C)
++
++#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40)
++#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44)
++#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48)
++#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C)
++
++#endif
++
++#define DELAY_INT_INIT 0x84048404
++#define FE_INT_DLY_INIT (TX_DLY_INT | RX_DLY_INT)
++
++
++#if !defined (CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
++
++/* 6. Counter and Meter Table */
++#define PPE_AC_BCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x000) /* PPE Accounting Group 0 Byte Cnt */
++#define PPE_AC_PCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x004) /* PPE Accounting Group 0 Packet Cnt */
++/* 0 ~ 63 */
++
++#define PPE_MTR_CNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x200) /* 0 ~ 63 */
++/* skip... */
++#define PPE_MTR_CNT63 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x2FC)
++
++#define GDMA_TX_GBCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x300) /* Transmit good byte cnt for GEport */
++#define GDMA_TX_GPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x304) /* Transmit good pkt cnt for GEport */
++#define GDMA_TX_SKIPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x308) /* Transmit skip cnt for GEport */
++#define GDMA_TX_COLCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x30C) /* Transmit collision cnt for GEport */
++
++/* update these address mapping to fit data sheet v0.26, by bobtseng, 2007.6.14 */
++#define GDMA_RX_GBCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x320)
++#define GDMA_RX_GPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x324)
++#define GDMA_RX_OERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x328)
++#define GDMA_RX_FERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x32C)
++#define GDMA_RX_SERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x330)
++#define GDMA_RX_LERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x334)
++#define GDMA_RX_CERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x338)
++#define GDMA_RX_FCCNT1 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x33C)
++
++#endif
++
++
++/* Per Port Packet Counts in RT3052, added by bobtseng 2009.4.17. */
++#define PORT0_PKCOUNT (0xb01100e8)
++#define PORT1_PKCOUNT (0xb01100ec)
++#define PORT2_PKCOUNT (0xb01100f0)
++#define PORT3_PKCOUNT (0xb01100f4)
++#define PORT4_PKCOUNT (0xb01100f8)
++#define PORT5_PKCOUNT (0xb01100fc)
++
++
++// PHYS_TO_K1
++#define PHYS_TO_K1(physaddr) KSEG1ADDR(physaddr)
++
++
++#define sysRegRead(phys) \
++ (*(volatile unsigned int *)PHYS_TO_K1(phys))
++
++#define sysRegWrite(phys, val) \
++ ((*(volatile unsigned int *)PHYS_TO_K1(phys)) = (val))
++
++#define u_long unsigned long
++#define u32 unsigned int
++#define u16 unsigned short
++
++
++/* ====================================== */
++#define GDM1_DISPAD BIT(18)
++#define GDM1_DISCRC BIT(17)
++
++//GDMA1 uni-cast frames destination port
++#define GDM1_ICS_EN (0x1 << 22)
++#define GDM1_TCS_EN (0x1 << 21)
++#define GDM1_UCS_EN (0x1 << 20)
++#define GDM1_JMB_EN (0x1 << 19)
++#define GDM1_STRPCRC (0x1 << 16)
++#define GDM1_UFRC_P_CPU (0 << 12)
++#if defined (CONFIG_RALINK_MT7621)
++#define GDM1_UFRC_P_PPE (4 << 12)
++#else
++#define GDM1_UFRC_P_PPE (6 << 12)
++#endif
++
++//GDMA1 broad-cast MAC address frames
++#define GDM1_BFRC_P_CPU (0 << 8)
++#if defined (CONFIG_RALINK_MT7621)
++#define GDM1_BFRC_P_PPE (4 << 8)
++#else
++#define GDM1_BFRC_P_PPE (6 << 8)
++#endif
++
++//GDMA1 multi-cast MAC address frames
++#define GDM1_MFRC_P_CPU (0 << 4)
++#if defined (CONFIG_RALINK_MT7621)
++#define GDM1_MFRC_P_PPE (4 << 4)
++#else
++#define GDM1_MFRC_P_PPE (6 << 4)
++#endif
++
++//GDMA1 other MAC address frames destination port
++#define GDM1_OFRC_P_CPU (0 << 0)
++#if defined (CONFIG_RALINK_MT7621)
++#define GDM1_OFRC_P_PPE (4 << 0)
++#else
++#define GDM1_OFRC_P_PPE (6 << 0)
++#endif
++
++#if defined (CONFIG_RALINK_RT6856) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
++/* checksum generator registers are removed */
++#define ICS_GEN_EN (0 << 2)
++#define UCS_GEN_EN (0 << 1)
++#define TCS_GEN_EN (0 << 0)
++#else
++#define ICS_GEN_EN (1 << 2)
++#define UCS_GEN_EN (1 << 1)
++#define TCS_GEN_EN (1 << 0)
++#endif
++
++// MDIO_CFG bit
++#define MDIO_CFG_GP1_FC_TX (1 << 11)
++#define MDIO_CFG_GP1_FC_RX (1 << 10)
++
++/* ====================================== */
++/* ====================================== */
++#define GP1_LNK_DWN BIT(9)
++#define GP1_AN_FAIL BIT(8)
++/* ====================================== */
++/* ====================================== */
++#define PSE_RESET BIT(0)
++/* ====================================== */
++#define PST_DRX_IDX1 BIT(17)
++#define PST_DRX_IDX0 BIT(16)
++#define PST_DTX_IDX3 BIT(3)
++#define PST_DTX_IDX2 BIT(2)
++#define PST_DTX_IDX1 BIT(1)
++#define PST_DTX_IDX0 BIT(0)
++
++#define RX_2B_OFFSET BIT(31)
++#define DESC_32B_EN BIT(8)
++#define TX_WB_DDONE BIT(6)
++#define RX_DMA_BUSY BIT(3)
++#define TX_DMA_BUSY BIT(1)
++#define RX_DMA_EN BIT(2)
++#define TX_DMA_EN BIT(0)
++
++#define PDMA_BT_SIZE_4DWORDS (0<<4)
++#define PDMA_BT_SIZE_8DWORDS (1<<4)
++#define PDMA_BT_SIZE_16DWORDS (2<<4)
++#define PDMA_BT_SIZE_32DWORDS (3<<4)
++
++/* Register bits.
++ */
++
++#define MACCFG_RXEN (1<<2)
++#define MACCFG_TXEN (1<<3)
++#define MACCFG_PROMISC (1<<18)
++#define MACCFG_RXMCAST (1<<19)
++#define MACCFG_FDUPLEX (1<<20)
++#define MACCFG_PORTSEL (1<<27)
++#define MACCFG_HBEATDIS (1<<28)
++
++
++#define DMACTL_SR (1<<1) /* Start/Stop Receive */
++#define DMACTL_ST (1<<13) /* Start/Stop Transmission Command */
++
++#define DMACFG_SWR (1<<0) /* Software Reset */
++#define DMACFG_BURST32 (32<<8)
++
++#define DMASTAT_TS 0x00700000 /* Transmit Process State */
++#define DMASTAT_RS 0x000e0000 /* Receive Process State */
++
++#define MACCFG_INIT 0 //(MACCFG_FDUPLEX) // | MACCFG_PORTSEL)
++
++
++
++/* Descriptor bits.
++ */
++#define R_OWN 0x80000000 /* Own Bit */
++#define RD_RER 0x02000000 /* Receive End Of Ring */
++#define RD_LS 0x00000100 /* Last Descriptor */
++#define RD_ES 0x00008000 /* Error Summary */
++#define RD_CHAIN 0x01000000 /* Chained */
++
++/* Word 0 */
++#define T_OWN 0x80000000 /* Own Bit */
++#define TD_ES 0x00008000 /* Error Summary */
++
++/* Word 1 */
++#define TD_LS 0x40000000 /* Last Segment */
++#define TD_FS 0x20000000 /* First Segment */
++#define TD_TER 0x08000000 /* Transmit End Of Ring */
++#define TD_CHAIN 0x01000000 /* Chained */
++
++
++#define TD_SET 0x08000000 /* Setup Packet */
++
++
++#define POLL_DEMAND 1
++
++#define RSTCTL (0x34)
++#define RSTCTL_RSTENET1 (1<<19)
++#define RSTCTL_RSTENET2 (1<<20)
++
++#define INIT_VALUE_OF_RT2883_PSE_FQ_CFG 0xff908000
++#define INIT_VALUE_OF_PSE_FQFC_CFG 0x80504000
++#define INIT_VALUE_OF_FORCE_100_FD 0x1001BC01
++#define INIT_VALUE_OF_FORCE_1000_FD 0x1F01DC01
++
++// Define Whole FE Reset Register
++#define RSTCTRL (RALINK_SYSCTL_BASE + 0x34)
++
++/*=========================================
++ PDMA RX Descriptor Format define
++=========================================*/
++
++//-------------------------------------------------
++typedef struct _PDMA_RXD_INFO1_ PDMA_RXD_INFO1_T;
++
++struct _PDMA_RXD_INFO1_
++{
++ unsigned int PDP0;
++};
++//-------------------------------------------------
++typedef struct _PDMA_RXD_INFO2_ PDMA_RXD_INFO2_T;
++
++struct _PDMA_RXD_INFO2_
++{
++ unsigned int PLEN1 : 14;
++ unsigned int LS1 : 1;
++ unsigned int TAG : 1;
++ unsigned int PLEN0 : 14;
++ unsigned int LS0 : 1;
++ unsigned int DDONE_bit : 1;
++};
++//-------------------------------------------------
++typedef struct _PDMA_RXD_INFO3_ PDMA_RXD_INFO3_T;
++
++struct _PDMA_RXD_INFO3_
++{
++ unsigned int VID:16;
++ unsigned int TPID:16;
++};
++//-------------------------------------------------
++typedef struct _PDMA_RXD_INFO4_ PDMA_RXD_INFO4_T;
++
++struct _PDMA_RXD_INFO4_
++{
++#if defined (CONFIG_RALINK_MT7620)
++ unsigned int FOE_Entry : 14;
++ unsigned int CRSN : 5;
++ unsigned int SPORT : 3;
++ unsigned int L4F : 1;
++ unsigned int L4VLD : 1;
++ unsigned int TACK : 1;
++ unsigned int IP4F : 1;
++ unsigned int IP4 : 1;
++ unsigned int IP6 : 1;
++ unsigned int UN_USE1 : 4;
++#elif defined (CONFIG_RALINK_MT7621)
++ unsigned int FOE_Entry : 14;
++ unsigned int CRSN : 5;
++ unsigned int SP : 4;
++ unsigned int L4F : 1;
++ unsigned int L4VLD : 1;
++ unsigned int TACK : 1;
++ unsigned int IP4F : 1;
++ unsigned int IP4 : 1;
++ unsigned int IP6 : 1;
++ unsigned int UN_USE1 : 3;
++#else
++ unsigned int FOE_Entry : 14;
++ unsigned int FVLD : 1;
++ unsigned int UN_USE1 : 1;
++ unsigned int AI : 8;
++ unsigned int SP : 3;
++ unsigned int AIS : 1;
++ unsigned int L4F : 1;
++ unsigned int IPF : 1;
++ unsigned int L4FVLD_bit : 1;
++ unsigned int IPFVLD_bit : 1;
++#endif
++};
++
++
++struct PDMA_rxdesc {
++ PDMA_RXD_INFO1_T rxd_info1;
++ PDMA_RXD_INFO2_T rxd_info2;
++ PDMA_RXD_INFO3_T rxd_info3;
++ PDMA_RXD_INFO4_T rxd_info4;
++#ifdef CONFIG_32B_DESC
++ unsigned int rxd_info5;
++ unsigned int rxd_info6;
++ unsigned int rxd_info7;
++ unsigned int rxd_info8;
++#endif
++};
++
++/*=========================================
++ PDMA TX Descriptor Format define
++=========================================*/
++//-------------------------------------------------
++typedef struct _PDMA_TXD_INFO1_ PDMA_TXD_INFO1_T;
++
++struct _PDMA_TXD_INFO1_
++{
++ unsigned int SDP0;
++};
++//-------------------------------------------------
++typedef struct _PDMA_TXD_INFO2_ PDMA_TXD_INFO2_T;
++
++struct _PDMA_TXD_INFO2_
++{
++ unsigned int SDL1 : 14;
++ unsigned int LS1_bit : 1;
++ unsigned int BURST_bit : 1;
++ unsigned int SDL0 : 14;
++ unsigned int LS0_bit : 1;
++ unsigned int DDONE_bit : 1;
++};
++//-------------------------------------------------
++typedef struct _PDMA_TXD_INFO3_ PDMA_TXD_INFO3_T;
++
++struct _PDMA_TXD_INFO3_
++{
++ unsigned int SDP1;
++};
++//-------------------------------------------------
++typedef struct _PDMA_TXD_INFO4_ PDMA_TXD_INFO4_T;
++
++struct _PDMA_TXD_INFO4_
++{
++#if defined (CONFIG_RALINK_MT7620)
++ unsigned int VPRI_VIDX : 8;
++ unsigned int SIDX : 4;
++ unsigned int INSP : 1;
++ unsigned int RESV : 2;
++ unsigned int UDF : 5;
++ unsigned int FP_BMAP : 8;
++ unsigned int TSO : 1;
++ unsigned int TUI_CO : 3;
++#elif defined (CONFIG_RALINK_MT7621)
++ unsigned int VLAN_TAG :17; // INSV(1)+VPRI(3)+CFI(1)+VID(12)
++ unsigned int RESV : 2;
++ unsigned int UDF : 6;
++ unsigned int FPORT : 3;
++ unsigned int TSO : 1;
++ unsigned int TUI_CO : 3;
++#else
++ unsigned int VPRI_VIDX : 8;
++ unsigned int SIDX : 4;
++ unsigned int INSP : 1;
++ unsigned int RESV : 1;
++ unsigned int UN_USE3 : 2;
++ unsigned int QN : 3;
++ unsigned int UN_USE2 : 1;
++ unsigned int UDF : 4;
++ unsigned int PN : 3;
++ unsigned int UN_USE1 : 1;
++ unsigned int TSO : 1;
++ unsigned int TUI_CO : 3;
++#endif
++};
++
++
++struct PDMA_txdesc {
++ PDMA_TXD_INFO1_T txd_info1;
++ PDMA_TXD_INFO2_T txd_info2;
++ PDMA_TXD_INFO3_T txd_info3;
++ PDMA_TXD_INFO4_T txd_info4;
++#ifdef CONFIG_32B_DESC
++ unsigned int txd_info5;
++ unsigned int txd_info6;
++ unsigned int txd_info7;
++ unsigned int txd_info8;
++#endif
++};
++
++
++#if defined (CONFIG_RALINK_MT7621)
++/*=========================================
++ QDMA TX Descriptor Format define
++=========================================*/
++//-------------------------------------------------
++typedef struct _QDMA_TXD_INFO1_ QDMA_TXD_INFO1_T;
++
++struct _QDMA_TXD_INFO1_
++{
++ unsigned int SDP;
++};
++//-------------------------------------------------
++typedef struct _QDMA_TXD_INFO2_ QDMA_TXD_INFO2_T;
++
++struct _QDMA_TXD_INFO2_
++{
++ unsigned int NDP;
++};
++//-------------------------------------------------
++typedef struct _QDMA_TXD_INFO3_ QDMA_TXD_INFO3_T;
++
++struct _QDMA_TXD_INFO3_
++{
++ unsigned int QID : 4;
++ unsigned int RESV : 10;
++ unsigned int SWC_bit : 1;
++ unsigned int BURST_bit : 1;
++ unsigned int SDL : 14;
++ unsigned int LS_bit : 1;
++ unsigned int OWN_bit : 1;
++};
++//-------------------------------------------------
++typedef struct _QDMA_TXD_INFO4_ QDMA_TXD_INFO4_T;
++
++struct _QDMA_TXD_INFO4_
++{
++ unsigned int VLAN_TAG :17; // INSV(1)+VPRI(3)+CFI(1)+VID(12)
++ unsigned int RESV : 2;
++ unsigned int UDF : 6;
++ unsigned int FPORT : 3;
++ unsigned int TSO : 1;
++ unsigned int TUI_CO : 3;
++};
++
++
++struct QDMA_txdesc {
++ QDMA_TXD_INFO1_T txd_info1;
++ QDMA_TXD_INFO2_T txd_info2;
++ QDMA_TXD_INFO3_T txd_info3;
++ QDMA_TXD_INFO4_T txd_info4;
++#ifdef CONFIG_32B_DESC
++ unsigned int txd_info5;
++ unsigned int txd_info6;
++ unsigned int txd_info7;
++ unsigned int txd_info8;
++#endif
++};
++#endif
++
++#define phys_to_bus(a) (a & 0x1FFFFFFF)
++
++#define PHY_Enable_Auto_Nego 0x1000
++#define PHY_Restart_Auto_Nego 0x0200
++
++/* PHY_STAT_REG = 1; */
++#define PHY_Auto_Neco_Comp 0x0020
++#define PHY_Link_Status 0x0004
++
++/* PHY_AUTO_NEGO_REG = 4; */
++#define PHY_Cap_10_Half 0x0020
++#define PHY_Cap_10_Full 0x0040
++#define PHY_Cap_100_Half 0x0080
++#define PHY_Cap_100_Full 0x0100
++
++/* proc definition */
++
++#if !defined (CONFIG_RALINK_RT6855) && !defined(CONFIG_RALINK_RT6855A) && \
++ !defined (CONFIG_RALINK_MT7620) && !defined (CONFIG_RALINK_MT7621)
++#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x4c)
++#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x50)
++#define PPE_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x54)
++#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x58)
++#endif
++
++#define PROCREG_CONTROL_FILE "/var/run/procreg_control"
++#if defined (CONFIG_RALINK_RT2880)
++#define PROCREG_DIR "rt2880"
++#elif defined (CONFIG_RALINK_RT3052)
++#define PROCREG_DIR "rt3052"
++#elif defined (CONFIG_RALINK_RT3352)
++#define PROCREG_DIR "rt3352"
++#elif defined (CONFIG_RALINK_RT5350)
++#define PROCREG_DIR "rt5350"
++#elif defined (CONFIG_RALINK_RT2883)
++#define PROCREG_DIR "rt2883"
++#elif defined (CONFIG_RALINK_RT3883)
++#define PROCREG_DIR "rt3883"
++#elif defined (CONFIG_RALINK_RT6855)
++#define PROCREG_DIR "rt6855"
++#elif defined (CONFIG_RALINK_MT7620)
++#define PROCREG_DIR "mt7620"
++#elif defined (CONFIG_RALINK_MT7621)
++#define PROCREG_DIR "mt7621"
++#elif defined (CONFIG_RALINK_MT7628)
++#define PROCREG_DIR "mt7628"
++#elif defined (CONFIG_RALINK_RT6855A)
++#define PROCREG_DIR "rt6855a"
++#else
++#define PROCREG_DIR "rt2880"
++#endif
++#define PROCREG_SKBFREE "skb_free"
++#define PROCREG_TXRING "tx_ring"
++#define PROCREG_RXRING "rx_ring"
++#define PROCREG_NUM_OF_TXD "num_of_txd"
++#define PROCREG_TSO_LEN "tso_len"
++#define PROCREG_LRO_STATS "lro_stats"
++#define PROCREG_GMAC "gmac"
++#define PROCREG_GMAC2 "gmac2"
++#define PROCREG_CP0 "cp0"
++#define PROCREG_RAQOS "qos"
++#define PROCREG_READ_VAL "regread_value"
++#define PROCREG_WRITE_VAL "regwrite_value"
++#define PROCREG_ADDR "reg_addr"
++#define PROCREG_CTL "procreg_control"
++#define PROCREG_RXDONE_INTR "rxdone_intr_count"
++#define PROCREG_ESW_INTR "esw_intr_count"
++#define PROCREG_ESW_CNT "esw_cnt"
++#define PROCREG_SNMP "snmp"
++#if defined (TASKLET_WORKQUEUE_SW)
++#define PROCREG_SCHE "schedule"
++#endif
++#define PROCREG_QDMA "qdma"
++
++struct rt2880_reg_op_data {
++ char name[64];
++ unsigned int reg_addr;
++ unsigned int op;
++ unsigned int reg_value;
++};
++
++#ifdef CONFIG_RAETH_LRO
++struct lro_counters {
++ u32 lro_aggregated;
++ u32 lro_flushed;
++ u32 lro_no_desc;
++};
++
++struct lro_para_struct {
++ unsigned int lan_ip1;
++};
++
++#endif // CONFIG_RAETH_LRO //
++
++
++
++
++typedef struct end_device
++{
++
++ unsigned int tx_cpu_owner_idx0;
++ unsigned int rx_cpu_owner_idx0;
++ unsigned int fe_int_status;
++ unsigned int tx_full;
++
++#if !defined (CONFIG_RAETH_QDMA)
++ unsigned int phy_tx_ring0;
++#else
++ /* QDMA Tx PTR */
++ struct sk_buff *free_skb[NUM_TX_DESC];
++ unsigned int tx_dma_ptr;
++ unsigned int tx_cpu_ptr;
++ unsigned int free_txd_num;
++ unsigned int free_txd_head;
++ unsigned int free_txd_tail;
++ struct QDMA_txdesc *txd_pool;
++ dma_addr_t phy_txd_pool;
++// unsigned int phy_txd_pool;
++ unsigned int txd_pool_info[NUM_TX_DESC];
++#endif
++
++ unsigned int phy_rx_ring0, phy_rx_ring1;
++
++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || \
++ defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || \
++ defined(CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620) || \
++ defined(CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
++ //send signal to user application to notify link status changed
++ struct work_struct kill_sig_wq;
++#endif
++
++ struct work_struct reset_task;
++#ifdef WORKQUEUE_BH
++ struct work_struct rx_wq;
++#else
++#if defined (TASKLET_WORKQUEUE_SW)
++ struct work_struct rx_wq;
++#endif
++#endif // WORKQUEUE_BH //
++
++#if defined(CONFIG_RAETH_QOS)
++ struct sk_buff * skb_free[NUM_TX_RINGS][NUM_TX_DESC];
++ unsigned int free_idx[NUM_TX_RINGS];
++#else
++ struct sk_buff* skb_free[NUM_TX_DESC];
++ unsigned int free_idx;
++#endif
++
++ struct net_device_stats stat; /* The new statistics table. */
++ spinlock_t page_lock; /* Page register locks */
++ struct PDMA_txdesc *tx_ring0;
++#if defined(CONFIG_RAETH_QOS)
++ struct PDMA_txdesc *tx_ring1;
++ struct PDMA_txdesc *tx_ring2;
++ struct PDMA_txdesc *tx_ring3;
++#endif
++ struct PDMA_rxdesc *rx_ring0;
++ struct sk_buff *netrx0_skbuf[NUM_RX_DESC];
++#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
++ struct PDMA_rxdesc *rx_ring1;
++ struct sk_buff *netrx1_skbuf[NUM_RX_DESC];
++#endif
++#ifdef CONFIG_RAETH_NAPI
++ atomic_t irq_sem;
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
++ struct napi_struct napi;
++#endif
++#endif
++#ifdef CONFIG_PSEUDO_SUPPORT
++ struct net_device *PseudoDev;
++ unsigned int isPseudo;
++#endif
++#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
++ struct mii_if_info mii_info;
++#endif
++#ifdef CONFIG_RAETH_LRO
++ struct lro_counters lro_counters;
++ struct net_lro_mgr lro_mgr;
++ struct net_lro_desc lro_arr[8];
++#endif
++#ifdef CONFIG_RAETH_HW_VLAN_RX
++ struct vlan_group *vlgrp;
++#endif
++} END_DEVICE, *pEND_DEVICE;
++
++
++#define RAETH_VERSION "v3.0"
++
++#endif
++
++#ifdef CONFIG_RAETH_QDMA
++#define DMA_GLO_CFG QDMA_GLO_CFG
++#define GDMA1_FWD_PORT 0x5555
++#define GDMA2_FWD_PORT 0x5555
++#define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0
++#define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1
++#define RAETH_FE_INT_STATUS QFE_INT_STATUS
++#define RAETH_FE_INT_ALL QFE_INT_ALL
++#define RAETH_FE_INT_ENABLE QFE_INT_ENABLE
++#define RAETH_FE_INT_DLY_INIT QFE_INT_DLY_INIT
++#define RAETH_FE_INT_SETTING RX_DONE_INT0 | RX_DONE_INT1 | RLS_DONE_INT
++#define RAETH_TX_DLY_INT RLS_DLY_INT
++#define RAETH_TX_DONE_INT0 RLS_DONE_INT
++#define RAETH_DLY_INT_CFG QDMA_DELAY_INT
++#else
++#define DMA_GLO_CFG PDMA_GLO_CFG
++#define GDMA1_FWD_PORT 0x0000
++#define GDMA2_FWD_PORT 0x0000
++#define RAETH_RX_CALC_IDX0 RX_CALC_IDX0
++#define RAETH_RX_CALC_IDX1 RX_CALC_IDX1
++#define RAETH_FE_INT_STATUS FE_INT_STATUS
++#define RAETH_FE_INT_ALL FE_INT_ALL
++#define RAETH_FE_INT_ENABLE FE_INT_ENABLE
++#define RAETH_FE_INT_DLY_INIT FE_INT_DLY_INIT
++#define RAETH_FE_INT_SETTING RX_DONE_INT0 | RX_DONE_INT1 | TX_DONE_INT0 | TX_DONE_INT1 | TX_DONE_INT2 | TX_DONE_INT3
++#define RAETH_TX_DLY_INT TX_DLY_INT
++#define RAETH_TX_DONE_INT0 TX_DONE_INT0
++#define RAETH_DLY_INT_CFG DLY_INT_CFG
++#endif
+--- /dev/null
++++ b/drivers/net/ethernet/raeth/ra_ioctl.h
+@@ -0,0 +1,92 @@
++#ifndef _RAETH_IOCTL_H
++#define _RAETH_IOCTL_H
++
++/* ioctl commands */
++#define RAETH_ESW_REG_READ 0x89F1
++#define RAETH_ESW_REG_WRITE 0x89F2
++#define RAETH_MII_READ 0x89F3
++#define RAETH_MII_WRITE 0x89F4
++#define RAETH_ESW_INGRESS_RATE 0x89F5
++#define RAETH_ESW_EGRESS_RATE 0x89F6
++#define RAETH_ESW_PHY_DUMP 0x89F7
++#define RAETH_QDMA_REG_READ 0x89F8
++#define RAETH_QDMA_REG_WRITE 0x89F9
++#define RAETH_QDMA_QUEUE_MAPPING 0x89FA
++#define RAETH_QDMA_READ_CPU_CLK 0x89FB
++
++#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
++ defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621)
++
++#define REG_ESW_WT_MAC_MFC 0x10
++#define REG_ESW_WT_MAC_ATA1 0x74
++#define REG_ESW_WT_MAC_ATA2 0x78
++#define REG_ESW_WT_MAC_ATWD 0x7C
++#define REG_ESW_WT_MAC_ATC 0x80
++
++#define REG_ESW_TABLE_TSRA1 0x84
++#define REG_ESW_TABLE_TSRA2 0x88
++#define REG_ESW_TABLE_ATRD 0x8C
++
++
++#define REG_ESW_VLAN_VTCR 0x90
++#define REG_ESW_VLAN_VAWD1 0x94
++#define REG_ESW_VLAN_VAWD2 0x98
++
++
++#define REG_ESW_VLAN_ID_BASE 0x100
++
++//#define REG_ESW_VLAN_ID_BASE 0x50
++#define REG_ESW_VLAN_MEMB_BASE 0x70
++#define REG_ESW_TABLE_SEARCH 0x24
++#define REG_ESW_TABLE_STATUS0 0x28
++#define REG_ESW_TABLE_STATUS1 0x2C
++#define REG_ESW_TABLE_STATUS2 0x30
++#define REG_ESW_WT_MAC_AD0 0x34
++#define REG_ESW_WT_MAC_AD1 0x38
++#define REG_ESW_WT_MAC_AD2 0x3C
++
++#else
++/* rt3052 embedded ethernet switch registers */
++#define REG_ESW_VLAN_ID_BASE 0x50
++#define REG_ESW_VLAN_MEMB_BASE 0x70
++#define REG_ESW_TABLE_SEARCH 0x24
++#define REG_ESW_TABLE_STATUS0 0x28
++#define REG_ESW_TABLE_STATUS1 0x2C
++#define REG_ESW_TABLE_STATUS2 0x30
++#define REG_ESW_WT_MAC_AD0 0x34
++#define REG_ESW_WT_MAC_AD1 0x38
++#define REG_ESW_WT_MAC_AD2 0x3C
++#endif
++
++
++#if defined(CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
++#define REG_ESW_MAX 0x16C
++#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
++ defined (CONFIG_RALINK_MT7620)
++#define REG_ESW_MAX 0x7FFFF
++#else //RT305x, RT3350
++#define REG_ESW_MAX 0xFC
++#endif
++#define REG_HQOS_MAX 0x3FFF
++
++
++typedef struct rt3052_esw_reg {
++ unsigned int off;
++ unsigned int val;
++} esw_reg;
++
++typedef struct ralink_mii_ioctl_data {
++ __u32 phy_id;
++ __u32 reg_num;
++ __u32 val_in;
++ __u32 val_out;
++} ra_mii_ioctl_data;
++
++typedef struct rt335x_esw_reg {
++ unsigned int on_off;
++ unsigned int port;
++ unsigned int bw;/*Mbps*/
++} esw_rate;
++
++
++#endif
+--- /dev/null
++++ b/drivers/net/ethernet/raeth/ra_mac.c
+@@ -0,0 +1,98 @@
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/types.h>
++#include <linux/fcntl.h>
++#include <linux/interrupt.h>
++#include <linux/ptrace.h>
++#include <linux/ioport.h>
++#include <linux/in.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++#include <linux/signal.h>
++#include <linux/irq.h>
++#include <linux/ctype.h>
++
++#include <asm/io.h>
++#include <asm/bitops.h>
++#include <asm/io.h>
++#include <asm/dma.h>
++
++#include <asm/rt2880/surfboardint.h> /* for cp0 reg access, added by bobtseng */
++
++#include <linux/errno.h>
++#include <linux/init.h>
++//#include <linux/mca.h>
++
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/skbuff.h>
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/proc_fs.h>
++#include <asm/uaccess.h>
++
++#if defined(CONFIG_USER_SNMPD)
++#include <linux/seq_file.h>
++#endif
++
++
++
++#include "ra2882ethreg.h"
++#include "raether.h"
++#include "ra_mac.h"
++
++extern struct net_device *dev_raether;
++
++
++void ra2880stop(END_DEVICE *ei_local)
++{
++ unsigned int regValue;
++ printk("ra2880stop()...");
++
++ regValue = sysRegRead(PDMA_GLO_CFG);
++ regValue &= ~(TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
++ sysRegWrite(PDMA_GLO_CFG, regValue);
++ printk("-> %s 0x%08x 0x%08x\n", "PDMA_GLO_CFG", PDMA_GLO_CFG, regValue);
++ printk("Done\n");
++}
++
++void ei_irq_clear(void)
++{
++ sysRegWrite(FE_INT_STATUS, 0xFFFFFFFF);
++ printk("-> %s 0x%08x 0x%08x\n", "FE_INT_STATUS", FE_INT_STATUS, 0xFFFFFFFF);
++}
++
++void rt2880_gmac_hard_reset(void)
++{
++ sysRegWrite(RSTCTRL, RALINK_FE_RST);
++ printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, RALINK_FE_RST);
++ sysRegWrite(RSTCTRL, 0);
++ printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, 0);
++}
++
++void ra2880EnableInterrupt()
++{
++ unsigned int regValue = sysRegRead(FE_INT_ENABLE);
++ sysRegWrite(FE_INT_ENABLE, regValue);
++ printk("-> %s 0x%08x 0x%08x\n", "FE_INT_ENABLE", FE_INT_ENABLE, regValue);
++}
++
++void ra2880MacAddressSet(unsigned char p[6])
++{
++ unsigned long regValue;
++
++ regValue = (p[0] << 8) | (p[1]);
++ sysRegWrite(GDMA1_MAC_ADRH, regValue);
++ printk("-> %s 0x%08x 0x%08x\n", "GDMA1_MAC_ADRH", GDMA1_MAC_ADRH, regValue);
++
++ regValue = (p[2] << 24) | (p[3] <<16) | (p[4] << 8) | p[5];
++ printk("-> %s 0x%08x 0x%08x\n", "GDMA1_MAC_ADRL", GDMA1_MAC_ADRL, regValue);
++ sysRegWrite(GDMA1_MAC_ADRL, regValue);
++
++ return;
++}
++
++
+--- /dev/null
++++ b/drivers/net/ethernet/raeth/ra_mac.h
+@@ -0,0 +1,35 @@
++#ifndef RA_MAC_H
++#define RA_MAC_H
++
++void ra2880stop(END_DEVICE *ei_local);
++void ra2880MacAddressSet(unsigned char p[6]);
++void ra2880Mac2AddressSet(unsigned char p[6]);
++void ethtool_init(struct net_device *dev);
++
++void ra2880EnableInterrupt(void);
++
++void dump_qos(void);
++void dump_reg(void);
++void dump_cp0(void);
++
++int debug_proc_init(void);
++void debug_proc_exit(void);
++
++#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
++ defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621)
++void enable_auto_negotiate(int unused);
++#else
++void enable_auto_negotiate(int ge);
++#endif
++
++void rt2880_gmac_hard_reset(void);
++
++int TsoLenUpdate(int tso_len);
++int NumOfTxdUpdate(int num_of_txd);
++
++#ifdef CONFIG_RAETH_LRO
++int LroStatsUpdate(struct net_lro_mgr *lro_mgr, bool all_flushed);
++#endif
++int getnext(const char *src, int separator, char *dest);
++int str_to_ip(unsigned int *ip, const char *str);
++#endif
+--- /dev/null
++++ b/drivers/net/ethernet/raeth/raether.c
+@@ -0,0 +1,693 @@
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/interrupt.h>
++#include <linux/init.h>
++#include <linux/skbuff.h>
++#include <linux/if_vlan.h>
++#include <linux/if_ether.h>
++#include <linux/fs.h>
++#include <asm/uaccess.h>
++#include <linux/delay.h>
++#include <linux/sched.h>
++
++#include <asm/rt2880/rt_mmap.h>
++#include "ra2882ethreg.h"
++#include "raether.h"
++#include "ra_mac.h"
++#include "ra_ioctl.h"
++
++static int rt2880_eth_recv(struct net_device* dev);
++int reg_dbg = 0;
++
++void setup_internal_gsw(void);
++
++#define MAX_RX_LENGTH 1536
++
++struct net_device *dev_raether;
++
++static int rx_dma_owner_idx;
++static int rx_dma_owner_idx0;
++static int pending_recv;
++static struct PDMA_rxdesc *rx_ring;
++static unsigned long tx_ring_full=0;
++
++#define KSEG1 0xa0000000
++#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
++#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
++
++extern int fe_dma_init(struct net_device *dev);
++extern int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no);
++extern void ei_xmit_housekeeping(unsigned long unused);
++extern inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no);
++
++static int ei_set_mac_addr(struct net_device *dev, void *p)
++{
++ struct sockaddr *addr = p;
++
++ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
++
++ if(netif_running(dev))
++ return -EBUSY;
++
++ ra2880MacAddressSet(addr->sa_data);
++ return 0;
++}
++
++
++void set_fe_dma_glo_cfg(void)
++{
++ int dma_glo_cfg=0;
++
++ dma_glo_cfg = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS);
++
++ dma_glo_cfg |= (RX_2B_OFFSET);
++
++ sysRegWrite(DMA_GLO_CFG, dma_glo_cfg);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "DMA_GLO_CFG", DMA_GLO_CFG, dma_glo_cfg);
++}
++
++int forward_config(struct net_device *dev)
++{
++ unsigned int regVal, regCsg;
++
++ regVal = sysRegRead(GDMA1_FWD_CFG);
++ regCsg = sysRegRead(CDMA_CSG_CFG);
++
++ //set unicast/multicast/broadcast frame to cpu
++ regVal &= ~0xFFFF;
++ regVal |= GDMA1_FWD_PORT;
++ regCsg &= ~0x7;
++
++ //disable ipv4 header checksum check
++ regVal &= ~GDM1_ICS_EN;
++ regCsg &= ~ICS_GEN_EN;
++
++ //disable tcp checksum check
++ regVal &= ~GDM1_TCS_EN;
++ regCsg &= ~TCS_GEN_EN;
++
++ //disable udp checksum check
++ regVal &= ~GDM1_UCS_EN;
++ regCsg &= ~UCS_GEN_EN;
++
++
++ dev->features &= ~NETIF_F_IP_CSUM; /* disable checksum TCP/UDP over IPv4 */
++
++
++ sysRegWrite(GDMA1_FWD_CFG, regVal);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "GDMA1_FWD_CFG", GDMA1_FWD_CFG, regVal);
++ sysRegWrite(CDMA_CSG_CFG, regCsg);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "CDMA_CSG_CFG", CDMA_CSG_CFG, regCsg);
++
++ regVal = 0x1;
++ sysRegWrite(FE_RST_GL, regVal);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "FE_RST_GL", FE_RST_GL, regVal);
++ sysRegWrite(FE_RST_GL, 0); // update for RSTCTL issue
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "FE_RST_GL", FE_RST_GL, 1);
++
++ regCsg = sysRegRead(CDMA_CSG_CFG);
++ printk("CDMA_CSG_CFG = %0X\n",regCsg);
++ regVal = sysRegRead(GDMA1_FWD_CFG);
++ printk("GDMA1_FWD_CFG = %0X\n",regVal);
++
++ return 1;
++}
++
++
++static int rt2880_eth_recv(struct net_device* dev)
++{
++ struct sk_buff *skb, *rx_skb;
++ unsigned int length = 0;
++ unsigned long RxProcessed;
++
++
++ int bReschedule = 0;
++ END_DEVICE* ei_local = netdev_priv(dev);
++
++
++
++ RxProcessed = 0;
++
++ rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
++
++ for ( ; ; ) {
++
++ if (RxProcessed++ > NUM_RX_MAX_PROCESS)
++ {
++ // need to reschedule rx handle
++ bReschedule = 1;
++ break;
++ }
++
++
++
++ if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.DDONE_bit == 1) {
++ rx_ring = ei_local->rx_ring0;
++ rx_dma_owner_idx = rx_dma_owner_idx0;
++ } else {
++ break;
++ }
++
++ /* skb processing */
++ length = rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0;
++ rx_skb = ei_local->netrx0_skbuf[rx_dma_owner_idx];
++ rx_skb->data = ei_local->netrx0_skbuf[rx_dma_owner_idx]->data;
++ rx_skb->len = length;
++
++ rx_skb->data += NET_IP_ALIGN;
++
++ rx_skb->tail = rx_skb->data + length;
++
++ rx_skb->dev = dev;
++ rx_skb->protocol = eth_type_trans(rx_skb,dev);
++
++ rx_skb->ip_summed = CHECKSUM_NONE;
++
++
++ /* We have to check the free memory size is big enough
++ * before pass the packet to cpu*/
++ skb = __dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN, GFP_ATOMIC);
++
++ if (unlikely(skb == NULL))
++ {
++ printk(KERN_ERR "skb not available...\n");
++ ei_local->stat.rx_dropped++;
++ bReschedule = 1;
++ break;
++ }
++
++ {
++ netif_rx(rx_skb);
++ }
++
++ {
++ ei_local->stat.rx_packets++;
++ ei_local->stat.rx_bytes += length;
++ }
++
++
++ rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0 = MAX_RX_LENGTH;
++ rx_ring[rx_dma_owner_idx].rxd_info2.LS0 = 0;
++ rx_ring[rx_dma_owner_idx].rxd_info2.DDONE_bit = 0;
++ rx_ring[rx_dma_owner_idx].rxd_info1.PDP0 = dma_map_single(NULL, skb->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
++
++ /* Move point to next RXD which wants to alloc*/
++ sysRegWrite(RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RAETH_RX_CALC_IDX0", RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
++ ei_local->netrx0_skbuf[rx_dma_owner_idx] = skb;
++
++ /* Update to Next packet point that was received.
++ */
++ rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
++ } /* for */
++
++ return bReschedule;
++}
++
++void ei_receive_workq(struct work_struct *work)
++{
++ struct net_device *dev = dev_raether;
++ END_DEVICE *ei_local = netdev_priv(dev);
++ unsigned long reg_int_mask=0;
++ int bReschedule=0;
++
++
++ if(tx_ring_full==0){
++ bReschedule = rt2880_eth_recv(dev);
++ if(bReschedule)
++ {
++ schedule_work(&ei_local->rx_wq);
++ }else{
++ reg_int_mask=sysRegRead(RAETH_FE_INT_ENABLE);
++ sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask| RX_DLY_INT);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, reg_int_mask| RX_DLY_INT);
++ }
++ }else{
++ schedule_work(&ei_local->rx_wq);
++ }
++}
++
++
++static irqreturn_t ei_interrupt(int irq, void *dev_id)
++{
++ unsigned long reg_int_val;
++ unsigned long reg_int_mask=0;
++ unsigned int recv = 0;
++ unsigned int transmit __maybe_unused = 0;
++ unsigned long flags;
++
++ struct net_device *dev = (struct net_device *) dev_id;
++ END_DEVICE *ei_local = netdev_priv(dev);
++
++ if (dev == NULL)
++ {
++ printk (KERN_ERR "net_interrupt(): irq %x for unknown device.\n", IRQ_ENET0);
++ return IRQ_NONE;
++ }
++
++
++ spin_lock_irqsave(&(ei_local->page_lock), flags);
++ reg_int_val = sysRegRead(RAETH_FE_INT_STATUS);
++
++ if((reg_int_val & RX_DLY_INT))
++ recv = 1;
++
++ if (reg_int_val & RAETH_TX_DLY_INT)
++ transmit = 1;
++
++ sysRegWrite(RAETH_FE_INT_STATUS, RAETH_FE_INT_DLY_INIT);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_STATUS", RAETH_FE_INT_STATUS, RAETH_FE_INT_DLY_INIT);
++
++ ei_xmit_housekeeping(0);
++
++ if (((recv == 1) || (pending_recv ==1)) && (tx_ring_full==0))
++ {
++ reg_int_mask = sysRegRead(RAETH_FE_INT_ENABLE);
++ sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT));
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT));
++ pending_recv=0;
++ schedule_work(&ei_local->rx_wq);
++ }
++ else if (recv == 1 && tx_ring_full==1)
++ {
++ pending_recv=1;
++ }
++ spin_unlock_irqrestore(&(ei_local->page_lock), flags);
++
++ return IRQ_HANDLED;
++}
++
++static void esw_link_status_changed(int port_no, void *dev_id)
++{
++ unsigned int reg_val;
++ mii_mgr_read(31, (0x3008 + (port_no*0x100)), ®_val);
++ if(reg_val & 0x1) {
++ printk("ESW: Link Status Changed - Port%d Link UP\n", port_no);
++ } else {
++ printk("ESW: Link Status Changed - Port%d Link Down\n", port_no);
++ }
++}
++
++
++static irqreturn_t esw_interrupt(int irq, void *dev_id)
++{
++ unsigned long flags;
++ unsigned int reg_int_val;
++ struct net_device *dev = (struct net_device *) dev_id;
++ END_DEVICE *ei_local = netdev_priv(dev);
++
++ spin_lock_irqsave(&(ei_local->page_lock), flags);
++ mii_mgr_read(31, 0x700c, ®_int_val);
++
++ if (reg_int_val & P4_LINK_CH) {
++ esw_link_status_changed(4, dev_id);
++ }
++
++ if (reg_int_val & P3_LINK_CH) {
++ esw_link_status_changed(3, dev_id);
++ }
++ if (reg_int_val & P2_LINK_CH) {
++ esw_link_status_changed(2, dev_id);
++ }
++ if (reg_int_val & P1_LINK_CH) {
++ esw_link_status_changed(1, dev_id);
++ }
++ if (reg_int_val & P0_LINK_CH) {
++ esw_link_status_changed(0, dev_id);
++ }
++
++ mii_mgr_write(31, 0x700c, 0x1f); //ack switch link change
++ spin_unlock_irqrestore(&(ei_local->page_lock), flags);
++ return IRQ_HANDLED;
++}
++
++
++
++static int ei_start_xmit_fake(struct sk_buff* skb, struct net_device *dev)
++{
++ return ei_start_xmit(skb, dev, 1);
++}
++
++static int ei_change_mtu(struct net_device *dev, int new_mtu)
++{
++ unsigned long flags;
++ END_DEVICE *ei_local = netdev_priv(dev); // get priv ei_local pointer from net_dev structure
++
++ if ( ei_local == NULL ) {
++ printk(KERN_EMERG "%s: ei_change_mtu passed a non-existent private pointer from net_dev!\n", dev->name);
++ return -ENXIO;
++ }
++
++ spin_lock_irqsave(&ei_local->page_lock, flags);
++
++ if ( (new_mtu > 4096) || (new_mtu < 64)) {
++ spin_unlock_irqrestore(&ei_local->page_lock, flags);
++ return -EINVAL;
++ }
++
++ if ( new_mtu > 1500 ) {
++ spin_unlock_irqrestore(&ei_local->page_lock, flags);
++ return -EINVAL;
++ }
++
++ dev->mtu = new_mtu;
++
++ spin_unlock_irqrestore(&ei_local->page_lock, flags);
++ return 0;
++}
++
++
++static const struct net_device_ops ei_netdev_ops = {
++ .ndo_init = rather_probe,
++ .ndo_open = ei_open,
++ .ndo_stop = ei_close,
++ .ndo_start_xmit = ei_start_xmit_fake,
++ .ndo_set_mac_address = eth_mac_addr,
++ .ndo_change_mtu = ei_change_mtu,
++ .ndo_validate_addr = eth_validate_addr,
++};
++
++void ra2880_setup_dev_fptable(struct net_device *dev)
++{
++ RAETH_PRINT(__FUNCTION__ "is called!\n");
++
++ dev->netdev_ops = &ei_netdev_ops;
++#define TX_TIMEOUT (5*HZ)
++ dev->watchdog_timeo = TX_TIMEOUT;
++
++}
++
++void fe_reset(void)
++{
++ u32 val;
++ val = sysRegRead(RSTCTRL);
++
++ val = val | RALINK_FE_RST;
++ sysRegWrite(RSTCTRL, val);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, val);
++ val = val & ~(RALINK_FE_RST);
++ sysRegWrite(RSTCTRL, val);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, val);
++}
++
++void ei_reset_task(struct work_struct *work)
++{
++ struct net_device *dev = dev_raether;
++
++ ei_close(dev);
++ ei_open(dev);
++
++ return;
++}
++
++void ei_tx_timeout(struct net_device *dev)
++{
++ END_DEVICE *ei_local = netdev_priv(dev);
++
++ schedule_work(&ei_local->reset_task);
++}
++
++int __init rather_probe(struct net_device *dev)
++{
++ END_DEVICE *ei_local = netdev_priv(dev);
++ struct sockaddr addr;
++ unsigned char mac_addr01234[5] = {0x00, 0x0C, 0x43, 0x28, 0x80};
++
++ fe_reset();
++ net_srandom(jiffies);
++ memcpy(addr.sa_data, mac_addr01234, 5);
++ addr.sa_data[5] = net_random()&0xFF;
++ ei_set_mac_addr(dev, &addr);
++ spin_lock_init(&ei_local->page_lock);
++ ether_setup(dev);
++
++ return 0;
++}
++
++
++int ei_open(struct net_device *dev)
++{
++ int i, err;
++ unsigned long flags;
++ END_DEVICE *ei_local;
++
++
++ if (!try_module_get(THIS_MODULE))
++ {
++ printk("%s: Cannot reserve module\n", __FUNCTION__);
++ return -1;
++ }
++ printk("Raeth %s (",RAETH_VERSION);
++ printk("Workqueue");
++
++ printk(")\n");
++ ei_local = netdev_priv(dev); // get device pointer from System
++ // unsigned int flags;
++
++ if (ei_local == NULL)
++ {
++ printk(KERN_EMERG "%s: ei_open passed a non-existent device!\n", dev->name);
++ return -ENXIO;
++ }
++
++ /* receiving packet buffer allocation - NUM_RX_DESC x MAX_RX_LENGTH */
++ for ( i = 0; i < NUM_RX_DESC; i++)
++ {
++ ei_local->netrx0_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN);
++ if (ei_local->netrx0_skbuf[i] == NULL ) {
++ printk("rx skbuff buffer allocation failed!");
++ } else {
++ }
++ }
++
++ spin_lock_irqsave(&(ei_local->page_lock), flags);
++ fe_dma_init(dev);
++ fe_sw_init(); //initialize fe and switch register
++ err = request_irq( dev->irq, ei_interrupt, 0, dev->name, dev); // try to fix irq in open
++ if (err)
++ return err;
++
++ if ( dev->dev_addr != NULL) {
++ ra2880MacAddressSet((void *)(dev->dev_addr));
++ } else {
++ printk("dev->dev_addr is empty !\n");
++ }
++ mii_mgr_write(31, 0x7008, 0x1f); //enable switch link change intr
++ err = request_irq(31, esw_interrupt, IRQF_DISABLED, "Ralink_ESW", dev);
++ if (err)
++ return err;
++
++ sysRegWrite(RAETH_DLY_INT_CFG, DELAY_INT_INIT);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RAETH_DLY_INT_CFG", RAETH_DLY_INT_CFG, DELAY_INT_INIT);
++ sysRegWrite(RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT);
++
++ INIT_WORK(&ei_local->reset_task, ei_reset_task);
++
++ INIT_WORK(&ei_local->rx_wq, ei_receive_workq);
++
++ netif_start_queue(dev);
++
++
++ spin_unlock_irqrestore(&(ei_local->page_lock), flags);
++
++
++ forward_config(dev);
++ return 0;
++}
++
++int ei_close(struct net_device *dev)
++{
++ int i;
++ END_DEVICE *ei_local = netdev_priv(dev); // device pointer
++ unsigned long flags;
++ spin_lock_irqsave(&(ei_local->page_lock), flags);
++
++ cancel_work_sync(&ei_local->reset_task);
++ netif_stop_queue(dev);
++ ra2880stop(ei_local);
++ msleep(10);
++
++ cancel_work_sync(&ei_local->rx_wq);
++ free_irq(dev->irq, dev);
++ free_irq(31, dev);
++ for ( i = 0; i < NUM_RX_DESC; i++)
++ {
++ if (ei_local->netrx0_skbuf[i] != NULL) {
++ dev_kfree_skb(ei_local->netrx0_skbuf[i]);
++ ei_local->netrx0_skbuf[i] = NULL;
++ }
++ }
++ if (ei_local->tx_ring0 != NULL) {
++ pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring0, ei_local->phy_tx_ring0);
++ }
++ pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring0, ei_local->phy_rx_ring0);
++
++ printk("Free TX/RX Ring Memory!\n");
++
++// fe_reset();
++ spin_unlock_irqrestore(&(ei_local->page_lock), flags);
++
++ module_put(THIS_MODULE);
++ return 0;
++}
++
++
++void setup_internal_gsw(void)
++{
++ u32 i;
++ u32 regValue;
++
++ /* reduce RGMII2 PAD driving strength */
++ *(volatile u_long *)(PAD_RGMII2_MDIO_CFG) &= ~(0x3 << 4);
++
++ //RGMII1=Normal mode
++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 14);
++
++ //GMAC1= RGMII mode
++ *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 12);
++
++ //enable MDIO to control MT7530
++ regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60));
++ regValue &= ~(0x3 << 12);
++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue;
++
++ for(i=0;i<=4;i++)
++ {
++ //turn off PHY
++ mii_mgr_read(i, 0x0 ,®Value);
++ regValue |= (0x1<<11);
++ mii_mgr_write(i, 0x0, regValue);
++ }
++ mii_mgr_write(31, 0x7000, 0x3); //reset switch
++ udelay(10);
++
++ if(sysRegRead(0xbe00000c)==0x00030101) {
++ sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2005e30b);//(GE1, Force 1000M/FD, FC ON)
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x100", RALINK_ETH_SW_BASE+0x100, 0x2005e30b);
++ mii_mgr_write(31, 0x3600, 0x5e30b);
++ } else {
++ sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2005e33b);//(GE1, Force 1000M/FD, FC ON)
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x100", RALINK_ETH_SW_BASE+0x100, 0x2005e33b);
++ mii_mgr_write(31, 0x3600, 0x5e33b);
++ }
++
++ sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x00008000);//(GE2, Link down)
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x200", RALINK_ETH_SW_BASE+0x200, 0x00008000);
++
++ //regValue = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable*/
++ mii_mgr_read(31, 0x7804 ,®Value);
++ regValue &= ~(1<<8); //Enable Port 6
++ regValue |= (1<<6); //Disable Port 5
++ regValue |= (1<<13); //Port 5 as GMAC, no Internal PHY
++
++ regValue |= (1<<16);//change HW-TRAP
++ printk("change HW-TRAP to 0x%x!!!!!!!!!!!!",regValue);
++ mii_mgr_write(31, 0x7804 ,regValue);
++ regValue = *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x10);
++ regValue = (regValue >> 6) & 0x7;
++ if(regValue >= 6) { //25Mhz Xtal
++ /* do nothing */
++ } else if(regValue >=3) { //40Mhz
++
++ mii_mgr_write(0, 13, 0x1f); // disable MT7530 core clock
++ mii_mgr_write(0, 14, 0x410);
++ mii_mgr_write(0, 13, 0x401f);
++ mii_mgr_write(0, 14, 0x0);
++
++ mii_mgr_write(0, 13, 0x1f); // disable MT7530 PLL
++ mii_mgr_write(0, 14, 0x40d);
++ mii_mgr_write(0, 13, 0x401f);
++ mii_mgr_write(0, 14, 0x2020);
++
++ mii_mgr_write(0, 13, 0x1f); // for MT7530 core clock = 500Mhz
++ mii_mgr_write(0, 14, 0x40e);
++ mii_mgr_write(0, 13, 0x401f);
++ mii_mgr_write(0, 14, 0x119);
++
++ mii_mgr_write(0, 13, 0x1f); // enable MT7530 PLL
++ mii_mgr_write(0, 14, 0x40d);
++ mii_mgr_write(0, 13, 0x401f);
++ mii_mgr_write(0, 14, 0x2820);
++
++ udelay(20); //suggest by CD
++
++ mii_mgr_write(0, 13, 0x1f); // enable MT7530 core clock
++ mii_mgr_write(0, 14, 0x410);
++ mii_mgr_write(0, 13, 0x401f);
++ }else { //20Mhz Xtal
++
++ /* TODO */
++
++ }
++ mii_mgr_write(0, 14, 0x1); /*RGMII*/
++
++#if 1
++ mii_mgr_write(31, 0x7b00, 0x102); //delay setting for 10/1000M
++ mii_mgr_write(31, 0x7b04, 0x14); //delay setting for 10/1000M
++#else
++ mii_mgr_write(31, 0x7b00, 8); // delay setting for 100M
++ mii_mgr_write(31, 0x7b04, 0x14); // for 100M
++#endif
++ /*Tx Driving*/
++ mii_mgr_write(31, 0x7a54, 0x44); //lower driving
++ mii_mgr_write(31, 0x7a5c, 0x44); //lower driving
++ mii_mgr_write(31, 0x7a64, 0x44); //lower driving
++ mii_mgr_write(31, 0x7a6c, 0x44); //lower driving
++ mii_mgr_write(31, 0x7a74, 0x44); //lower driving
++ mii_mgr_write(31, 0x7a7c, 0x44); //lower driving
++
++ for(i=0;i<=4;i++)
++ {
++ //turn on PHY
++ mii_mgr_read(i, 0x0 ,®Value);
++ regValue &= ~(0x1<<11);
++ mii_mgr_write(i, 0x0, regValue);
++ }
++
++ mii_mgr_read(31, 0x7808 ,®Value);
++ regValue |= (3<<16); //Enable INTR
++ mii_mgr_write(31, 0x7808 ,regValue);
++}
++
++int __init ra2882eth_init(void)
++{
++ int ret;
++ struct net_device *dev = alloc_etherdev(sizeof(END_DEVICE));
++ if (!dev)
++ return -ENOMEM;
++
++ strcpy(dev->name, DEV_NAME);
++ dev->irq = IRQ_ENET0;
++ dev->addr_len = 6;
++ dev->base_addr = RALINK_FRAME_ENGINE_BASE;
++
++ rather_probe(dev);
++ ra2880_setup_dev_fptable(dev);
++
++ if ( register_netdev(dev) != 0) {
++ printk(KERN_WARNING " " __FILE__ ": No ethernet port found.\n");
++ return -ENXIO;
++ }
++ ret = 0;
++
++ dev_raether = dev;
++ return ret;
++}
++
++void fe_sw_init(void)
++{
++ setup_internal_gsw();
++}
++
++
++void ra2882eth_cleanup_module(void)
++{
++}
++EXPORT_SYMBOL(set_fe_dma_glo_cfg);
++module_init(ra2882eth_init);
++module_exit(ra2882eth_cleanup_module);
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/net/ethernet/raeth/raether.h
+@@ -0,0 +1,92 @@
++#ifndef RA2882ETHEND_H
++#define RA2882ETHEND_H
++
++#ifdef DSP_VIA_NONCACHEABLE
++#define ESRAM_BASE 0xa0800000 /* 0x0080-0000 ~ 0x00807FFF */
++#else
++#define ESRAM_BASE 0x80800000 /* 0x0080-0000 ~ 0x00807FFF */
++#endif
++
++#define RX_RING_BASE ((int)(ESRAM_BASE + 0x7000))
++#define TX_RING_BASE ((int)(ESRAM_BASE + 0x7800))
++
++#if defined(CONFIG_RALINK_RT2880)
++#define NUM_TX_RINGS 1
++#else
++#define NUM_TX_RINGS 4
++#endif
++#ifdef MEMORY_OPTIMIZATION
++#ifdef CONFIG_RAETH_ROUTER
++#define NUM_RX_DESC 128
++#define NUM_TX_DESC 128
++#elif CONFIG_RT_3052_ESW
++#define NUM_RX_DESC 64
++#define NUM_TX_DESC 64
++#else
++#define NUM_RX_DESC 128
++#define NUM_TX_DESC 128
++#endif
++//#define NUM_RX_MAX_PROCESS 32
++#define NUM_RX_MAX_PROCESS 64
++#else
++#if defined (CONFIG_RAETH_ROUTER)
++#define NUM_RX_DESC 256
++#define NUM_TX_DESC 256
++#elif defined (CONFIG_RT_3052_ESW)
++#define NUM_RX_DESC 256
++#define NUM_TX_DESC 256
++#else
++#define NUM_RX_DESC 256
++#define NUM_TX_DESC 256
++#endif
++#if defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_MT7620)
++#define NUM_RX_MAX_PROCESS 2
++#else
++#define NUM_RX_MAX_PROCESS 16
++#endif
++#endif
++
++#define DEV_NAME "eth0"
++#define DEV2_NAME "eth3"
++
++#if defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7621)
++#define GMAC0_OFFSET 0xE000
++#define GMAC2_OFFSET 0xE006
++#else
++#define GMAC0_OFFSET 0x28
++#define GMAC2_OFFSET 0x22
++#endif
++
++#if defined(CONFIG_RALINK_RT6855A)
++#define IRQ_ENET0 22
++#else
++#define IRQ_ENET0 11 /* hardware interrupt #3, defined in RT2880 Soc Design Spec Rev 0.03, pp43 */
++#endif
++
++#define FE_INT_STATUS_REG (*(volatile unsigned long *)(FE_INT_STATUS))
++#define FE_INT_STATUS_CLEAN(reg) (*(volatile unsigned long *)(FE_INT_STATUS)) = reg
++
++//#define RAETH_DEBUG
++#ifdef RAETH_DEBUG
++#define RAETH_PRINT(fmt, args...) printk(KERN_INFO fmt, ## args)
++#else
++#define RAETH_PRINT(fmt, args...) { }
++#endif
++
++struct net_device_stats *ra_get_stats(struct net_device *dev);
++
++void ei_tx_timeout(struct net_device *dev);
++int rather_probe(struct net_device *dev);
++int ei_open(struct net_device *dev);
++int ei_close(struct net_device *dev);
++
++int ra2882eth_init(void);
++void ra2882eth_cleanup_module(void);
++
++void ei_xmit_housekeeping(unsigned long data);
++
++u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data);
++u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data);
++void fe_sw_init(void);
++
++#endif
+--- /dev/null
++++ b/drivers/net/ethernet/raeth/raether_pdma.c
+@@ -0,0 +1,212 @@
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/skbuff.h>
++#include <linux/if_vlan.h>
++#include <linux/if_ether.h>
++#include <linux/fs.h>
++#include <asm/uaccess.h>
++#include <linux/delay.h>
++#include <linux/sched.h>
++#include <asm/rt2880/rt_mmap.h>
++#include "ra2882ethreg.h"
++#include "raether.h"
++#include "ra_mac.h"
++
++#define MAX_RX_LENGTH 1536
++
++extern int reg_dbg;
++extern struct net_device *dev_raether;
++static unsigned long tx_ring_full=0;
++
++#define KSEG1 0xa0000000
++#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
++#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
++
++extern void set_fe_dma_glo_cfg(void);
++
++int fe_dma_init(struct net_device *dev)
++{
++
++ int i;
++ unsigned int regVal;
++ END_DEVICE* ei_local = netdev_priv(dev);
++
++ while(1)
++ {
++ regVal = sysRegRead(PDMA_GLO_CFG);
++ if((regVal & RX_DMA_BUSY))
++ {
++ printk("\n RX_DMA_BUSY !!! ");
++ continue;
++ }
++ if((regVal & TX_DMA_BUSY))
++ {
++ printk("\n TX_DMA_BUSY !!! ");
++ continue;
++ }
++ break;
++ }
++
++ for (i=0;i<NUM_TX_DESC;i++){
++ ei_local->skb_free[i]=0;
++ }
++ ei_local->free_idx =0;
++ ei_local->tx_ring0 = pci_alloc_consistent(NULL, NUM_TX_DESC * sizeof(struct PDMA_txdesc), &ei_local->phy_tx_ring0);
++ printk("\nphy_tx_ring = 0x%08x, tx_ring = 0x%p\n", ei_local->phy_tx_ring0, ei_local->tx_ring0);
++
++ for (i=0; i < NUM_TX_DESC; i++) {
++ memset(&ei_local->tx_ring0[i],0,sizeof(struct PDMA_txdesc));
++ ei_local->tx_ring0[i].txd_info2.LS0_bit = 1;
++ ei_local->tx_ring0[i].txd_info2.DDONE_bit = 1;
++
++ }
++
++ /* Initial RX Ring 0*/
++ ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
++ for (i = 0; i < NUM_RX_DESC; i++) {
++ memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
++ ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
++ ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
++ ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
++ ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
++ }
++ printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
++
++
++ regVal = sysRegRead(PDMA_GLO_CFG);
++ regVal &= 0x000000FF;
++ sysRegWrite(PDMA_GLO_CFG, regVal);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "PDMA_GLO_CFG", PDMA_GLO_CFG, regVal);
++
++ regVal=sysRegRead(PDMA_GLO_CFG);
++
++ /* Tell the adapter where the TX/RX rings are located. */
++ sysRegWrite(TX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_tx_ring0));
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_BASE_PTR0", TX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_tx_ring0));
++ sysRegWrite(TX_MAX_CNT0, cpu_to_le32((u32) NUM_TX_DESC));
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_MAX_CNT0", TX_MAX_CNT0, cpu_to_le32((u32) NUM_TX_DESC));
++ sysRegWrite(TX_CTX_IDX0, 0);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_CTX_IDX0", TX_CTX_IDX0, 0);
++ sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX0);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "PDMA_RST_CFG", PDMA_RST_CFG, PST_DTX_IDX0);
++
++ sysRegWrite(RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0));
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_BASE_PTR0", RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0));
++ sysRegWrite(RX_MAX_CNT0, cpu_to_le32((u32) NUM_RX_DESC));
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_MAX_CNT0", RX_MAX_CNT0, cpu_to_le32((u32) NUM_RX_DESC));
++ sysRegWrite(RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_CALC_IDX0", RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
++ sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX0);
++ if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "PDMA_RST_CFG", PDMA_RST_CFG, PST_DRX_IDX0);
++
++ set_fe_dma_glo_cfg();
++
++ return 1;
++}
++
++inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no)
++{
++ unsigned int length=skb->len;
++ END_DEVICE* ei_local = netdev_priv(dev);
++ unsigned long tx_cpu_owner_idx0 = sysRegRead(TX_CTX_IDX0);
++
++ while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0)
++ {
++ ei_local->stat.tx_errors++;
++ }
++
++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0 = virt_to_phys(skb->data);
++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0 = length;
++ if (gmac_no == 1) {
++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 1;
++ }else {
++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 2;
++ }
++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit = 0;
++ tx_cpu_owner_idx0 = (tx_cpu_owner_idx0+1) % NUM_TX_DESC;
++ while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0)
++ {
++ ei_local->stat.tx_errors++;
++ }
++ sysRegWrite(TX_CTX_IDX0, cpu_to_le32((u32)tx_cpu_owner_idx0));
++
++ {
++ ei_local->stat.tx_packets++;
++ ei_local->stat.tx_bytes += length;
++ }
++
++ return length;
++}
++
++int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no)
++{
++ END_DEVICE *ei_local = netdev_priv(dev);
++ unsigned long flags;
++ unsigned long tx_cpu_owner_idx;
++ unsigned int tx_cpu_owner_idx_next;
++ unsigned int num_of_txd;
++ unsigned int tx_cpu_owner_idx_next2;
++
++ dev->trans_start = jiffies; /* save the timestamp */
++ spin_lock_irqsave(&ei_local->page_lock, flags);
++ dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
++
++ tx_cpu_owner_idx = sysRegRead(TX_CTX_IDX0);
++ num_of_txd = 1;
++ tx_cpu_owner_idx_next = (tx_cpu_owner_idx + num_of_txd) % NUM_TX_DESC;
++
++ if(((ei_local->skb_free[tx_cpu_owner_idx]) ==0) && (ei_local->skb_free[tx_cpu_owner_idx_next]==0)){
++ rt2880_eth_send(dev, skb, gmac_no);
++
++ tx_cpu_owner_idx_next2 = (tx_cpu_owner_idx_next + 1) % NUM_TX_DESC;
++
++ if(ei_local->skb_free[tx_cpu_owner_idx_next2]!=0){
++ }
++ }else {
++ ei_local->stat.tx_dropped++;
++ kfree_skb(skb);
++ spin_unlock_irqrestore(&ei_local->page_lock, flags);
++ return 0;
++ }
++
++ ei_local->skb_free[tx_cpu_owner_idx] = skb;
++ spin_unlock_irqrestore(&ei_local->page_lock, flags);
++ return 0;
++}
++
++void ei_xmit_housekeeping(unsigned long unused)
++{
++ struct net_device *dev = dev_raether;
++ END_DEVICE *ei_local = netdev_priv(dev);
++ struct PDMA_txdesc *tx_desc;
++ unsigned long skb_free_idx;
++ unsigned long tx_dtx_idx __maybe_unused;
++ unsigned long reg_int_mask=0;
++
++ tx_dtx_idx = sysRegRead(TX_DTX_IDX0);
++ tx_desc = ei_local->tx_ring0;
++ skb_free_idx = ei_local->free_idx;
++ if ((ei_local->skb_free[skb_free_idx]) != 0 && tx_desc[skb_free_idx].txd_info2.DDONE_bit==1) {
++ while(tx_desc[skb_free_idx].txd_info2.DDONE_bit==1 && (ei_local->skb_free[skb_free_idx])!=0 ){
++ dev_kfree_skb_any(ei_local->skb_free[skb_free_idx]);
++ ei_local->skb_free[skb_free_idx]=0;
++ skb_free_idx = (skb_free_idx +1) % NUM_TX_DESC;
++ }
++
++ netif_wake_queue(dev);
++ tx_ring_full=0;
++ ei_local->free_idx = skb_free_idx;
++ }
++
++ reg_int_mask=sysRegRead(FE_INT_ENABLE);
++ sysRegWrite(FE_INT_ENABLE, reg_int_mask| TX_DLY_INT);
++}
++
++EXPORT_SYMBOL(ei_start_xmit);
++EXPORT_SYMBOL(ei_xmit_housekeeping);
++EXPORT_SYMBOL(fe_dma_init);
++EXPORT_SYMBOL(rt2880_eth_send);
+--- /dev/null
++++ b/drivers/net/ethernet/raeth/raether_qdma.c
+@@ -0,0 +1,805 @@
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/skbuff.h>
++#include <linux/if_vlan.h>
++#include <linux/if_ether.h>
++#include <linux/fs.h>
++#include <asm/uaccess.h>
++#include <asm/rt2880/surfboardint.h>
++#if defined (CONFIG_RAETH_TSO)
++#include <linux/tcp.h>
++#include <net/ipv6.h>
++#include <linux/ip.h>
++#include <net/ip.h>
++#include <net/tcp.h>
++#include <linux/in.h>
++#include <linux/ppp_defs.h>
++#include <linux/if_pppox.h>
++#endif
++#include <linux/delay.h>
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
++#include <linux/sched.h>
++#endif
++
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
++#include <asm/rt2880/rt_mmap.h>
++#else
++#include <linux/libata-compat.h>
++#endif
++
++#include "ra2882ethreg.h"
++#include "raether.h"
++#include "ra_mac.h"
++#include "ra_ioctl.h"
++#include "ra_rfrw.h"
++#ifdef CONFIG_RAETH_NETLINK
++#include "ra_netlink.h"
++#endif
++#if defined (CONFIG_RAETH_QOS)
++#include "ra_qos.h"
++#endif
++
++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
++#include "../../../net/nat/hw_nat/ra_nat.h"
++#endif
++
++#if defined (TASKLET_WORKQUEUE_SW)
++int init_schedule;
++int working_schedule;
++#endif
++
++
++#if !defined(CONFIG_RA_NAT_NONE)
++/* bruce+
++ */
++extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb);
++extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no);
++#endif
++
++#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE)
++/* Qwert+
++ */
++#include <asm/mipsregs.h>
++extern int (*ra_classifier_hook_tx)(struct sk_buff *skb, unsigned long cur_cycle);
++extern int (*ra_classifier_hook_rx)(struct sk_buff *skb, unsigned long cur_cycle);
++#endif /* CONFIG_RA_CLASSIFIER */
++
++#if defined (CONFIG_RALINK_RT3052_MP2)
++int32_t mcast_rx(struct sk_buff * skb);
++int32_t mcast_tx(struct sk_buff * skb);
++#endif
++
++#ifdef RA_MTD_RW_BY_NUM
++int ra_mtd_read(int num, loff_t from, size_t len, u_char *buf);
++#else
++int ra_mtd_read_nm(char *name, loff_t from, size_t len, u_char *buf);
++#endif
++
++/* gmac driver feature set config */
++#if defined (CONFIG_RAETH_NAPI) || defined (CONFIG_RAETH_QOS)
++#undef DELAY_INT
++#else
++#define DELAY_INT 1
++#endif
++
++//#define CONFIG_UNH_TEST
++/* end of config */
++
++#if defined (CONFIG_RAETH_JUMBOFRAME)
++#define MAX_RX_LENGTH 4096
++#else
++#define MAX_RX_LENGTH 1536
++#endif
++
++extern struct net_device *dev_raether;
++
++#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
++static int rx_dma_owner_idx1;
++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
++static int rx_calc_idx1;
++#endif
++#endif
++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
++static int rx_calc_idx0;
++static unsigned long tx_cpu_owner_idx0=0;
++#endif
++static unsigned long tx_ring_full=0;
++
++#if defined (CONFIG_ETHTOOL) && defined (CONFIG_RAETH_ROUTER)
++#include "ra_ethtool.h"
++extern struct ethtool_ops ra_ethtool_ops;
++#ifdef CONFIG_PSEUDO_SUPPORT
++extern struct ethtool_ops ra_virt_ethtool_ops;
++#endif // CONFIG_PSEUDO_SUPPORT //
++#endif // (CONFIG_ETHTOOL //
++
++#ifdef CONFIG_RALINK_VISTA_BASIC
++int is_switch_175c = 1;
++#endif
++
++//skb->mark to queue mapping table
++extern unsigned int M2Q_table[64];
++
++
++#define KSEG1 0xa0000000
++#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
++#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
++
++extern void set_fe_dma_glo_cfg(void);
++
++
++/**
++ *
++ * @brief: get the TXD index from its address
++ *
++ * @param: cpu_ptr
++ *
++ * @return: TXD index
++*/
++
++static unsigned int GET_TXD_OFFSET(struct QDMA_txdesc **cpu_ptr)
++{
++ struct net_device *dev = dev_raether;
++ END_DEVICE *ei_local = netdev_priv(dev);
++ int ctx_offset;
++ ctx_offset = (((((u32)*cpu_ptr) <<8)>>8) - ((((u32)ei_local->txd_pool)<<8)>>8))/ sizeof(struct QDMA_txdesc);
++ ctx_offset = (*cpu_ptr - ei_local->txd_pool);
++
++ return ctx_offset;
++}
++
++
++
++/**
++ * @brief get free TXD from TXD queue
++ *
++ * @param free_txd
++ *
++ * @return
++ */
++static int get_free_txd(struct QDMA_txdesc **free_txd)
++{
++ struct net_device *dev = dev_raether;
++ END_DEVICE *ei_local = netdev_priv(dev);
++ unsigned int tmp_idx;
++
++ if(ei_local->free_txd_num > 0){
++ tmp_idx = ei_local->free_txd_head;
++ ei_local->free_txd_head = ei_local->txd_pool_info[tmp_idx];
++ ei_local->free_txd_num -= 1;
++ *free_txd = &ei_local->txd_pool[tmp_idx];
++ return tmp_idx;
++ }else
++ return NUM_TX_DESC;
++}
++
++
++/**
++ * @brief add free TXD into TXD queue
++ *
++ * @param free_txd
++ *
++ * @return
++ */
++int put_free_txd(int free_txd_idx)
++{
++ struct net_device *dev = dev_raether;
++ END_DEVICE *ei_local = netdev_priv(dev);
++ ei_local->txd_pool_info[ei_local->free_txd_tail] = free_txd_idx;
++ ei_local->free_txd_tail = free_txd_idx;
++ ei_local->txd_pool_info[free_txd_idx] = NUM_TX_DESC;
++ ei_local->free_txd_num += 1;
++ return 1;
++}
++
++/*define qdma initial alloc*/
++/**
++ * @brief
++ *
++ * @param net_dev
++ *
++ * @return 0: fail
++ * 1: success
++ */
++bool qdma_tx_desc_alloc(void)
++{
++ struct net_device *dev = dev_raether;
++ END_DEVICE *ei_local = netdev_priv(dev);
++ struct QDMA_txdesc *free_txd = NULL;
++ unsigned int txd_idx;
++ int i = 0;
++
++
++ ei_local->txd_pool = pci_alloc_consistent(NULL, sizeof(struct QDMA_txdesc) * NUM_TX_DESC, &ei_local->phy_txd_pool);
++ printk("txd_pool=%p phy_txd_pool=%08X\n", ei_local->txd_pool , ei_local->phy_txd_pool);
++
++ if (ei_local->txd_pool == NULL) {
++ printk("adapter->txd_pool allocation failed!\n");
++ return 0;
++ }
++ printk("ei_local->skb_free start address is 0x%p.\n", ei_local->skb_free);
++ //set all txd_pool_info to 0.
++ for ( i = 0; i < NUM_TX_DESC; i++)
++ {
++ ei_local->skb_free[i]= 0;
++ ei_local->txd_pool_info[i] = i + 1;
++ ei_local->txd_pool[i].txd_info3.LS_bit = 1;
++ ei_local->txd_pool[i].txd_info3.OWN_bit = 1;
++ }
++
++ ei_local->free_txd_head = 0;
++ ei_local->free_txd_tail = NUM_TX_DESC - 1;
++ ei_local->free_txd_num = NUM_TX_DESC;
++
++
++ //get free txd from txd pool
++ txd_idx = get_free_txd(&free_txd);
++ if( txd_idx == NUM_TX_DESC) {
++ printk("get_free_txd fail\n");
++ return 0;
++ }
++
++ //add null TXD for transmit
++ ei_local->tx_dma_ptr = VIRT_TO_PHYS(free_txd);
++ ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
++ sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
++ sysRegWrite(QTX_DTX_PTR, ei_local->tx_dma_ptr);
++
++ //get free txd from txd pool
++
++ txd_idx = get_free_txd(&free_txd);
++ if( txd_idx == NUM_TX_DESC) {
++ printk("get_free_txd fail\n");
++ return 0;
++ }
++ // add null TXD for release
++ sysRegWrite(QTX_CRX_PTR, VIRT_TO_PHYS(free_txd));
++ sysRegWrite(QTX_DRX_PTR, VIRT_TO_PHYS(free_txd));
++
++ printk("free_txd: %p, ei_local->cpu_ptr: %08X\n", free_txd, ei_local->tx_cpu_ptr);
++
++ printk(" POOL HEAD_PTR | DMA_PTR | CPU_PTR \n");
++ printk("----------------+---------+--------\n");
++#if 1
++ printk(" 0x%p 0x%08X 0x%08X\n",ei_local->txd_pool,
++ ei_local->tx_dma_ptr, ei_local->tx_cpu_ptr);
++#endif
++ return 1;
++}
++
++bool fq_qdma_init(void)
++{
++ struct QDMA_txdesc *free_head = NULL;
++ unsigned int free_head_phy;
++ unsigned int free_tail_phy;
++ unsigned int *free_page_head = NULL;
++ unsigned int free_page_head_phy;
++ int i;
++
++ free_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * sizeof(struct QDMA_txdesc), &free_head_phy);
++ if (unlikely(free_head == NULL)){
++ printk(KERN_ERR "QDMA FQ decriptor not available...\n");
++ return 0;
++ }
++ memset(free_head, 0x0, sizeof(struct QDMA_txdesc) * NUM_QDMA_PAGE);
++
++ free_page_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, &free_page_head_phy);
++ if (unlikely(free_page_head == NULL)){
++ printk(KERN_ERR "QDMA FQ pager not available...\n");
++ return 0;
++ }
++ for (i=0; i < NUM_QDMA_PAGE; i++) {
++ free_head[i].txd_info1.SDP = (free_page_head_phy + (i * QDMA_PAGE_SIZE));
++ if(i < (NUM_QDMA_PAGE-1)){
++ free_head[i].txd_info2.NDP = (free_head_phy + ((i+1) * sizeof(struct QDMA_txdesc)));
++
++
++#if 0
++ printk("free_head_phy[%d] is 0x%x!!!\n",i, VIRT_TO_PHYS(&free_head[i]) );
++ printk("free_head[%d] is 0x%x!!!\n",i, &free_head[i] );
++ printk("free_head[%d].txd_info1.SDP is 0x%x!!!\n",i, free_head[i].txd_info1.SDP );
++ printk("free_head[%d].txd_info2.NDP is 0x%x!!!\n",i, free_head[i].txd_info2.NDP );
++#endif
++ }
++ free_head[i].txd_info3.SDL = QDMA_PAGE_SIZE;
++
++ }
++ free_tail_phy = (free_head_phy + (u32)((NUM_QDMA_PAGE-1) * sizeof(struct QDMA_txdesc)));
++
++ printk("free_head_phy is 0x%x!!!\n", free_head_phy);
++ printk("free_tail_phy is 0x%x!!!\n", free_tail_phy);
++ sysRegWrite(QDMA_FQ_HEAD, (u32)free_head_phy);
++ sysRegWrite(QDMA_FQ_TAIL, (u32)free_tail_phy);
++ sysRegWrite(QDMA_FQ_CNT, ((NUM_TX_DESC << 16) | NUM_QDMA_PAGE));
++ sysRegWrite(QDMA_FQ_BLEN, QDMA_PAGE_SIZE << 16);
++ return 1;
++}
++
++int fe_dma_init(struct net_device *dev)
++{
++
++ int i;
++ unsigned int regVal;
++ END_DEVICE* ei_local = netdev_priv(dev);
++
++ fq_qdma_init();
++
++ while(1)
++ {
++ regVal = sysRegRead(QDMA_GLO_CFG);
++ if((regVal & RX_DMA_BUSY))
++ {
++ printk("\n RX_DMA_BUSY !!! ");
++ continue;
++ }
++ if((regVal & TX_DMA_BUSY))
++ {
++ printk("\n TX_DMA_BUSY !!! ");
++ continue;
++ }
++ break;
++ }
++ /*tx desc alloc, add a NULL TXD to HW*/
++
++ qdma_tx_desc_alloc();
++
++
++ /* Initial RX Ring 0*/
++#ifdef CONFIG_32B_DESC
++ ei_local->rx_ring0 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
++ ei_local->phy_rx_ring0 = virt_to_phys(ei_local->rx_ring0);
++#else
++ ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
++#endif
++ for (i = 0; i < NUM_RX_DESC; i++) {
++ memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
++ ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
++#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
++ ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
++ ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
++#else
++ ei_local->rx_ring0[i].rxd_info2.LS0 = 1;
++#endif
++ ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
++ }
++ printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
++
++#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
++ /* Initial RX Ring 1*/
++#ifdef CONFIG_32B_DESC
++ ei_local->rx_ring1 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
++ ei_local->phy_rx_ring1 = virt_to_phys(ei_local->rx_ring1);
++#else
++ ei_local->rx_ring1 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring1);
++#endif
++ for (i = 0; i < NUM_RX_DESC; i++) {
++ memset(&ei_local->rx_ring1[i],0,sizeof(struct PDMA_rxdesc));
++ ei_local->rx_ring1[i].rxd_info2.DDONE_bit = 0;
++#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
++ ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
++ ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
++#else
++ ei_local->rx_ring1[i].rxd_info2.LS0 = 1;
++#endif
++ ei_local->rx_ring1[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx1_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
++ }
++ printk("\nphy_rx_ring1 = 0x%08x, rx_ring1 = 0x%p\n",ei_local->phy_rx_ring1,ei_local->rx_ring1);
++#endif
++
++ regVal = sysRegRead(QDMA_GLO_CFG);
++ regVal &= 0x000000FF;
++ sysRegWrite(QDMA_GLO_CFG, regVal);
++ regVal=sysRegRead(QDMA_GLO_CFG);
++
++ /* Tell the adapter where the TX/RX rings are located. */
++
++ sysRegWrite(QRX_BASE_PTR_0, phys_to_bus((u32) ei_local->phy_rx_ring0));
++ sysRegWrite(QRX_MAX_CNT_0, cpu_to_le32((u32) NUM_RX_DESC));
++ sysRegWrite(QRX_CRX_IDX_0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
++ rx_calc_idx0 = rx_dma_owner_idx0 = sysRegRead(QRX_CRX_IDX_0);
++#endif
++ sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX0);
++#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
++ sysRegWrite(QRX_BASE_PTR_1, phys_to_bus((u32) ei_local->phy_rx_ring1));
++ sysRegWrite(QRX_MAX_CNT_1, cpu_to_le32((u32) NUM_RX_DESC));
++ sysRegWrite(QRX_CRX_IDX_1, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
++ rx_calc_idx1 = rx_dma_owner_idx1 = sysRegRead(QRX_CRX_IDX_1);
++#endif
++ sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX1);
++#endif
++
++ set_fe_dma_glo_cfg();
++
++ return 1;
++}
++
++inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no)
++{
++ unsigned int length=skb->len;
++ END_DEVICE* ei_local = netdev_priv(dev);
++
++ struct QDMA_txdesc *cpu_ptr;
++
++ struct QDMA_txdesc *dma_ptr __maybe_unused;
++ struct QDMA_txdesc *free_txd;
++ int ctx_offset;
++#if defined (CONFIG_RAETH_TSO)
++ struct iphdr *iph = NULL;
++ struct QDMA_txdesc *init_cpu_ptr;
++ struct tcphdr *th = NULL;
++ struct skb_frag_struct *frag;
++ unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
++ int i=0;
++ int init_txd_idx;
++#endif // CONFIG_RAETH_TSO //
++
++#if defined (CONFIG_RAETH_TSOV6)
++ struct ipv6hdr *ip6h = NULL;
++#endif
++
++#ifdef CONFIG_PSEUDO_SUPPORT
++ PSEUDO_ADAPTER *pAd;
++#endif
++ cpu_ptr = PHYS_TO_VIRT(ei_local->tx_cpu_ptr);
++ dma_ptr = PHYS_TO_VIRT(ei_local->tx_dma_ptr);
++ ctx_offset = GET_TXD_OFFSET(&cpu_ptr);
++ ei_local->skb_free[ctx_offset] = skb;
++#if defined (CONFIG_RAETH_TSO)
++ init_cpu_ptr = cpu_ptr;
++ init_txd_idx = ctx_offset;
++#endif
++
++#if !defined (CONFIG_RAETH_TSO)
++
++ //2. prepare data
++ cpu_ptr->txd_info1.SDP = VIRT_TO_PHYS(skb->data);
++ cpu_ptr->txd_info3.SDL = skb->len;
++
++ if (gmac_no == 1) {
++ cpu_ptr->txd_info4.FPORT = 1;
++ }else {
++ cpu_ptr->txd_info4.FPORT = 2;
++ }
++
++
++ cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
++#if 0
++ iph = (struct iphdr *)skb_network_header(skb);
++ if (iph->tos == 0xe0)
++ cpu_ptr->txd_info3.QID = 3;
++ else if (iph->tos == 0xa0)
++ cpu_ptr->txd_info3.QID = 2;
++ else if (iph->tos == 0x20)
++ cpu_ptr->txd_info3.QID = 1;
++ else
++ cpu_ptr->txd_info3.QID = 0;
++#endif
++
++#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
++ if (skb->ip_summed == CHECKSUM_PARTIAL){
++ cpu_ptr->txd_info4.TUI_CO = 7;
++ }else {
++ cpu_ptr->txd_info4.TUI_CO = 0;
++ }
++#endif
++
++#ifdef CONFIG_RAETH_HW_VLAN_TX
++ if(vlan_tx_tag_present(skb)) {
++ cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
++ }else {
++ cpu_ptr->txd_info4.VLAN_TAG = 0;
++ }
++#endif
++
++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
++ if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
++ if(ra_sw_nat_hook_rx!= NULL){
++ cpu_ptr->txd_info4.FPORT = 4; /* PPE */
++ FOE_MAGIC_TAG(skb) = 0;
++ }
++ }
++#endif
++#if 0
++ cpu_ptr->txd_info4.FPORT = 4; /* PPE */
++ cpu_ptr->txd_info4.UDF = 0x2F;
++#endif
++
++ dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
++ cpu_ptr->txd_info3.SWC_bit = 1;
++
++ //3. get NULL TXD and decrease free_tx_num by 1.
++ ctx_offset = get_free_txd(&free_txd);
++ if(ctx_offset == NUM_TX_DESC) {
++ printk("get_free_txd fail\n"); // this should not happen. free_txd_num is 2 at least.
++ return 0;
++ }
++
++ //4. hook new TXD in the end of queue
++ cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
++
++
++ //5. move CPU_PTR to new TXD
++ ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
++ cpu_ptr->txd_info3.OWN_bit = 0;
++ sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
++
++#if 0
++ printk("----------------------------------------------\n");
++ printk("txd_info1:%08X \n",*(int *)&cpu_ptr->txd_info1);
++ printk("txd_info2:%08X \n",*(int *)&cpu_ptr->txd_info2);
++ printk("txd_info3:%08X \n",*(int *)&cpu_ptr->txd_info3);
++ printk("txd_info4:%08X \n",*(int *)&cpu_ptr->txd_info4);
++#endif
++
++#else //#if !defined (CONFIG_RAETH_TSO)
++ cpu_ptr->txd_info1.SDP = VIRT_TO_PHYS(skb->data);
++ cpu_ptr->txd_info3.SDL = (length - skb->data_len);
++ cpu_ptr->txd_info3.LS_bit = nr_frags ? 0:1;
++ if (gmac_no == 1) {
++ cpu_ptr->txd_info4.FPORT = 1;
++ }else {
++ cpu_ptr->txd_info4.FPORT = 2;
++ }
++
++ cpu_ptr->txd_info4.TSO = 0;
++ cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
++#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
++ if (skb->ip_summed == CHECKSUM_PARTIAL){
++ cpu_ptr->txd_info4.TUI_CO = 7;
++ }else {
++ cpu_ptr->txd_info4.TUI_CO = 0;
++ }
++#endif
++
++#ifdef CONFIG_RAETH_HW_VLAN_TX
++ if(vlan_tx_tag_present(skb)) {
++ cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
++ }else {
++ cpu_ptr->txd_info4.VLAN_TAG = 0;
++ }
++#endif
++
++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
++ if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
++ if(ra_sw_nat_hook_rx!= NULL){
++ cpu_ptr->txd_info4.FPORT = 4; /* PPE */
++ FOE_MAGIC_TAG(skb) = 0;
++ }
++ }
++#endif
++
++ cpu_ptr->txd_info3.SWC_bit = 1;
++
++ ctx_offset = get_free_txd(&free_txd);
++ if(ctx_offset == NUM_TX_DESC) {
++ printk("get_free_txd fail\n");
++ return 0;
++ }
++ cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
++ ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
++
++ if(nr_frags > 0) {
++ for(i=0;i<nr_frags;i++) {
++ frag = &skb_shinfo(skb)->frags[i];
++ cpu_ptr = free_txd;
++ cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
++ cpu_ptr->txd_info1.SDP = pci_map_page(NULL, frag->page, frag->page_offset, frag->size, PCI_DMA_TODEVICE);
++ cpu_ptr->txd_info3.SDL = frag->size;
++ cpu_ptr->txd_info3.LS_bit = (i==nr_frags-1)?1:0;
++ cpu_ptr->txd_info3.OWN_bit = 0;
++ cpu_ptr->txd_info3.SWC_bit = 1;
++ ei_local->skb_free[ctx_offset] = (i==nr_frags-1)?skb:(struct sk_buff *)0xFFFFFFFF; //MAGIC ID
++
++ ctx_offset = get_free_txd(&free_txd);
++ cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
++ ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
++ }
++ ei_local->skb_free[init_txd_idx]= (struct sk_buff *)0xFFFFFFFF; //MAGIC ID
++ }
++
++ if(skb_shinfo(skb)->gso_segs > 1) {
++
++// TsoLenUpdate(skb->len);
++
++ /* TCP over IPv4 */
++ iph = (struct iphdr *)skb_network_header(skb);
++#if defined (CONFIG_RAETH_TSOV6)
++ /* TCP over IPv6 */
++ ip6h = (struct ipv6hdr *)skb_network_header(skb);
++#endif
++ if((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
++ th = (struct tcphdr *)skb_transport_header(skb);
++
++ init_cpu_ptr->txd_info4.TSO = 1;
++
++ th->check = htons(skb_shinfo(skb)->gso_size);
++ dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
++ }
++
++#if defined (CONFIG_RAETH_TSOV6)
++ /* TCP over IPv6 */
++ //ip6h = (struct ipv6hdr *)skb_network_header(skb);
++ else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) {
++ th = (struct tcphdr *)skb_transport_header(skb);
++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
++ init_cpu_ptr->txd_info4.TSO = 1;
++#else
++ init_cpu_ptr->txd_info4.TSO = 1;
++#endif
++ th->check = htons(skb_shinfo(skb)->gso_size);
++ dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
++ }
++#endif
++ }
++
++
++// dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
++
++ init_cpu_ptr->txd_info3.OWN_bit = 0;
++#endif // CONFIG_RAETH_TSO //
++
++ sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
++
++#ifdef CONFIG_PSEUDO_SUPPORT
++ if (gmac_no == 2) {
++ if (ei_local->PseudoDev != NULL) {
++ pAd = netdev_priv(ei_local->PseudoDev);
++ pAd->stat.tx_packets++;
++ pAd->stat.tx_bytes += length;
++ }
++ } else
++
++#endif
++ {
++ ei_local->stat.tx_packets++;
++ ei_local->stat.tx_bytes += skb->len;
++ }
++ return length;
++}
++
++int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no)
++{
++ END_DEVICE *ei_local = netdev_priv(dev);
++ unsigned long flags;
++ unsigned int num_of_txd;
++#if defined (CONFIG_RAETH_TSO)
++ unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
++#endif
++#ifdef CONFIG_PSEUDO_SUPPORT
++ PSEUDO_ADAPTER *pAd;
++#endif
++
++#if !defined(CONFIG_RA_NAT_NONE)
++ if(ra_sw_nat_hook_tx!= NULL)
++ {
++ spin_lock_irqsave(&ei_local->page_lock, flags);
++ if(ra_sw_nat_hook_tx(skb, gmac_no)==1){
++ spin_unlock_irqrestore(&ei_local->page_lock, flags);
++ }else{
++ kfree_skb(skb);
++ spin_unlock_irqrestore(&ei_local->page_lock, flags);
++ return 0;
++ }
++ }
++#endif
++
++
++
++ dev->trans_start = jiffies; /* save the timestamp */
++ spin_lock_irqsave(&ei_local->page_lock, flags);
++ dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
++
++
++//check free_txd_num before calling rt288_eth_send()
++
++#if defined (CONFIG_RAETH_TSO)
++ num_of_txd = (nr_frags==0) ? 1 : (nr_frags + 1);
++#else
++ num_of_txd = 1;
++#endif
++
++#if defined(CONFIG_RALINK_MT7621)
++ if(sysRegRead(0xbe00000c)==0x00030101) {
++ ei_xmit_housekeeping(0);
++ }
++#endif
++
++
++ if ((ei_local->free_txd_num > num_of_txd + 1) && (ei_local->free_txd_num != NUM_TX_DESC))
++ {
++ rt2880_eth_send(dev, skb, gmac_no); // need to modify rt2880_eth_send() for QDMA
++ if (ei_local->free_txd_num < 3)
++ {
++#if defined (CONFIG_RAETH_STOP_RX_WHEN_TX_FULL)
++ netif_stop_queue(dev);
++#ifdef CONFIG_PSEUDO_SUPPORT
++ netif_stop_queue(ei_local->PseudoDev);
++#endif
++ tx_ring_full = 1;
++#endif
++ }
++ } else {
++#ifdef CONFIG_PSEUDO_SUPPORT
++ if (gmac_no == 2)
++ {
++ if (ei_local->PseudoDev != NULL)
++ {
++ pAd = netdev_priv(ei_local->PseudoDev);
++ pAd->stat.tx_dropped++;
++ }
++ } else
++#endif
++ ei_local->stat.tx_dropped++;
++ kfree_skb(skb);
++ spin_unlock_irqrestore(&ei_local->page_lock, flags);
++ return 0;
++ }
++ spin_unlock_irqrestore(&ei_local->page_lock, flags);
++ return 0;
++}
++
++void ei_xmit_housekeeping(unsigned long unused)
++{
++ struct net_device *dev = dev_raether;
++ END_DEVICE *ei_local = netdev_priv(dev);
++#ifndef CONFIG_RAETH_NAPI
++ unsigned long reg_int_mask=0;
++#endif
++ struct QDMA_txdesc *dma_ptr = NULL;
++ struct QDMA_txdesc *cpu_ptr = NULL;
++ struct QDMA_txdesc *tmp_ptr = NULL;
++ unsigned int htx_offset = 0;
++
++ dma_ptr = PHYS_TO_VIRT(sysRegRead(QTX_DRX_PTR));
++ cpu_ptr = PHYS_TO_VIRT(sysRegRead(QTX_CRX_PTR));
++ if(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) {
++ while(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) {
++
++ //1. keep cpu next TXD
++ tmp_ptr = PHYS_TO_VIRT(cpu_ptr->txd_info2.NDP);
++ htx_offset = GET_TXD_OFFSET(&tmp_ptr);
++ //2. free skb meomry
++#if defined (CONFIG_RAETH_TSO)
++ if(ei_local->skb_free[htx_offset]!=(struct sk_buff *)0xFFFFFFFF) {
++ dev_kfree_skb_any(ei_local->skb_free[htx_offset]);
++ }
++#else
++ dev_kfree_skb_any(ei_local->skb_free[htx_offset]);
++#endif
++
++ //3. release TXD
++ htx_offset = GET_TXD_OFFSET(&cpu_ptr);
++ put_free_txd(htx_offset);
++
++ netif_wake_queue(dev);
++#ifdef CONFIG_PSEUDO_SUPPORT
++ netif_wake_queue(ei_local->PseudoDev);
++#endif
++ tx_ring_full=0;
++
++ //4. update cpu_ptr to next ptr
++ cpu_ptr = tmp_ptr;
++ }
++ }
++ sysRegWrite(QTX_CRX_PTR, VIRT_TO_PHYS(cpu_ptr));
++#ifndef CONFIG_RAETH_NAPI
++ reg_int_mask=sysRegRead(QFE_INT_ENABLE);
++#if defined (DELAY_INT)
++ sysRegWrite(FE_INT_ENABLE, reg_int_mask| RLS_DLY_INT);
++#else
++
++ sysRegWrite(FE_INT_ENABLE, reg_int_mask | RLS_DONE_INT);
++#endif
++#endif //CONFIG_RAETH_NAPI//
++}
++
++EXPORT_SYMBOL(ei_start_xmit);
++EXPORT_SYMBOL(ei_xmit_housekeeping);
++EXPORT_SYMBOL(fe_dma_init);
++EXPORT_SYMBOL(rt2880_eth_send);
+--- a/drivers/net/ethernet/Kconfig
++++ b/drivers/net/ethernet/Kconfig
+@@ -136,6 +136,7 @@ source "drivers/net/ethernet/packetengin
+ source "drivers/net/ethernet/pasemi/Kconfig"
+ source "drivers/net/ethernet/qlogic/Kconfig"
+ source "drivers/net/ethernet/ralink/Kconfig"
++source "drivers/net/ethernet/raeth/Kconfig"
+ source "drivers/net/ethernet/realtek/Kconfig"
+ source "drivers/net/ethernet/renesas/Kconfig"
+ source "drivers/net/ethernet/rdc/Kconfig"
+--- a/drivers/net/ethernet/Makefile
++++ b/drivers/net/ethernet/Makefile
+@@ -54,6 +54,7 @@ obj-$(CONFIG_NET_PACKET_ENGINE) += packe
+ obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
+ obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
+ obj-$(CONFIG_NET_RALINK) += ralink/
++obj-$(CONFIG_RAETH) += raeth/
+ obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
+ obj-$(CONFIG_SH_ETH) += renesas/
+ obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
+--- /dev/null
++++ b/arch/mips/include/asm/rt2880/board-custom.h
+@@ -0,0 +1,153 @@
++/* Copyright Statement:
++ *
++ * This software/firmware and related documentation ("MediaTek Software") are
++ * protected under relevant copyright laws. The information contained herein
++ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
++ * Without the prior written permission of MediaTek inc. and/or its licensors,
++ * any reproduction, modification, use or disclosure of MediaTek Software,
++ * and information contained herein, in whole or in part, shall be strictly prohibited.
++ */
++/* MediaTek Inc. (C) 2010. All rights reserved.
++ *
++ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++ *
++ * The following software/firmware and/or related documentation ("MediaTek Software")
++ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
++ * applicable license agreements with MediaTek Inc.
++ */
++
++#ifndef __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
++#define __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
++
++#include <linux/autoconf.h>
++
++/*=======================================================================*/
++/* MT6575 SD */
++/*=======================================================================*/
++#ifdef MTK_EMMC_SUPPORT
++#define CFG_DEV_MSDC0
++#endif
++#define CFG_DEV_MSDC1
++#define CFG_DEV_MSDC2
++#define CFG_DEV_MSDC3
++#if defined(CONFIG_MTK_COMBO) || defined(CONFIG_MTK_COMBO_MODULE)
++/*
++SDIO slot index number used by connectivity combo chip:
++0: invalid (used by memory card)
++1: MSDC1
++2: MSDC2
++*/
++#define CONFIG_MTK_WCN_CMB_SDIO_SLOT (2) /* MSDC2 */
++#else
++#undef CONFIG_MTK_WCN_CMB_SDIO_SLOT
++#endif
++
++#if 0 /* FIXME. */
++/*=======================================================================*/
++/* MT6575 UART */
++/*=======================================================================*/
++#define CFG_DEV_UART1
++#define CFG_DEV_UART2
++#define CFG_DEV_UART3
++#define CFG_DEV_UART4
++
++#define CFG_UART_PORTS (4)
++
++/*=======================================================================*/
++/* MT6575 I2C */
++/*=======================================================================*/
++#define CFG_DEV_I2C
++//#define CFG_I2C_HIGH_SPEED_MODE
++//#define CFG_I2C_DMA_MODE
++
++/*=======================================================================*/
++/* MT6575 ADB */
++/*=======================================================================*/
++#define ADB_SERIAL "E1K"
++
++#endif
++
++/*=======================================================================*/
++/* MT6575 NAND FLASH */
++/*=======================================================================*/
++#if 0
++#define RAMDOM_READ 1<<0
++#define CACHE_READ 1<<1
++/*******************************************************************************
++ * NFI & ECC Configuration
++ *******************************************************************************/
++typedef struct
++{
++ u16 id; //deviceid+menuid
++ u8 addr_cycle;
++ u8 iowidth;
++ u16 totalsize;
++ u16 blocksize;
++ u16 pagesize;
++ u32 timmingsetting;
++ char devciename[14];
++ u32 advancedmode; //
++}flashdev_info,*pflashdev_info;
++
++static const flashdev_info g_FlashTable[]={
++ //micro
++ {0xAA2C, 5, 8, 256, 128, 2048, 0x01113, "MT29F2G08ABD", 0},
++ {0xB12C, 4, 16, 128, 128, 2048, 0x01113, "MT29F1G16ABC", 0},
++ {0xBA2C, 5, 16, 256, 128, 2048, 0x01113, "MT29F2G16ABD", 0},
++ {0xAC2C, 5, 8, 512, 128, 2048, 0x01113, "MT29F4G08ABC", 0},
++ {0xBC2C, 5, 16, 512, 128, 2048, 0x44333, "MT29F4G16ABD", 0},
++ //samsung
++ {0xBAEC, 5, 16, 256, 128, 2048, 0x01123, "K522H1GACE", 0},
++ {0xBCEC, 5, 16, 512, 128, 2048, 0x01123, "K524G2GACB", 0},
++ {0xDAEC, 5, 8, 256, 128, 2048, 0x33222, "K9F2G08U0A", RAMDOM_READ},
++ {0xF1EC, 4, 8, 128, 128, 2048, 0x01123, "K9F1G08U0A", RAMDOM_READ},
++ {0xAAEC, 5, 8, 256, 128, 2048, 0x01123, "K9F2G08R0A", 0},
++ //hynix
++ {0xD3AD, 5, 8, 1024, 256, 2048, 0x44333, "HY27UT088G2A", 0},
++ {0xA1AD, 4, 8, 128, 128, 2048, 0x01123, "H8BCSOPJOMCP", 0},
++ {0xBCAD, 5, 16, 512, 128, 2048, 0x01123, "H8BCSOUNOMCR", 0},
++ {0xBAAD, 5, 16, 256, 128, 2048, 0x01123, "H8BCSOSNOMCR", 0},
++ //toshiba
++ {0x9598, 5, 16, 816, 128, 2048, 0x00113, "TY9C000000CMG", 0},
++ {0x9498, 5, 16, 375, 128, 2048, 0x00113, "TY9C000000CMG", 0},
++ {0xC198, 4, 16, 128, 128, 2048, 0x44333, "TC58NWGOS8C", 0},
++ {0xBA98, 5, 16, 256, 128, 2048, 0x02113, "TC58NYG1S8C", 0},
++ //st-micro
++ {0xBA20, 5, 16, 256, 128, 2048, 0x01123, "ND02CGR4B2DI6", 0},
++
++ // elpida
++ {0xBC20, 5, 16, 512, 128, 2048, 0x01123, "04GR4B2DDI6", 0},
++ {0x0000, 0, 0, 0, 0, 0, 0, "xxxxxxxxxxxxx", 0}
++};
++#endif
++
++
++#define NFI_DEFAULT_ACCESS_TIMING (0x44333)
++
++//uboot only support 1 cs
++#define NFI_CS_NUM (2)
++#define NFI_DEFAULT_CS (0)
++
++#define USE_AHB_MODE (1)
++
++#define PLATFORM_EVB (1)
++
++#endif /* __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H */
++
+--- /dev/null
++++ b/arch/mips/include/asm/rt2880/eureka_ep430.h
+@@ -0,0 +1,204 @@
++/**************************************************************************
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ **************************************************************************
++ */
++
++#ifndef _EUREKA_EP430_H
++#define _EUREKA_EP430_H
++
++
++#include <asm/addrspace.h> /* for KSEG1ADDR() */
++#include <asm/byteorder.h> /* for cpu_to_le32() */
++#include <asm/mach-ralink/rt_mmap.h>
++
++
++/*
++ * Because of an error/peculiarity in the Galileo chip, we need to swap the
++ * bytes when running bigendian.
++ */
++
++#define MV_WRITE(ofs, data) \
++ *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
++#define MV_READ(ofs, data) \
++ *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
++#define MV_READ_DATA(ofs) \
++ le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
++
++#define MV_WRITE_16(ofs, data) \
++ *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
++#define MV_READ_16(ofs, data) \
++ *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
++
++#define MV_WRITE_8(ofs, data) \
++ *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
++#define MV_READ_8(ofs, data) \
++ *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
++
++#define MV_SET_REG_BITS(ofs,bits) \
++ (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) |= ((u32)cpu_to_le32(bits))
++#define MV_RESET_REG_BITS(ofs,bits) \
++ (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) &= ~((u32)cpu_to_le32(bits))
++
++#define RALINK_PCI_CONFIG_ADDR 0x20
++#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
++
++#if defined(CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT2883)
++#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
++#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
++#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
++#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
++#define RALINK_PCI_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0010)
++#define RALINK_PCI_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0018)
++#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
++#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
++#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
++#define RALINK_PCI_ID *(volatile u32 *)(RALINK_PCI_BASE + 0x0030)
++#define RALINK_PCI_CLASS *(volatile u32 *)(RALINK_PCI_BASE + 0x0034)
++#define RALINK_PCI_SUBID *(volatile u32 *)(RALINK_PCI_BASE + 0x0038)
++#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
++#define RALINK_PCI_STATUS *(volatile u32 *)(RALINK_PCI_BASE + 0x0050)
++
++#elif defined(CONFIG_RALINK_RT3883)
++
++#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
++#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
++#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
++#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
++#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
++#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
++#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
++#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
++
++/*
++PCI0 --> PCI
++PCI1 --> PCIe
++*/
++#define RT3883_PCI_OFFSET 0x1000
++#define RT3883_PCIE_OFFSET 0x2000
++
++#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0010)
++#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0018)
++#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0030)
++#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0034)
++#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0038)
++
++#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0010)
++#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0018)
++#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0030)
++#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0034)
++#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0038)
++#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0050)
++
++#elif defined(CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7628)
++
++#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
++#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
++#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
++#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
++#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
++#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
++#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
++#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
++
++/*
++PCI0 --> PCIe 0
++PCI1 --> PCIe 1
++*/
++#define RT6855_PCIE0_OFFSET 0x2000
++#define RT6855_PCIE1_OFFSET 0x3000
++
++#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
++#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
++#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
++#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
++#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
++#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
++#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
++#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
++
++#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
++#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
++#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
++#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
++#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
++#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
++#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
++#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
++
++#elif defined (CONFIG_RALINK_MT7621)
++
++#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
++#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
++#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
++#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
++#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
++#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
++#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
++#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
++
++/*
++PCI0 --> PCIe 0
++PCI1 --> PCIe 1
++PCI2 --> PCIe 2
++*/
++#define RT6855_PCIE0_OFFSET 0x2000
++#define RT6855_PCIE1_OFFSET 0x3000
++#define RT6855_PCIE2_OFFSET 0x4000
++
++#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
++#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
++#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
++#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
++#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
++#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
++#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
++#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
++
++#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
++#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
++#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
++#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
++#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
++#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
++#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
++#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
++
++#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
++#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
++#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
++#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
++#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
++#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
++#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
++#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
++
++#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
++#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
++
++#elif defined(CONFIG_RALINK_RT3052) || defined(CONFIG_RALINK_RT3352) || defined(CONFIG_RALINK_RT5350)
++#else
++#error "undefined in PCI"
++#endif
++
++#endif
+--- /dev/null
++++ b/arch/mips/include/asm/rt2880/generic.h
+@@ -0,0 +1,42 @@
++/*
++ * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * Defines of the Palmchip boards specific address-MAP, registers, etc.
++ */
++#ifndef __ASM_SURFBOARD_GENERIC_H
++#define __ASM_SURFBOARD_GENERIC_H
++
++#include <asm/addrspace.h>
++#include <asm/byteorder.h>
++#include <asm/mach-ralink/rt_mmap.h>
++
++/*
++ * Reset register.
++ */
++#define SOFTRES_REG (KSEG1ADDR(RALINK_SYSCTL_BASE+0x34))
++#define GORESET (0x1)
++
++/*
++ * Power-off register
++ */
++#define POWER_DIR_REG (KSEG1ADDR(RALINK_PIO_BASE+0x24))
++#define POWER_DIR_OUTPUT (0x80) /* GPIO 7 */
++#define POWER_POL_REG (KSEG1ADDR(RALINK_PIO_BASE+0x28))
++#define POWEROFF_REG (KSEG1ADDR(RALINK_PIO_BASE+0x20))
++#define POWEROFF (0x0) /* drive low */
++
++
++#endif /* __ASM_SURFBOARD_GENERIC_H */
+--- /dev/null
++++ b/arch/mips/include/asm/rt2880/lm.h
+@@ -0,0 +1,32 @@
++#include <linux/version.h>
++
++struct lm_device {
++ struct device dev;
++ struct resource resource;
++ unsigned int irq;
++ unsigned int id;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
++ void *lm_drvdata;
++#endif
++};
++
++struct lm_driver {
++ struct device_driver drv;
++ int (*probe)(struct lm_device *);
++ void (*remove)(struct lm_device *);
++ int (*suspend)(struct lm_device *, u32);
++ int (*resume)(struct lm_device *);
++};
++
++int lm_driver_register(struct lm_driver *drv);
++void lm_driver_unregister(struct lm_driver *drv);
++
++int lm_device_register(struct lm_device *dev);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
++# define lm_get_drvdata(lm) ((lm)->lm_drvdata)
++# define lm_set_drvdata(lm,d) do { (lm)->lm_drvdata = (d); } while (0)
++#else
++# define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
++# define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
++#endif
+--- /dev/null
++++ b/arch/mips/include/asm/rt2880/prom.h
+@@ -0,0 +1,50 @@
++/*
++ * Carsten Langgaard, carstenl@mips.com
++ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
++ *
++ * ########################################################################
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ * MIPS boards bootprom interface for the Linux kernel.
++ *
++ */
++
++#ifndef _MIPS_PROM_H
++#define _MIPS_PROM_H
++
++extern char *prom_getcmdline(void);
++extern char *prom_getenv(char *name);
++extern void setup_prom_printf(int tty_no);
++extern void prom_setup_printf(int tty_no);
++extern void prom_printf(char *fmt, ...);
++extern void prom_init_cmdline(void);
++extern void prom_meminit(void);
++extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
++extern void prom_free_prom_memory (void);
++extern void mips_display_message(const char *str);
++extern void mips_display_word(unsigned int num);
++extern int get_ethernet_addr(char *ethernet_addr);
++
++/* Memory descriptor management. */
++#define PROM_MAX_PMEMBLOCKS 32
++struct prom_pmemblock {
++ unsigned long base; /* Within KSEG0. */
++ unsigned int size; /* In bytes. */
++ unsigned int type; /* free or prom memory */
++};
++
++#endif /* !(_MIPS_PROM_H) */
+--- /dev/null
++++ b/arch/mips/include/asm/rt2880/rt_mmap.h
+@@ -0,0 +1,796 @@
++/**************************************************************************
++ *
++ * BRIEF MODULE DESCRIPTION
++ * register definition for Ralink RT-series SoC
++ *
++ * Copyright 2007 Ralink Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ **************************************************************************
++ */
++
++#ifndef __RALINK_MMAP__
++#define __RALINK_MMAP__
++
++#if defined (CONFIG_RALINK_RT2880_SHUTTLE)
++
++#define RALINK_SYSCTL_BASE 0xA0300000
++#define RALINK_TIMER_BASE 0xA0300100
++#define RALINK_INTCL_BASE 0xA0300200
++#define RALINK_MEMCTRL_BASE 0xA0300300
++#define RALINK_UART_BASE 0xA0300500
++#define RALINK_PIO_BASE 0xA0300600
++#define RALINK_I2C_BASE 0xA0300900
++#define RALINK_SPI_BASE 0xA0300B00
++#define RALINK_UART_LITE_BASE 0xA0300C00
++#define RALINK_FRAME_ENGINE_BASE 0xA0310000
++#define RALINK_EMBEDD_ROM_BASE 0xA0400000
++#define RALINK_PCI_BASE 0xA0500000
++#define RALINK_11N_MAC_BASE 0xA0600000
++
++//Interrupt Controller
++#define RALINK_INTCTL_TIMER0 (1<<0)
++#define RALINK_INTCTL_WDTIMER (1<<1)
++#define RALINK_INTCTL_UART (1<<2)
++#define RALINK_INTCTL_PIO (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UARTLITE (1<<8)
++#define RALINK_INTCTL_ILL_ACCESS (1<<23)
++
++//Reset Control Register
++#define RALINK_TIMER_RST (1<<1)
++#define RALINK_INTC_RST (1<<2)
++#define RALINK_MC_RST (1<<3)
++#define RALINK_CPU_RST (1<<4)
++#define RALINK_UART_RST (1<<5)
++#define RALINK_PIO_RST (1<<6)
++#define RALINK_I2C_RST (1<<9)
++#define RALINK_SPI_RST (1<<11)
++#define RALINK_UART2_RST (1<<12)
++#define RALINK_PCI_RST (1<<16)
++#define RALINK_2860_RST (1<<17)
++#define RALINK_FE_RST (1<<18)
++#define RALINK_PCM_RST (1<<19)
++
++
++#elif defined (CONFIG_RALINK_RT2880_MP)
++
++#define RALINK_SYSCTL_BASE 0xA0300000
++#define RALINK_TIMER_BASE 0xA0300100
++#define RALINK_INTCL_BASE 0xA0300200
++#define RALINK_MEMCTRL_BASE 0xA0300300
++#define RALINK_UART_BASE 0xA0300500
++#define RALINK_PIO_BASE 0xA0300600
++#define RALINK_I2C_BASE 0xA0300900
++#define RALINK_SPI_BASE 0xA0300B00
++#define RALINK_UART_LITE_BASE 0x00300C00
++#define RALINK_FRAME_ENGINE_BASE 0xA0400000
++#define RALINK_EMBEDD_ROM_BASE 0xA0410000
++#define RALINK_PCI_BASE 0xA0440000
++#define RALINK_11N_MAC_BASE 0xA0480000
++
++//Interrupt Controller
++#define RALINK_INTCTL_TIMER0 (1<<0)
++#define RALINK_INTCTL_WDTIMER (1<<1)
++#define RALINK_INTCTL_UART (1<<2)
++#define RALINK_INTCTL_PIO (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UARTLITE (1<<8)
++#define RALINK_INTCTL_ILL_ACCESS (1<<23)
++
++//Reset Control Register
++#define RALINK_TIMER_RST (1<<1)
++#define RALINK_INTC_RST (1<<2)
++#define RALINK_MC_RST (1<<3)
++#define RALINK_CPU_RST (1<<4)
++#define RALINK_UART_RST (1<<5)
++#define RALINK_PIO_RST (1<<6)
++#define RALINK_I2C_RST (1<<9)
++#define RALINK_SPI_RST (1<<11)
++#define RALINK_UART2_RST (1<<12)
++#define RALINK_PCI_RST (1<<16)
++#define RALINK_2860_RST (1<<17)
++#define RALINK_FE_RST (1<<18)
++#define RALINK_PCM_RST (1<<19)
++
++#elif defined (CONFIG_RALINK_RT3052)
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_TIMER_BASE 0xB0000100
++#define RALINK_INTCL_BASE 0xB0000200
++#define RALINK_MEMCTRL_BASE 0xB0000300
++#define RALINK_PCM_BASE 0xB0000400
++#define RALINK_UART_BASE 0x10000500
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_GDMA_BASE 0xB0000700
++#define RALINK_NAND_CTRL_BASE 0xB0000800
++#define RALINK_I2C_BASE 0xB0000900
++#define RALINK_I2S_BASE 0xB0000A00
++#define RALINK_SPI_BASE 0xB0000B00
++#define RALINK_UART_LITE_BASE 0x10000C00
++#define RALINK_FRAME_ENGINE_BASE 0xB0100000
++#define RALINK_ETH_SW_BASE 0xB0110000
++#define RALINK_11N_MAC_BASE 0xB0180000
++#define RALINK_USB_OTG_BASE 0x101C0000
++
++//Interrupt Controller
++#define RALINK_INTCTL_SYSCTL (1<<0)
++#define RALINK_INTCTL_TIMER0 (1<<1)
++#define RALINK_INTCTL_WDTIMER (1<<2)
++#define RALINK_INTCTL_ILL_ACCESS (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UART (1<<5)
++#define RALINK_INTCTL_PIO (1<<6)
++#define RALINK_INTCTL_DMA (1<<7)
++#define RALINK_INTCTL_NAND (1<<8)
++#define RALINK_INTCTL_PC (1<<9)
++#define RALINK_INTCTL_I2S (1<<10)
++#define RALINK_INTCTL_UARTLITE (1<<12)
++#define RALINK_INTCTL_ESW (1<<17)
++#define RALINK_INTCTL_OTG (1<<18)
++#define RALINK_INTCTL_OTG_IRQN 18
++#define RALINK_INTCTL_GLOBAL (1<<31)
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_CPU_RST (1<<1)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_UART_RST (1<<12)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UARTL_RST (1<<19)
++#define RALINK_RT2872_RST (1<<20)
++#define RALINK_FE_RST (1<<21)
++#define RALINK_OTG_RST (1<<22)
++#define RALINK_SW_RST (1<<23)
++#define RALINK_EPHY_RST (1<<24)
++
++#elif defined (CONFIG_RALINK_RT3352)
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_TIMER_BASE 0xB0000100
++#define RALINK_INTCL_BASE 0xB0000200
++#define RALINK_MEMCTRL_BASE 0xB0000300
++#define RALINK_UART_BASE 0x10000500
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_I2C_BASE 0xB0000900
++#define RALINK_I2S_BASE 0xB0000A00
++#define RALINK_SPI_BASE 0xB0000B00
++#define RALINK_NAND_CTRL_BASE 0xB0000800
++#define RALINK_UART_LITE_BASE 0x10000C00
++#define RALINK_PCM_BASE 0xB0002000
++#define RALINK_GDMA_BASE 0xB0002800
++#define RALINK_FRAME_ENGINE_BASE 0xB0100000
++#define RALINK_ETH_SW_BASE 0xB0110000
++#define RALINK_USB_DEV_BASE 0x10120000
++#define RALINK_11N_MAC_BASE 0xB0180000
++#define RALINK_USB_HOST_BASE 0x101C0000
++
++#define RALINK_MCNT_CFG 0xB0000D00
++#define RALINK_COMPARE 0xB0000D04
++#define RALINK_COUNT 0xB0000D08
++
++//Interrupt Controller
++#define RALINK_INTCTL_SYSCTL (1<<0)
++#define RALINK_INTCTL_TIMER0 (1<<1)
++#define RALINK_INTCTL_WDTIMER (1<<2)
++#define RALINK_INTCTL_ILL_ACCESS (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UART (1<<5)
++#define RALINK_INTCTL_PIO (1<<6)
++#define RALINK_INTCTL_DMA (1<<7)
++#define RALINK_INTCTL_PC (1<<9)
++#define RALINK_INTCTL_I2S (1<<10)
++#define RALINK_INTCTL_UARTLITE (1<<12)
++#define RALINK_INTCTL_ESW (1<<17)
++#define RALINK_INTCTL_OTG (1<<18)
++#define RALINK_INTCTL_GLOBAL (1<<31)
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_UART_RST (1<<12)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UARTL_RST (1<<19)
++#define RALINK_WLAN_RST (1<<20)
++#define RALINK_FE_RST (1<<21)
++#define RALINK_UHST_RST (1<<22)
++#define RALINK_ESW_RST (1<<23)
++#define RALINK_EPHY_RST (1<<24)
++#define RALINK_UDEV_RST (1<<25)
++
++
++//Clock Conf Register
++#define RALINK_UPHY1_CLK_EN (1<<20)
++#define RALINK_UPHY0_CLK_EN (1<<18)
++#define RALINK_GE1_CLK_EN (1<<16)
++
++
++#elif defined (CONFIG_RALINK_RT5350)
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_TIMER_BASE 0xB0000100
++#define RALINK_INTCL_BASE 0xB0000200
++#define RALINK_MEMCTRL_BASE 0xB0000300
++#define RALINK_UART_BASE 0x10000500
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_I2C_BASE 0xB0000900
++#define RALINK_I2S_BASE 0xB0000A00
++#define RALINK_SPI_BASE 0xB0000B00
++#define RALINK_UART_LITE_BASE 0x10000C00
++#define RALINK_PCM_BASE 0xB0002000
++#define RALINK_GDMA_BASE 0xB0002800
++#define RALINK_FRAME_ENGINE_BASE 0xB0100000
++#define RALINK_ETH_SW_BASE 0xB0110000
++#define RALINK_USB_DEV_BASE 0x10120000
++#define RALINK_11N_MAC_BASE 0xB0180000
++#define RALINK_USB_HOST_BASE 0x101C0000
++
++#define RALINK_MCNT_CFG 0xB0000D00
++#define RALINK_COMPARE 0xB0000D04
++#define RALINK_COUNT 0xB0000D08
++
++//Interrupt Controller
++#define RALINK_INTCTL_SYSCTL (1<<0)
++#define RALINK_INTCTL_TIMER0 (1<<1)
++#define RALINK_INTCTL_WDTIMER (1<<2)
++#define RALINK_INTCTL_ILL_ACCESS (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UART (1<<5)
++#define RALINK_INTCTL_PIO (1<<6)
++#define RALINK_INTCTL_DMA (1<<7)
++#define RALINK_INTCTL_PC (1<<9)
++#define RALINK_INTCTL_I2S (1<<10)
++#define RALINK_INTCTL_UARTLITE (1<<12)
++#define RALINK_INTCTL_ESW (1<<17)
++#define RALINK_INTCTL_USB_HOST (1<<18)
++#define RALINK_INTCTL_USB_DEV (1<<19)
++#define RALINK_INTCTL_GLOBAL (1<<31)
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_UART_RST (1<<12)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UARTL_RST (1<<19)
++#define RALINK_WLAN_RST (1<<20)
++#define RALINK_FE_RST (1<<21)
++#define RALINK_UHST_RST (1<<22)
++#define RALINK_ESW_RST (1<<23)
++#define RALINK_EPHY_RST (1<<24)
++#define RALINK_UDEV_RST (1<<25)
++#define RALINK_MIPSC_RST (1<<28)
++
++//Clock Conf Register
++#define RALINK_UPHY0_CLK_EN (1<<18)
++#define RALINK_GE1_CLK_EN (1<<16)
++
++#elif defined (CONFIG_RALINK_RT2883)
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_TIMER_BASE 0xB0000100
++#define RALINK_INTCL_BASE 0xB0000200
++#define RALINK_MEMCTRL_BASE 0xB0000300
++#define RALINK_PCM_BASE 0xB0000400
++#define RALINK_UART_BASE 0x10000500
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_GDMA_BASE 0xB0000700
++#define RALINK_NAND_CTRL_BASE 0xB0000800
++#define RALINK_I2C_BASE 0xB0000900
++#define RALINK_I2S_BASE 0xB0000A00
++#define RALINK_SPI_BASE 0xB0000B00
++#define RALINK_UART_LITE_BASE 0x10000C00
++#define RALINK_FRAME_ENGINE_BASE 0xB0100000
++#define RALINK_PCI_BASE 0xB0140000
++#define RALINK_11N_MAC_BASE 0xB0180000
++#define RALINK_USB_OTG_BASE 0x101C0000
++
++//Interrupt Controller
++#define RALINK_INTCTL_SYSCTL (1<<0)
++#define RALINK_INTCTL_TIMER0 (1<<1)
++#define RALINK_INTCTL_WDTIMER (1<<2)
++#define RALINK_INTCTL_ILL_ACCESS (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UART (1<<5)
++#define RALINK_INTCTL_PIO (1<<6)
++#define RALINK_INTCTL_DMA (1<<7)
++#define RALINK_INTCTL_NAND (1<<8)
++#define RALINK_INTCTL_PC (1<<9)
++#define RALINK_INTCTL_I2S (1<<10)
++#define RALINK_INTCTL_UARTLITE (1<<12)
++#define RALINK_INTCTL_OTG (1<<18)
++#define RALINK_INTCTL_OTG_IRQN 18
++#define RALINK_INTCTL_GLOBAL (1<<31)
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_CPU_RST (1<<1)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_UART_RST (1<<12)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UARTL_RST (1<<19)
++#define RALINK_WLAN_RST (1<<20)
++#define RALINK_FE_RST (1<<21)
++#define RALINK_OTG_RST (1<<22)
++#define RALINK_PCIE_RST (1<<23)
++
++#elif defined (CONFIG_RALINK_RT3883)
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_TIMER_BASE 0xB0000100
++#define RALINK_INTCL_BASE 0xB0000200
++#define RALINK_MEMCTRL_BASE 0xB0000300
++#define RALINK_UART_BASE 0x10000500
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_NOR_CTRL_BASE 0xB0000700
++#define RALINK_NAND_CTRL_BASE 0xB0000810
++#define RALINK_I2C_BASE 0xB0000900
++#define RALINK_I2S_BASE 0xB0000A00
++#define RALINK_SPI_BASE 0xB0000B00
++#define RALINK_UART_LITE_BASE 0x10000C00
++#define RALINK_PCM_BASE 0xB0002000
++#define RALINK_GDMA_BASE 0xB0002800
++#define RALINK_CODEC1_BASE 0xB0003000
++#define RALINK_CODEC2_BASE 0xB0003800
++#define RALINK_FRAME_ENGINE_BASE 0xB0100000
++#define RALINK_USB_DEV_BASE 0x10120000
++#define RALINK_PCI_BASE 0xB0140000
++#define RALINK_11N_MAC_BASE 0xB0180000
++#define RALINK_USB_HOST_BASE 0x101C0000
++#define RALINK_PCIE_BASE 0xB0200000
++
++//Interrupt Controller
++#define RALINK_INTCTL_SYSCTL (1<<0)
++#define RALINK_INTCTL_TIMER0 (1<<1)
++#define RALINK_INTCTL_WDTIMER (1<<2)
++#define RALINK_INTCTL_ILL_ACCESS (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UART (1<<5)
++#define RALINK_INTCTL_PIO (1<<6)
++#define RALINK_INTCTL_DMA (1<<7)
++#define RALINK_INTCTL_NAND (1<<8)
++#define RALINK_INTCTL_PC (1<<9)
++#define RALINK_INTCTL_I2S (1<<10)
++#define RALINK_INTCTL_UARTLITE (1<<12)
++#define RALINK_INTCTL_UHST (1<<18)
++#define RALINK_INTCTL_UDEV (1<<19)
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_UART_RST (1<<12)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_NAND_RST (1<<15)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UARTL_RST (1<<19)
++#define RALINK_WLAN_RST (1<<20)
++#define RALINK_FE_RST (1<<21)
++#define RALINK_UHST_RST (1<<22)
++#define RALINK_PCIE_RST (1<<23)
++#define RALINK_PCI_RST (1<<24)
++#define RALINK_UDEV_RST (1<<25)
++#define RALINK_FLASH_RST (1<<26)
++
++//Clock Conf Register
++#define RALINK_UPHY1_CLK_EN (1<<20)
++#define RALINK_UPHY0_CLK_EN (1<<18)
++#define RALINK_GE1_CLK_EN (1<<16)
++
++#elif defined (CONFIG_RALINK_RT6855)
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_TIMER_BASE 0xB0000100
++#define RALINK_INTCL_BASE 0xB0000200
++#define RALINK_MEMCTRL_BASE 0xB0000300
++#define RALINK_UART_BASE 0x10000500
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_I2C_BASE 0xB0000900
++#define RALINK_I2S_BASE 0xB0000A00
++#define RALINK_SPI_BASE 0xB0000B00
++#define RALINK_NAND_CTRL_BASE 0xB0000800
++#define RALINK_UART_LITE_BASE 0x10000C00
++#define RALINK_PCM_BASE 0xB0002000
++#define RALINK_GDMA_BASE 0xB0002800
++#define RALINK_FRAME_ENGINE_BASE 0xB0100000
++#define RALINK_ETH_SW_BASE 0xB0110000
++#define RALINK_PCI_BASE 0xB0140000
++#define RALINK_USB_DEV_BASE 0x10120000
++#define RALINK_11N_MAC_BASE 0xB0180000
++#define RALINK_USB_HOST_BASE 0x101C0000
++
++#define RALINK_MCNT_CFG 0xB0000D00
++#define RALINK_COMPARE 0xB0000D04
++#define RALINK_COUNT 0xB0000D08
++
++//Interrupt Controller
++#define RALINK_INTCTL_SYSCTL (1<<0)
++#define RALINK_INTCTL_TIMER0 (1<<1)
++#define RALINK_INTCTL_WDTIMER (1<<2)
++#define RALINK_INTCTL_ILL_ACCESS (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UART (1<<5)
++#define RALINK_INTCTL_PIO (1<<6)
++#define RALINK_INTCTL_DMA (1<<7)
++#define RALINK_INTCTL_PC (1<<9)
++#define RALINK_INTCTL_I2S (1<<10)
++#define RALINK_INTCTL_UARTLITE (1<<12)
++#define RALINK_INTCTL_ESW (1<<17)
++#define RALINK_INTCTL_OTG (1<<18)
++#define RALINK_INTCTL_GLOBAL (1<<31)
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_UART_RST (1<<12)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UARTL_RST (1<<19)
++#define RALINK_FE_RST (1<<21)
++#define RALINK_UHST_RST (1<<22)
++#define RALINK_ESW_RST (1<<23)
++#define RALINK_EPHY_RST (1<<24)
++#define RALINK_UDEV_RST (1<<25)
++#define RALINK_PCIE0_RST (1<<26)
++#define RALINK_PCIE1_RST (1<<27)
++
++//Clock Conf Register
++#define RALINK_UPHY0_CLK_EN (1<<25)
++#define RALINK_PCIE0_CLK_EN (1<<26)
++#define RALINK_PCIE1_CLK_EN (1<<27)
++
++
++#elif defined (CONFIG_RALINK_MT7620)
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_TIMER_BASE 0xB0000100
++#define RALINK_INTCL_BASE 0xB0000200
++#define RALINK_MEMCTRL_BASE 0xB0000300
++#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
++#define RALINK_UART_BASE 0x10000500
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_NAND_CTRL_BASE 0xB0000810
++#define RALINK_I2C_BASE 0xB0000900
++#define RALINK_I2S_BASE 0xB0000A00
++#define RALINK_SPI_BASE 0xB0000B00
++#define RALINK_UART_LITE_BASE 0x10000C00
++#define RALINK_MIPS_CNT_BASE 0x10000D00
++#define RALINK_PCM_BASE 0xB0002000
++#define RALINK_GDMA_BASE 0xB0002800
++#define RALINK_CRYPTO_ENGINE_BASE 0xB0004000
++#define RALINK_FRAME_ENGINE_BASE 0xB0100000
++#define RALINK_PPE_BASE 0xB0100C00
++#define RALINK_ETH_SW_BASE 0xB0110000
++#define RALINK_USB_DEV_BASE 0x10120000
++#define RALINK_MSDC_BASE 0xB0130000
++#define RALINK_PCI_BASE 0xB0140000
++#define RALINK_11N_MAC_BASE 0xB0180000
++#define RALINK_USB_HOST_BASE 0x101C0000
++
++#define RALINK_MCNT_CFG 0xB0000D00
++#define RALINK_COMPARE 0xB0000D04
++#define RALINK_COUNT 0xB0000D08
++
++//Interrupt Controller
++#define RALINK_INTCTL_SYSCTL (1<<0)
++#define RALINK_INTCTL_TIMER0 (1<<1)
++#define RALINK_INTCTL_WDTIMER (1<<2)
++#define RALINK_INTCTL_ILL_ACCESS (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UART (1<<5)
++#define RALINK_INTCTL_PIO (1<<6)
++#define RALINK_INTCTL_DMA (1<<7)
++#define RALINK_INTCTL_PC (1<<9)
++#define RALINK_INTCTL_I2S (1<<10)
++#define RALINK_INTCTL_SPI (1<<11)
++#define RALINK_INTCTL_UARTLITE (1<<12)
++#define RALINK_INTCTL_CRYPTO (1<<13)
++#define RALINK_INTCTL_ESW (1<<17)
++#define RALINK_INTCTL_UHST (1<<18)
++#define RALINK_INTCTL_UDEV (1<<19)
++#define RALINK_INTCTL_GLOBAL (1<<31)
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_UART_RST (1<<12)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UARTL_RST (1<<19)
++#define RALINK_FE_RST (1<<21)
++#define RALINK_UHST_RST (1<<22)
++#define RALINK_ESW_RST (1<<23)
++#define RALINK_EPHY_RST (1<<24)
++#define RALINK_UDEV_RST (1<<25)
++#define RALINK_PCIE0_RST (1<<26)
++#define RALINK_PCIE1_RST (1<<27)
++#define RALINK_MIPS_CNT_RST (1<<28)
++#define RALINK_CRYPTO_RST (1<<29)
++
++//Clock Conf Register
++#define RALINK_UPHY0_CLK_EN (1<<25)
++#define RALINK_UPHY1_CLK_EN (1<<22)
++#define RALINK_PCIE0_CLK_EN (1<<26)
++#define RALINK_PCIE1_CLK_EN (1<<27)
++
++//CPU PLL CFG Register
++#define CPLL_SW_CONFIG (0x1UL << 31)
++#define CPLL_MULT_RATIO_SHIFT 16
++#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
++#define CPLL_DIV_RATIO_SHIFT 10
++#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
++#define BASE_CLOCK 40 /* Mhz */
++
++#elif defined (CONFIG_RALINK_MT7621)
++
++#define RALINK_SYSCTL_BASE 0xBE000000
++#define RALINK_TIMER_BASE 0xBE000100
++#define RALINK_INTCL_BASE 0xBE000200
++#define RALINK_RBUS_MATRIXCTL_BASE 0xBE000400
++#define RALINK_MIPS_CNT_BASE 0x1E000500
++#define RALINK_PIO_BASE 0xBE000600
++#define RALINK_SPDIF_BASE 0xBE000700
++#define RALINK_I2C_BASE 0xBE000900
++#define RALINK_I2S_BASE 0xBE000A00
++#define RALINK_SPI_BASE 0xBE000B00
++#define RALINK_UART_LITE1_BASE 0x1E000C00
++#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
++#define RALINK_UART_LITE2_BASE 0x1E000D00
++#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
++#define RALINK_UART_LITE3_BASE 0x1E000E00
++#define RALINK_ANA_CTRL_BASE 0xBE000F00
++#define RALINK_PCM_BASE 0xBE002000
++#define RALINK_GDMA_BASE 0xBE002800
++#define RALINK_NAND_CTRL_BASE 0xBE003000
++#define RALINK_NANDECC_CTRL_BASE 0xBE003800
++#define RALINK_CRYPTO_ENGINE_BASE 0xBE004000
++#define RALINK_MEMCTRL_BASE 0xBE005000
++#define RALINK_EXT_MC_ARB_BASE 0xBE006000
++#define RALINK_HS_DMA_BASE 0xBE007000
++#define RALINK_FRAME_ENGINE_BASE 0xBE100000
++#define RALINK_PPE_BASE 0xBE100C00
++#define RALINK_ETH_SW_BASE 0xBE110000
++#define RALINK_ROM_BASE 0xBE118000
++#define RALINK_MSDC_BASE 0xBE130000
++#define RALINK_PCI_BASE 0xBE140000
++#define RALINK_USB_HOST_BASE 0x1E1C0000
++#define RALINK_11N_MAC_BASE 0xBE180000 //Unused
++
++#define RALINK_MCNT_CFG 0xBE000500
++#define RALINK_COMPARE 0xBE000504
++#define RALINK_COUNT 0xBE000508
++
++//Interrupt Controller
++#define RALINK_INTCTL_FE (1<<3)
++#define RALINK_INTCTL_PCIE0 (1<<4)
++#define RALINK_INTCTL_SYSCTL (1<<6)
++#define RALINK_INTCTL_I2C (1<<8)
++#define RALINK_INTCTL_DRAMC (1<<9)
++#define RALINK_INTCTL_PCM (1<<10)
++#define RALINK_INTCTL_HSDMA (1<<11)
++#define RALINK_INTCTL_PIO (1<<12)
++#define RALINK_INTCTL_DMA (1<<13)
++#define RALINK_INTCTL_NFI (1<<14)
++#define RALINK_INTCTL_NFIECC (1<<15)
++#define RALINK_INTCTL_I2S (1<<16)
++#define RALINK_INTCTL_SPI (1<<17)
++#define RALINK_INTCTL_SPDIF (1<<18)
++#define RALINK_INTCTL_CRYPTO (1<<19)
++#define RALINK_INTCTL_SDXC (1<<20)
++#define RALINK_INTCTL_PCTRL (1<<21)
++#define RALINK_INTCTL_USB (1<<22)
++#define RALINK_INTCTL_SWITCH (1<<23)
++#define RALINK_INTCTL_PCIE1 (1<<24)
++#define RALINK_INTCTL_PCIE2 (1<<25)
++#define RALINK_INTCTL_UART1 (1<<26)
++#define RALINK_INTCTL_UART2 (1<<27)
++#define RALINK_INTCTL_UART3 (1<<28)
++#define RALINK_INTCTL_WDTIMER (1<<29)
++#define RALINK_INTCTL_TIMER0 (1<<30)
++#define RALINK_INTCTL_TIMER1 (1<<31)
++
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_MCM_RST (1<<1)
++#define RALINK_HSDMA_RST (1<<2)
++#define RALINK_FE_RST (1<<6)
++#define RALINK_SPDIF_RST (1<<7)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_NAND_RST (1<<15)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UART1_RST (1<<19)
++#define RALINK_UART2_RST (1<<20)
++#define RALINK_UART3_RST (1<<21)
++#define RALINK_ETH_RST (1<<23)
++#define RALINK_PCIE0_RST (1<<24)
++#define RALINK_PCIE1_RST (1<<25)
++#define RALINK_PCIE2_RST (1<<26)
++#define RALINK_AUX_STCK_RST (1<<28)
++#define RALINK_CRYPTO_RST (1<<29)
++#define RALINK_SDXC_RST (1<<30)
++#define RALINK_PPE_RST (1<<31)
++
++//Clock Conf Register
++#define RALINK_PCIE0_CLK_EN (1<<24)
++#define RALINK_PCIE1_CLK_EN (1<<25)
++#define RALINK_PCIE2_CLK_EN (1<<26)
++//#define RALINK_UPHY0_CLK_EN (1<<27)
++//#define RALINK_UPHY1_CLK_EN (1<<28)
++
++//CPU PLL CFG Register
++#define CPLL_SW_CONFIG (0x1UL << 31)
++#define CPLL_MULT_RATIO_SHIFT 16
++#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
++#define CPLL_DIV_RATIO_SHIFT 10
++#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
++#define BASE_CLOCK 40 /* Mhz */
++
++#define RALINK_TESTSTAT 0xBE000018
++#define RALINK_TESTSTAT2 0xBE00001C
++
++#elif defined (CONFIG_RALINK_MT7628)
++
++#define RALINK_SYSCTL_BASE 0xB0000000
++#define RALINK_TIMER_BASE 0xB0000100
++#define RALINK_INTCL_BASE 0xB0000200
++#define RALINK_MEMCTRL_BASE 0xB0000300
++#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
++#define RALINK_MIPS_CNT_BASE 0x10000500
++#define RALINK_PIO_BASE 0xB0000600
++#define RALINK_SPI_SLAVE_BASE 0xB0000700
++#define RALINK_I2C_BASE 0xB0000900
++#define RALINK_I2S_BASE 0xB0000A00
++#define RALINK_SPI_BASE 0xB0000B00
++#define RALINK_UART_LITE1_BASE 0x10000C00
++#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
++#define RALINK_UART_LITE2_BASE 0x10000D00
++#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
++#define RALINK_UART_LITE3_BASE 0x10000E00
++#define RALINK_PCM_BASE 0xB0002000
++#define RALINK_GDMA_BASE 0xB0002800
++#define RALINK_AES_ENGINE_BASE 0xB0004000
++#define RALINK_CRYPTO_ENGINE_BASE RALINK_AES_ENGINE_BASE
++#define RALINK_FRAME_ENGINE_BASE 0xB0100000
++#define RALINK_PPE_BASE 0xB0100C00
++#define RALINK_ETH_SW_BASE 0xB0110000
++#define RALINK_USB_DEV_BASE 0xB0120000
++#define RALINK_MSDC_BASE 0xB0130000
++#define RALINK_PCI_BASE 0xB0140000
++#define RALINK_11N_MAC_BASE 0xB0180000
++#define RALINK_USB_HOST_BASE 0x101C0000
++
++#define RALINK_MCNT_CFG 0xB0000500
++#define RALINK_COMPARE 0xB0000504
++#define RALINK_COUNT 0xB0000508
++
++
++//Interrupt Controller
++#define RALINK_INTCTL_SYSCTL (1<<0)
++#define RALINK_INTCTL_TIMER0 (1<<1)
++#define RALINK_INTCTL_WDTIMER (1<<2)
++#define RALINK_INTCTL_ILL_ACCESS (1<<3)
++#define RALINK_INTCTL_PCM (1<<4)
++#define RALINK_INTCTL_UART (1<<5)
++#define RALINK_INTCTL_PIO (1<<6)
++#define RALINK_INTCTL_DMA (1<<7)
++#define RALINK_INTCTL_PC (1<<9)
++#define RALINK_INTCTL_I2S (1<<10)
++#define RALINK_INTCTL_SPI (1<<11)
++#define RALINK_INTCTL_UARTLITE (1<<12)
++#define RALINK_INTCTL_CRYPTO (1<<13)
++#define RALINK_INTCTL_ESW (1<<17)
++#define RALINK_INTCTL_UHST (1<<18)
++#define RALINK_INTCTL_UDEV (1<<19)
++#define RALINK_INTCTL_GLOBAL (1<<31)
++
++//Reset Control Register
++#define RALINK_SYS_RST (1<<0)
++#define RALINK_TIMER_RST (1<<8)
++#define RALINK_INTC_RST (1<<9)
++#define RALINK_MC_RST (1<<10)
++#define RALINK_PCM_RST (1<<11)
++#define RALINK_UART_RST (1<<12)
++#define RALINK_PIO_RST (1<<13)
++#define RALINK_DMA_RST (1<<14)
++#define RALINK_I2C_RST (1<<16)
++#define RALINK_I2S_RST (1<<17)
++#define RALINK_SPI_RST (1<<18)
++#define RALINK_UARTL_RST (1<<19)
++#define RALINK_FE_RST (1<<21)
++#define RALINK_UHST_RST (1<<22)
++#define RALINK_ESW_RST (1<<23)
++#define RALINK_EPHY_RST (1<<24)
++#define RALINK_UDEV_RST (1<<25)
++#define RALINK_PCIE0_RST (1<<26)
++#define RALINK_PCIE1_RST (1<<27)
++#define RALINK_MIPS_CNT_RST (1<<28)
++#define RALINK_CRYPTO_RST (1<<29)
++
++//Clock Conf Register
++#define RALINK_UPHY0_CLK_EN (1<<25)
++#define RALINK_UPHY1_CLK_EN (1<<22)
++#define RALINK_PCIE0_CLK_EN (1<<26)
++#define RALINK_PCIE1_CLK_EN (1<<27)
++
++//CPU PLL CFG Register
++#define CPLL_SW_CONFIG (0x1UL << 31)
++#define CPLL_MULT_RATIO_SHIFT 16
++#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
++#define CPLL_DIV_RATIO_SHIFT 10
++#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
++#define BASE_CLOCK 40 /* Mhz */
++
++#endif
++#endif
+--- /dev/null
++++ b/arch/mips/include/asm/rt2880/serial_rt2880.h
+@@ -0,0 +1,443 @@
++/**************************************************************************
++ *
++ * BRIEF MODULE DESCRIPTION
++ * serial port definition for Ralink RT2880 solution
++ *
++ * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ **************************************************************************
++ * May 2007 Bruce Chang
++ *
++ * Initial Release
++ *
++ *
++ *
++ **************************************************************************
++ */
++
++#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
++#define RT2880_UART_RBR_OFFSET 0x00
++#define RT2880_UART_TBR_OFFSET 0x00
++#define RT2880_UART_IER_OFFSET 0x04
++#define RT2880_UART_IIR_OFFSET 0x08
++#define RT2880_UART_FCR_OFFSET 0x08
++#define RT2880_UART_LCR_OFFSET 0x0C
++#define RT2880_UART_MCR_OFFSET 0x10
++#define RT2880_UART_LSR_OFFSET 0x14
++#define RT2880_UART_DLL_OFFSET 0x00
++#define RT2880_UART_DLM_OFFSET 0x04
++#else
++#define RT2880_UART_RBR_OFFSET 0x00
++#define RT2880_UART_TBR_OFFSET 0x04
++#define RT2880_UART_IER_OFFSET 0x08
++#define RT2880_UART_IIR_OFFSET 0x0C
++#define RT2880_UART_FCR_OFFSET 0x10
++#define RT2880_UART_LCR_OFFSET 0x14
++#define RT2880_UART_MCR_OFFSET 0x18
++#define RT2880_UART_LSR_OFFSET 0x1C
++#define RT2880_UART_DLL_OFFSET 0x2C
++#define RT2880_UART_DLM_OFFSET 0x30
++#endif
++
++#define RBR(x) *(volatile u32 *)((x)+RT2880_UART_RBR_OFFSET)
++#define TBR(x) *(volatile u32 *)((x)+RT2880_UART_TBR_OFFSET)
++#define IER(x) *(volatile u32 *)((x)+RT2880_UART_IER_OFFSET)
++#define IIR(x) *(volatile u32 *)((x)+RT2880_UART_IIR_OFFSET)
++#define FCR(x) *(volatile u32 *)((x)+RT2880_UART_FCR_OFFSET)
++#define LCR(x) *(volatile u32 *)((x)+RT2880_UART_LCR_OFFSET)
++#define MCR(x) *(volatile u32 *)((x)+RT2880_UART_MCR_OFFSET)
++#define LSR(x) *(volatile u32 *)((x)+RT2880_UART_LSR_OFFSET)
++#define DLL(x) *(volatile u32 *)((x)+RT2880_UART_DLL_OFFSET)
++#define DLM(x) *(volatile u32 *)((x)+RT2880_UART_DLM_OFFSET)
++
++
++#if defined (CONFIG_RALINK_RT2880) || \
++ defined (CONFIG_RALINK_RT2883) || \
++ defined (CONFIG_RALINK_RT3883) || \
++ defined (CONFIG_RALINK_RT3352) || \
++ defined (CONFIG_RALINK_RT5350) || \
++ defined (CONFIG_RALINK_RT6855) || \
++ defined (CONFIG_RALINK_MT7620) || \
++ defined (CONFIG_RALINK_RT3052)
++
++#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
++
++#define UART_TX 4 /* Out: Transmit buffer (DLAB=0) */
++#define UART_TRG 4 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
++ * In: Fifo count
++ * Out: Fifo custom trigger levels
++ * XR16C85x only
++ */
++
++#define UART_IER 8 /* Out: Interrupt Enable Register */
++#define UART_FCTR 8 /* (LCR=BF) Feature Control Register
++ * XR16C85x only
++ */
++
++#define UART_IIR 12 /* In: Interrupt ID Register */
++#define UART_EFR 12 /* I/O: Extended Features Register */
++ /* (DLAB=1, 16C660 only) */
++
++#define UART_FCR 16 /* Out: FIFO Control Register */
++#define UART_LCR 20 /* Out: Line Control Register */
++#define UART_MCR 24 /* Out: Modem Control Register */
++#define UART_LSR 28 /* In: Line Status Register */
++#define UART_MSR 32 /* In: Modem Status Register */
++#define UART_SCR 36 /* I/O: Scratch Register */
++#define UART_DLL 44 /* Out: Divisor Latch Low (DLAB=1) */
++/* Since surfboard uart cannot be accessed by byte, using UART_DLM will cause
++ * unpredictable values to be written to the Divisor Latch
++ */
++#define UART_DLM 48 /* Out: Divisor Latch High (DLAB=1) */
++
++#else
++
++#define UART_RX 0 /* In: Receive buffer */
++#define UART_TX 0 /* Out: Transmit buffer */
++#define UART_DLL 0 /* Out: Divisor Latch Low */
++#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
++ * In: Fifo count
++ * Out: Fifo custom trigger levels */
++
++#define UART_DLM 4 /* Out: Divisor Latch High */
++#define UART_IER 4 /* Out: Interrupt Enable Register */
++#define UART_FCTR 4 /* Feature Control Register */
++
++#define UART_IIR 8 /* In: Interrupt ID Register */
++#define UART_FCR 8 /* Out: FIFO Control Register */
++#define UART_EFR 8 /* I/O: Extended Features Register */
++
++#define UART_LCR 12 /* Out: Line Control Register */
++#define UART_MCR 16 /* Out: Modem Control Register */
++#define UART_LSR 20 /* In: Line Status Register */
++#define UART_MSR 24 /* In: Modem Status Register */
++#define UART_SCR 28 /* I/O: Scratch Register */
++#define UART_EMSR 28 /* Extended Mode Select Register */
++
++#endif
++/*
++ * DLAB=0
++ */
++//#define UART_IER 1 /* Out: Interrupt Enable Register */
++#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
++#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
++#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
++#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
++/*
++ * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1
++ */
++#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
++
++//#define UART_IIR 2 /* In: Interrupt ID Register */
++#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
++#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
++#define UART_IIR_MSI 0x00 /* Modem status interrupt */
++#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
++#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
++#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
++
++//#define UART_FCR 2 /* Out: FIFO Control Register */
++#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
++#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
++#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
++#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
++/*
++ * Note: The FIFO trigger levels are chip specific:
++ * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
++ * PC16550D: 1 4 8 14 xx xx xx xx
++ * TI16C550A: 1 4 8 14 xx xx xx xx
++ * TI16C550C: 1 4 8 14 xx xx xx xx
++ * ST16C550: 1 4 8 14 xx xx xx xx
++ * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2
++ * NS16C552: 1 4 8 14 xx xx xx xx
++ * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
++ * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
++ * TI16C752: 8 16 56 60 8 16 32 56
++ */
++#define UART_FCR_R_TRIG_00 0x00
++#define UART_FCR_R_TRIG_01 0x40
++#define UART_FCR_R_TRIG_10 0x80
++#define UART_FCR_R_TRIG_11 0xc0
++#define UART_FCR_T_TRIG_00 0x00
++#define UART_FCR_T_TRIG_01 0x10
++#define UART_FCR_T_TRIG_10 0x20
++#define UART_FCR_T_TRIG_11 0x30
++
++#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
++#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
++#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
++#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
++#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
++/* 16650 definitions */
++#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
++#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
++#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
++#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
++#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
++#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
++#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
++#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
++#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */
++
++//#define UART_LCR 3 /* Out: Line Control Register */
++/*
++ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
++ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
++ */
++#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
++#define UART_LCR_SBC 0x40 /* Set break control */
++#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
++#define UART_LCR_EPAR 0x10 /* Even parity select */
++#define UART_LCR_PARITY 0x08 /* Parity Enable */
++#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */
++#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
++#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
++#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
++#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
++
++//#define UART_MCR 4 /* Out: Modem Control Register */
++#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
++#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
++#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
++#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
++#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
++#define UART_MCR_OUT2 0x08 /* Out2 complement */
++#define UART_MCR_OUT1 0x04 /* Out1 complement */
++#define UART_MCR_RTS 0x02 /* RTS complement */
++#define UART_MCR_DTR 0x01 /* DTR complement */
++
++//#define UART_LSR 5 /* In: Line Status Register */
++#define UART_LSR_TEMT 0x40 /* Transmitter empty */
++#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
++#define UART_LSR_BI 0x10 /* Break interrupt indicator */
++#define UART_LSR_FE 0x08 /* Frame error indicator */
++#define UART_LSR_PE 0x04 /* Parity error indicator */
++#define UART_LSR_OE 0x02 /* Overrun error indicator */
++#define UART_LSR_DR 0x01 /* Receiver data ready */
++
++//#define UART_MSR 6 /* In: Modem Status Register */
++#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
++#define UART_MSR_RI 0x40 /* Ring Indicator */
++#define UART_MSR_DSR 0x20 /* Data Set Ready */
++#define UART_MSR_CTS 0x10 /* Clear to Send */
++#define UART_MSR_DDCD 0x08 /* Delta DCD */
++#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
++#define UART_MSR_DDSR 0x02 /* Delta DSR */
++#define UART_MSR_DCTS 0x01 /* Delta CTS */
++#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
++
++//#define UART_SCR 7 /* I/O: Scratch Register */
++
++/*
++ * DLAB=1
++ */
++//#define UART_DLL 0 /* Out: Divisor Latch Low */
++//#define UART_DLM 1 /* Out: Divisor Latch High */
++
++/*
++ * LCR=0xBF (or DLAB=1 for 16C660)
++ */
++//#define UART_EFR 2 /* I/O: Extended Features Register */
++#define UART_EFR_CTS 0x80 /* CTS flow control */
++#define UART_EFR_RTS 0x40 /* RTS flow control */
++#define UART_EFR_SCD 0x20 /* Special character detect */
++#define UART_EFR_ECB 0x10 /* Enhanced control bit */
++/*
++ * the low four bits control software flow control
++ */
++
++/*
++ * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
++ */
++#define UART_XON1 4 /* I/O: Xon character 1 */
++#define UART_XON2 5 /* I/O: Xon character 2 */
++#define UART_XOFF1 6 /* I/O: Xoff character 1 */
++#define UART_XOFF2 7 /* I/O: Xoff character 2 */
++
++/*
++ * EFR[4]=1 MCR[6]=1, TI16C752
++ */
++#define UART_TI752_TCR 6 /* I/O: transmission control register */
++#define UART_TI752_TLR 7 /* I/O: trigger level register */
++
++/*
++ * LCR=0xBF, XR16C85x
++ */
++//#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
++// * In: Fifo count
++// * Out: Fifo custom trigger levels */
++/*
++ * These are the definitions for the Programmable Trigger Register
++ */
++#define UART_TRG_1 0x01
++#define UART_TRG_4 0x04
++#define UART_TRG_8 0x08
++#define UART_TRG_16 0x10
++#define UART_TRG_32 0x20
++#define UART_TRG_64 0x40
++#define UART_TRG_96 0x60
++#define UART_TRG_120 0x78
++#define UART_TRG_128 0x80
++
++//#define UART_FCTR 1 /* Feature Control Register */
++#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
++#define UART_FCTR_RTS_4DELAY 0x01
++#define UART_FCTR_RTS_6DELAY 0x02
++#define UART_FCTR_RTS_8DELAY 0x03
++#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */
++#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
++#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
++#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
++#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
++#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
++#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
++#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
++#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
++
++/*
++ * LCR=0xBF, FCTR[6]=1
++ */
++//#define UART_EMSR 7 /* Extended Mode Select Register */
++#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
++#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */
++
++/*
++ * The Intel XScale on-chip UARTs define these bits
++ */
++#define UART_IER_DMAE 0x80 /* DMA Requests Enable */
++#define UART_IER_UUE 0x40 /* UART Unit Enable */
++#define UART_IER_NRZE 0x20 /* NRZ coding Enable */
++#define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
++
++#define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */
++
++#define UART_FCR_PXAR1 0x00 /* receive FIFO treshold = 1 */
++#define UART_FCR_PXAR8 0x40 /* receive FIFO treshold = 8 */
++#define UART_FCR_PXAR16 0x80 /* receive FIFO treshold = 16 */
++#define UART_FCR_PXAR32 0xc0 /* receive FIFO treshold = 32 */
++
++
++
++
++/*
++ * These register definitions are for the 16C950
++ */
++#define UART_ASR 0x01 /* Additional Status Register */
++#define UART_RFL 0x03 /* Receiver FIFO level */
++#define UART_TFL 0x04 /* Transmitter FIFO level */
++#define UART_ICR 0x05 /* Index Control Register */
++
++/* The 16950 ICR registers */
++#define UART_ACR 0x00 /* Additional Control Register */
++#define UART_CPR 0x01 /* Clock Prescalar Register */
++#define UART_TCR 0x02 /* Times Clock Register */
++#define UART_CKS 0x03 /* Clock Select Register */
++#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
++#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
++#define UART_FCL 0x06 /* Flow Control Level Lower */
++#define UART_FCH 0x07 /* Flow Control Level Higher */
++#define UART_ID1 0x08 /* ID #1 */
++#define UART_ID2 0x09 /* ID #2 */
++#define UART_ID3 0x0A /* ID #3 */
++#define UART_REV 0x0B /* Revision */
++#define UART_CSR 0x0C /* Channel Software Reset */
++#define UART_NMR 0x0D /* Nine-bit Mode Register */
++#define UART_CTR 0xFF
++
++/*
++ * The 16C950 Additional Control Reigster
++ */
++#define UART_ACR_RXDIS 0x01 /* Receiver disable */
++#define UART_ACR_TXDIS 0x02 /* Receiver disable */
++#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
++#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
++#define UART_ACR_ICRRD 0x40 /* ICR Read enable */
++#define UART_ACR_ASREN 0x80 /* Additional status enable */
++
++
++
++/*
++ * These definitions are for the RSA-DV II/S card, from
++ *
++ * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
++ */
++
++#define UART_RSA_BASE (-8)
++
++#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
++
++#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
++#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
++#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
++#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
++
++#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
++
++#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
++#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
++#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
++#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
++#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
++
++#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
++
++#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
++#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
++#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
++#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
++#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
++#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
++#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
++#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
++
++#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
++
++#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
++
++#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
++
++#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
++
++/*
++ * The RSA DSV/II board has two fixed clock frequencies. One is the
++ * standard rate, and the other is 8 times faster.
++ */
++#define SERIAL_RSA_BAUD_BASE (921600)
++#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
++
++/*
++ * Extra serial register definitions for the internal UARTs
++ * in TI OMAP processors.
++ */
++#define UART_OMAP_MDR1 0x08 /* Mode definition register */
++#define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */
++#define UART_OMAP_SCR 0x10 /* Supplementary control register */
++#define UART_OMAP_SSR 0x11 /* Supplementary status register */
++#define UART_OMAP_EBLR 0x12 /* BOF length register */
++#define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */
++#define UART_OMAP_MVER 0x14 /* Module version register */
++#define UART_OMAP_SYSC 0x15 /* System configuration register */
++#define UART_OMAP_SYSS 0x16 /* System status register */
++
++
+--- /dev/null
++++ b/arch/mips/include/asm/rt2880/sizes.h
+@@ -0,0 +1,52 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++/* DO NOT EDIT!! - this file automatically generated
++ * from .s file by awk -f s2h.awk
++ */
++/* Size definitions
++ * Copyright (C) ARM Limited 1998. All rights reserved.
++ */
++
++#ifndef __sizes_h
++#define __sizes_h 1
++
++/* handy sizes */
++#define SZ_1K 0x00000400
++#define SZ_4K 0x00001000
++#define SZ_8K 0x00002000
++#define SZ_16K 0x00004000
++#define SZ_64K 0x00010000
++#define SZ_128K 0x00020000
++#define SZ_256K 0x00040000
++#define SZ_512K 0x00080000
++
++#define SZ_1M 0x00100000
++#define SZ_2M 0x00200000
++#define SZ_4M 0x00400000
++#define SZ_8M 0x00800000
++#define SZ_16M 0x01000000
++#define SZ_32M 0x02000000
++#define SZ_64M 0x04000000
++#define SZ_128M 0x08000000
++#define SZ_256M 0x10000000
++#define SZ_512M 0x20000000
++
++#define SZ_1G 0x40000000
++#define SZ_2G 0x80000000
++
++#endif
++
++/* END */
+--- /dev/null
++++ b/arch/mips/include/asm/rt2880/surfboard.h
+@@ -0,0 +1,70 @@
++/*
++ * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
++ *
++ * ########################################################################
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ */
++#ifndef _SURFBOARD_H
++#define _SURFBOARD_H
++
++#include <asm/addrspace.h>
++
++
++
++/*
++ * Surfboard system clock.
++ * This is the default value and maybe overidden by System Clock passed on the
++ * command line (sysclk=).
++ */
++#define SURFBOARD_SYSTEM_CLOCK (125000000)
++
++/*
++ * Surfboard UART base baud rate = System Clock / 16.
++ * Ex. (14.7456 MHZ / 16) = 921600
++ * (32.0000 MHZ / 16) = 2000000
++ */
++#define SURFBOARD_BAUD_DIV (16)
++#define SURFBOARD_BASE_BAUD (SURFBOARD_SYSTEM_CLOCK / SURFBOARD_BAUD_DIV)
++
++/*
++ * Maximum number of IDE Controllers
++ * Surfboard only has one ide (ide0), so only 2 drives are
++ * possible. (no need to check for more hwifs.)
++ */
++//#define MAX_IDE_HWIFS (1) /* Surfboard/Wakeboard */
++#define MAX_IDE_HWIFS (2) /* Graphite board */
++
++#define GCMP_BASE_ADDR 0x1fbf8000
++#define GCMP_ADDRSPACE_SZ (256 * 1024)
++
++/*
++ * * GIC Specific definitions
++ * */
++#define GIC_BASE_ADDR 0x1fbc0000
++#define GIC_ADDRSPACE_SZ (128 * 1024)
++#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE)
++
++/* GIC's Nomenclature for Core Interrupt Pins */
++#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
++#define GIC_CPU_INT1 1 /* . */
++#define GIC_CPU_INT2 2 /* . */
++#define GIC_CPU_INT3 3 /* . */
++#define GIC_CPU_INT4 4 /* . */
++#define GIC_CPU_INT5 5 /* Core Interrupt 5 */
++
++#endif /* !(_SURFBOARD_H) */
+--- /dev/null
++++ b/arch/mips/include/asm/rt2880/surfboardint.h
+@@ -0,0 +1,190 @@
++/*
++ * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
++ *
++ * ########################################################################
++ *
++ * This program is free software; you can distribute it and/or modify it
++ * under the terms of the GNU General Public License (Version 2) as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * ########################################################################
++ *
++ * Defines for the Surfboard interrupt controller.
++ *
++ */
++#ifndef _SURFBOARDINT_H
++#define _SURFBOARDINT_H
++
++/* Number of IRQ supported on hw interrupt 0. */
++#if defined (CONFIG_RALINK_RT2880)
++#define RALINK_CPU_TIMER_IRQ 6 /* mips timer */
++#define SURFBOARDINT_GPIO 7 /* GPIO */
++#define SURFBOARDINT_UART1 8 /* UART Lite */
++#define SURFBOARDINT_UART 9 /* UART */
++#define SURFBOARDINT_TIMER0 10 /* timer0 */
++#elif defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT2883) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620)
++#define RALINK_CPU_TIMER_IRQ 5 /* mips timer */
++#define SURFBOARDINT_GPIO 6 /* GPIO */
++#define SURFBOARDINT_DMA 7 /* DMA */
++#define SURFBOARDINT_NAND 8 /* NAND */
++#define SURFBOARDINT_PC 9 /* Performance counter */
++#define SURFBOARDINT_I2S 10 /* I2S */
++#define SURFBOARDINT_SDXC 14 /* SDXC */
++#define SURFBOARDINT_ESW 17 /* ESW */
++#define SURFBOARDINT_UART1 12 /* UART Lite */
++#define SURFBOARDINT_CRYPTO 13 /* CryptoEngine */
++#define SURFBOARDINT_SYSCTL 32 /* SYSCTL */
++#define SURFBOARDINT_TIMER0 33 /* timer0 */
++#define SURFBOARDINT_WDG 34 /* watch dog */
++#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
++#define SURFBOARDINT_PCM 36 /* PCM */
++#define SURFBOARDINT_UART 37 /* UART */
++#define RALINK_INT_PCIE0 13 /* PCIE0 */
++#define RALINK_INT_PCIE1 14 /* PCIE1 */
++
++
++#elif defined (CONFIG_RALINK_MT7628)
++#define SURFBOARDINT_SYSCTL 0 /* SYSCTL */
++#define SURFBOARDINT_PCM 4 /* PCM */
++#define SURFBOARDINT_GPIO 6 /* GPIO */
++#define SURFBOARDINT_DMA 7 /* DMA */
++#define SURFBOARDINT_PC 9 /* Performance counter */
++#define SURFBOARDINT_I2S 10 /* I2S */
++#define SURFBOARDINT_SPI 11 /* SPI */
++#define SURFBOARDINT_AES 13 /* AES */
++#define SURFBOARDINT_CRYPTO 13 /* CryptoEngine */
++#define SURFBOARDINT_SDXC 14 /* SDXC */
++#define SURFBOARDINT_ESW 17 /* ESW */
++#define SURFBOARDINT_USB 18 /* USB */
++#define SURFBOARDINT_UART_LITE1 20 /* UART Lite */
++#define SURFBOARDINT_UART_LITE2 21 /* UART Lite */
++#define SURFBOARDINT_UART_LITE3 22 /* UART Lite */
++#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1
++#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2
++#define SURFBOARDINT_WDG 23 /* WDG timer */
++#define SURFBOARDINT_TIMER0 24 /* Timer0 */
++#define SURFBOARDINT_TIMER1 25 /* Timer1 */
++#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
++#define RALINK_INT_PCIE0 2 /* PCIE0 */
++
++
++#elif defined (CONFIG_RALINK_MT7621)
++
++#define SURFBOARDINT_FE 3 /* FE */
++#define SURFBOARDINT_PCIE0 4 /* PCIE0 */
++#define SURFBOARDINT_SYSCTL 6 /* SYSCTL */
++#define SURFBOARDINT_I2C 8 /* I2C */
++#define SURFBOARDINT_DRAMC 9 /* DRAMC */
++#define SURFBOARDINT_PCM 10 /* PCM */
++#define SURFBOARDINT_HSGDMA 11 /* HSGDMA */
++#define SURFBOARDINT_GPIO 12 /* GPIO */
++#define SURFBOARDINT_DMA 13 /* GDMA */
++#define SURFBOARDINT_NAND 14 /* NAND */
++#define SURFBOARDINT_NAND_ECC 15 /* NFI ECC */
++#define SURFBOARDINT_I2S 16 /* I2S */
++#define SURFBOARDINT_SPI 17 /* SPI */
++#define SURFBOARDINT_SPDIF 18 /* SPDIF */
++#define SURFBOARDINT_CRYPTO 19 /* CryptoEngine */
++#define SURFBOARDINT_SDXC 20 /* SDXC */
++#define SURFBOARDINT_PCTRL 21 /* Performance counter */
++#define SURFBOARDINT_USB 22 /* USB */
++#define SURFBOARDINT_ESW 31 /* Switch */
++#define SURFBOARDINT_PCIE1 24 /* PCIE1 */
++#define SURFBOARDINT_PCIE2 25 /* PCIE2 */
++#define SURFBOARDINT_UART_LITE1 26 /* UART Lite */
++#define SURFBOARDINT_UART_LITE2 27 /* UART Lite */
++#define SURFBOARDINT_UART_LITE3 28 /* UART Lite */
++#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2 //ttyS0
++#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1 //ttyS1
++
++#define SURFBOARDINT_WDG 29 /* WDG timer */
++#define SURFBOARDINT_TIMER0 30 /* Timer0 */
++#define SURFBOARDINT_TIMER1 31 /* Timer1 */
++
++#define RALINK_INT_PCIE0 SURFBOARDINT_PCIE0
++#define RALINK_INT_PCIE1 SURFBOARDINT_PCIE1
++#define RALINK_INT_PCIE2 SURFBOARDINT_PCIE2
++
++#elif defined (CONFIG_RALINK_RT3883)
++#define RALINK_CPU_TIMER_IRQ 5 /* mips timer */
++#define SURFBOARDINT_GPIO 6 /* GPIO */
++#define SURFBOARDINT_DMA 7 /* DMA */
++#define SURFBOARDINT_NAND 8 /* NAND */
++#define SURFBOARDINT_PC 9 /* Performance counter */
++#define SURFBOARDINT_I2S 10 /* I2S */
++#define SURFBOARDINT_UART1 12 /* UART Lite */
++#define SURFBOARDINT_PCI 18 /* PCI */
++#define SURFBOARDINT_UDEV 19 /* USB Device */
++#define SURFBOARDINT_UHST 20 /* USB Host */
++#define SURFBOARDINT_SYSCTL 32 /* SYSCTL */
++#define SURFBOARDINT_TIMER0 33 /* timer0 */
++#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
++#define SURFBOARDINT_PCM 36 /* PCM */
++#define SURFBOARDINT_UART 37 /* UART */
++#endif
++
++#define SURFBOARDINT_END 64
++#define RT2880_INTERINT_START 40
++
++/* Global interrupt bit definitions */
++#define C_SURFBOARD_GLOBAL_INT 31
++#define M_SURFBOARD_GLOBAL_INT (1 << C_SURFBOARD_GLOBAL_INT)
++
++/* added ??? */
++#define RALINK_SDRAM_ILL_ACC_ADDR *(volatile u32 *)(RALINK_SYSCTL_BASE + 0x310)
++#define RALINK_SDRAM_ILL_ACC_TYPE *(volatile u32 *)(RALINK_SYSCTL_BASE + 0x314)
++/* end of added, bobtseng */
++
++/*
++ * Surfboard registers are memory mapped on 32-bit aligned boundaries and
++ * only word access are allowed.
++ */
++#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
++#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x9C) //IRQ_STAT
++#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0xA0) //FIQ_STAT
++#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x6C) //FIQ_SEL
++#define RALINK_INTRAW (RALINK_INTCL_BASE + 0xA4) //INT_PURE
++#define RALINK_INTENA (RALINK_INTCL_BASE + 0x80) //IRQ_MASK_SET
++#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x78) //IRQ_MASK_CLR
++#else
++#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x0)
++#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0x4)
++#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x20)
++#define RALINK_INTRAW (RALINK_INTCL_BASE + 0x30)
++#define RALINK_INTENA (RALINK_INTCL_BASE + 0x34)
++#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x38)
++#endif
++
++/* bobtseng added ++, 2006.3.6. */
++#define read_32bit_cp0_register(source) \
++({ int __res; \
++ __asm__ __volatile__( \
++ ".set\tpush\n\t" \
++ ".set\treorder\n\t" \
++ "mfc0\t%0,"STR(source)"\n\t" \
++ ".set\tpop" \
++ : "=r" (__res)); \
++ __res;})
++
++#define write_32bit_cp0_register(register,value) \
++ __asm__ __volatile__( \
++ "mtc0\t%0,"STR(register)"\n\t" \
++ "nop" \
++ : : "r" (value));
++
++/* bobtseng added --, 2006.3.6. */
++
++void surfboardint_init(void);
++u32 get_surfboard_sysclk(void);
++
++
++#endif /* !(_SURFBOARDINT_H) */
+--- /dev/null
++++ b/arch/mips/include/asm/rt2880/war.h
+@@ -0,0 +1,25 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
++ */
++#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
++#define __ASM_MIPS_MACH_MIPS_WAR_H
++
++#define R4600_V1_INDEX_ICACHEOP_WAR 0
++#define R4600_V1_HIT_CACHEOP_WAR 0
++#define R4600_V2_HIT_CACHEOP_WAR 0
++#define R5432_CP0_INTERRUPT_WAR 0
++#define BCM1250_M3_WAR 0
++#define SIBYTE_1956_WAR 0
++#define MIPS4K_ICACHE_REFILL_WAR 1
++#define MIPS_CACHE_SYNC_WAR 1
++#define TX49XX_ICACHE_INDEX_INV_WAR 0
++#define RM9000_CDEX_SMP_WAR 0
++#define ICACHE_REFILLS_WORKAROUND_WAR 1
++#define R10000_LLSC_WAR 0
++#define MIPS34K_MISSED_ITLB_WAR 0
++
++#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/target/linux/ramips/patches-3.10/0217-pinmux-rt2880.patch b/target/linux/ramips/patches-3.10/0217-pinmux-rt2880.patch
new file mode 100644
index 0000000000..05d95484da
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0217-pinmux-rt2880.patch
@@ -0,0 +1,88 @@
+Index: linux-3.10.32/arch/mips/ralink/rt288x.c
+===================================================================
+--- linux-3.10.32.orig/arch/mips/ralink/rt288x.c 2014-02-22 20:41:54.000000000 +0000
++++ linux-3.10.32/arch/mips/ralink/rt288x.c 2014-03-18 11:18:06.689596876 +0000
+@@ -17,46 +17,27 @@
+ #include <asm/mipsregs.h>
+ #include <asm/mach-ralink/ralink_regs.h>
+ #include <asm/mach-ralink/rt288x.h>
++#include <asm/mach-ralink/pinmux.h>
+
+ #include "common.h"
+
+-static struct ralink_pinmux_grp mode_mux[] = {
+- {
+- .name = "i2c",
+- .mask = RT2880_GPIO_MODE_I2C,
+- .gpio_first = 1,
+- .gpio_last = 2,
+- }, {
+- .name = "spi",
+- .mask = RT2880_GPIO_MODE_SPI,
+- .gpio_first = 3,
+- .gpio_last = 6,
+- }, {
+- .name = "uartlite",
+- .mask = RT2880_GPIO_MODE_UART0,
+- .gpio_first = 7,
+- .gpio_last = 14,
+- }, {
+- .name = "jtag",
+- .mask = RT2880_GPIO_MODE_JTAG,
+- .gpio_first = 17,
+- .gpio_last = 21,
+- }, {
+- .name = "mdio",
+- .mask = RT2880_GPIO_MODE_MDIO,
+- .gpio_first = 22,
+- .gpio_last = 23,
+- }, {
+- .name = "sdram",
+- .mask = RT2880_GPIO_MODE_SDRAM,
+- .gpio_first = 24,
+- .gpio_last = 39,
+- }, {
+- .name = "pci",
+- .mask = RT2880_GPIO_MODE_PCI,
+- .gpio_first = 40,
+- .gpio_last = 71,
+- }, {0}
++static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
++static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 6) };
++static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 14) };
++static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 21) };
++static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 23) };
++static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 39) };
++static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 71) };
++
++static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
++ GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
++ GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
++ GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
++ GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
++ GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
++ GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
++ GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
++ { 0 }
+ };
+
+ static void rt288x_wdt_reset(void)
+@@ -69,11 +50,6 @@
+ rt_sysc_w32(t, SYSC_REG_CLKCFG);
+ }
+
+-struct ralink_pinmux rt_gpio_pinmux = {
+- .mode = mode_mux,
+- .wdt_reset = rt288x_wdt_reset,
+-};
+-
+ void __init ralink_clk_init(void)
+ {
+ unsigned long cpu_rate;
+@@ -140,4 +116,6 @@
+ soc_info->mem_base = RT2880_SDRAM_BASE;
+ soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
+ soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
++
++ rt2880_pinmux_data = rt2880_pinmux_data_act;
+ }
diff --git a/target/linux/ramips/patches-3.10/0203-owrt-MIPS-add-OWRTDTB-secion.patch b/target/linux/ramips/patches-3.10/0300-MIPS-OWRTDTB.patch
similarity index 80%
rename from target/linux/ramips/patches-3.10/0203-owrt-MIPS-add-OWRTDTB-secion.patch
rename to target/linux/ramips/patches-3.10/0300-MIPS-OWRTDTB.patch
index 71d8fe9982..1a00dc2dd8 100644
--- a/target/linux/ramips/patches-3.10/0203-owrt-MIPS-add-OWRTDTB-secion.patch
+++ b/target/linux/ramips/patches-3.10/0300-MIPS-OWRTDTB.patch
@@ -24,7 +24,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
NESTED(kernel_entry, 16, sp) # kernel entry point
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
-@@ -21,4 +21,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
+@@ -26,4 +26,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
obj-$(CONFIG_DEBUG_FS) += bootrom.o
@@ -32,8 +32,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#obj-y += dts/
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
-@@ -77,6 +77,8 @@ void __init device_tree_init(void)
- //free_bootmem(base, size);
+@@ -90,6 +90,8 @@ static int __init early_init_dt_find_mem
+ return 0;
}
+extern struct boot_param_header __image_dtb;
@@ -41,12 +41,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
void __init plat_mem_setup(void)
{
set_io_port_base(KSEG1);
-@@ -85,7 +87,7 @@ void __init plat_mem_setup(void)
+@@ -98,7 +100,7 @@ void __init plat_mem_setup(void)
* Load the builtin devicetree. This causes the chosen node to be
* parsed resulting in our memory appearing
*/
- __dt_setup_arch(&__dtb_start);
+ __dt_setup_arch(&__image_dtb);
- if (soc_info.mem_size)
- add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
+ of_scan_flat_dt(early_init_dt_find_memory, NULL);
+ if (memory_dtb)
diff --git a/target/linux/ramips/patches-3.10/0501-MIPS-increase-GIC_INTR_MAX.patch b/target/linux/ramips/patches-3.10/0501-MIPS-increase-GIC_INTR_MAX.patch
deleted file mode 100644
index 35ac5ed572..0000000000
--- a/target/linux/ramips/patches-3.10/0501-MIPS-increase-GIC_INTR_MAX.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From e5327a1c6969316370af5cae7cfe6b8163178575 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 2 Dec 2013 16:07:23 +0100
-Subject: [PATCH 500/507] MIPS: increase GIC_INTR_MAX
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/gic.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/include/asm/gic.h
-+++ b/arch/mips/include/asm/gic.h
-@@ -19,7 +19,7 @@
- #define GIC_TRIG_EDGE 1
- #define GIC_TRIG_LEVEL 0
-
--#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
-+#define GIC_NUM_INTRS (56 + NR_CPUS * 2)
-
- #define MSK(n) ((1 << (n)) - 1)
- #define REG32(addr) (*(volatile unsigned int *) (addr))
diff --git a/target/linux/ramips/patches-3.10/0509-MIPS-Kconfig-CMP-support-needs-to-select-SMP-as-well.patch b/target/linux/ramips/patches-3.10/0509-MIPS-Kconfig-CMP-support-needs-to-select-SMP-as-well.patch
deleted file mode 100644
index 1e6afb21de..0000000000
--- a/target/linux/ramips/patches-3.10/0509-MIPS-Kconfig-CMP-support-needs-to-select-SMP-as-well.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From 184edf882ebb7885b49fa231a503205da94e78f0 Mon Sep 17 00:00:00 2001
-From: Markos Chandras <markos.chandras@imgtec.com>
-Date: Wed, 2 Oct 2013 12:40:26 -0500
-Subject: [PATCH 065/105] MIPS: Kconfig: CMP support needs to select SMP as
- well
-
-The CMP code is only designed to work with SMP configurations.
-Fixes multiple build problems on certain randconfigs:
-
-In file included from arch/mips/kernel/smp-cmp.c:34:0:
-arch/mips/include/asm/smp.h:28:0:
-error: "raw_smp_processor_id" redefined [-Werror]
-
-In file included from include/linux/sched.h:30:0,
-from arch/mips/kernel/smp-cmp.c:22:
-include/linux/smp.h:135:0: note: this is the location of the
-previous definition
-
-In file included from arch/mips/kernel/smp-cmp.c:34:0:
-arch/mips/include/asm/smp.h:57:20:
-error: redefinition of 'smp_send_reschedule'
-
-In file included from include/linux/sched.h:30:0,
-from arch/mips/kernel/smp-cmp.c:22:
-include/linux/smp.h:179:20: note: previous
-definition of 'smp_send_reschedule' was here
-
-In file included from arch/mips/kernel/smp-cmp.c:34:0:
-arch/mips/include/asm/smp.h: In function 'smp_send_reschedule':
-arch/mips/include/asm/smp.h:61:8:
-error: dereferencing pointer to incomplete type
-[...]
-
-Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
-Cc: linux-mips@linux-mips.org
-Cc: Markos Chandras <markos.chandras@imgtec.com>
-Patchwork: https://patchwork.linux-mips.org/patch/5812/
-Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
----
- arch/mips/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -2038,6 +2038,7 @@ config MIPS_VPE_APSP_API
- config MIPS_CMP
- bool "MIPS CMP framework support"
- depends on SYS_SUPPORTS_MIPS_CMP
-+ select SMP
- select SYNC_R4K
- select SYS_SUPPORTS_SMP
- select SYS_SUPPORTS_SCHED_SMT if SMP
diff --git a/target/linux/ramips/patches-3.10/0512-USB-add-xhci-support-for-mt7621.patch b/target/linux/ramips/patches-3.10/0512-USB-add-xhci-support-for-mt7621.patch
deleted file mode 100644
index 7cc81a2a6d..0000000000
--- a/target/linux/ramips/patches-3.10/0512-USB-add-xhci-support-for-mt7621.patch
+++ /dev/null
@@ -1,840 +0,0 @@
---- a/drivers/usb/core/hub.c
-+++ b/drivers/usb/core/hub.c
-@@ -1254,7 +1254,7 @@ static void hub_quiesce(struct usb_hub *
- if (type != HUB_SUSPEND) {
- /* Disconnect all the children */
- for (i = 0; i < hdev->maxchild; ++i) {
-- if (hub->ports[i]->child)
-+ if (hub->ports[i] && hub->ports[i]->child)
- usb_disconnect(&hub->ports[i]->child);
- }
- }
---- a/drivers/usb/core/port.c
-+++ b/drivers/usb/core/port.c
-@@ -193,6 +193,7 @@ exit:
- void usb_hub_remove_port_device(struct usb_hub *hub,
- int port1)
- {
-- device_unregister(&hub->ports[port1 - 1]->dev);
-+ if (hub->ports[port1 - 1])
-+ device_unregister(&hub->ports[port1 - 1]->dev);
- }
-
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -28,7 +28,11 @@ config USB_XHCI_HCD
- if USB_XHCI_HCD
-
- config USB_XHCI_PLATFORM
-- tristate
-+ bool "xHCI platform"
-+
-+config USB_MT7621_XHCI_PLATFORM
-+ bool "MTK MT7621 xHCI"
-+ depends on USB_XHCI_PLATFORM
-
- config USB_XHCI_HCD_DEBUGGING
- bool "Debugging for the xHCI host controller"
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -13,15 +13,23 @@ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
-
- xhci-hcd-y := xhci.o xhci-mem.o
- xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
-+ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
- xhci-hcd-$(CONFIG_PCI) += xhci-pci.o
-+endif
-+
-+ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
-+xhci-hcd-y += mtk-phy.o xhci-mtk-scheduler.o xhci-mtk-power.o xhci-mtk.o mtk-phy-7621.o mtk-phy-ahb.o
-+endif
-
- ifneq ($(CONFIG_USB_XHCI_PLATFORM), )
-- xhci-hcd-y += xhci-plat.o
-+xhci-hcd-y += xhci-plat.o
- endif
-
- obj-$(CONFIG_USB_WHCI_HCD) += whci/
-
-+ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
- obj-$(CONFIG_PCI) += pci-quirks.o
-+endif
-
- obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
- obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
---- a/drivers/usb/host/pci-quirks.h
-+++ b/drivers/usb/host/pci-quirks.h
-@@ -1,7 +1,7 @@
- #ifndef __LINUX_USB_PCI_QUIRKS_H
- #define __LINUX_USB_PCI_QUIRKS_H
-
--#ifdef CONFIG_PCI
-+#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
- int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
- #endif /* CONFIG_PCI */
---- a/drivers/usb/host/xhci.c
-+++ b/drivers/usb/host/xhci.c
-@@ -30,6 +30,16 @@
-
- #include "xhci.h"
-
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+#include <asm/uaccess.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/platform_device.h>
-+#include "mtk-phy.h"
-+#include "xhci-mtk-scheduler.h"
-+#include "xhci-mtk-power.h"
-+#include "xhci-mtk.h"
-+#endif
-+
- #define DRIVER_AUTHOR "Sarah Sharp"
- #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
-
-@@ -38,6 +48,18 @@ static int link_quirk;
- module_param(link_quirk, int, S_IRUGO | S_IWUSR);
- MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
-
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
-+static struct file_operations xhci_mtk_test_fops = {
-+ .owner = THIS_MODULE,
-+ .read = xhci_mtk_test_read,
-+ .write = xhci_mtk_test_write,
-+ .unlocked_ioctl = xhci_mtk_test_unlock_ioctl,
-+ .open = xhci_mtk_test_open,
-+ .release = xhci_mtk_test_release,
-+};
-+#endif
-+
- /* TODO: copied from ehci-hcd.c - can this be refactored? */
- /*
- * xhci_handshake - spin reading hc until handshake completes or fails
-@@ -189,7 +211,7 @@ int xhci_reset(struct xhci_hcd *xhci)
- return ret;
- }
-
--#ifdef CONFIG_PCI
-+#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- static int xhci_free_msi(struct xhci_hcd *xhci)
- {
- int i;
-@@ -389,6 +411,7 @@ static int xhci_try_enable_msi(struct us
- return ret;
- }
- hcd->irq = pdev->irq;
-+
- return 0;
- }
-
-@@ -430,6 +453,11 @@ static void compliance_mode_recovery(uns
- xhci_dbg(xhci, "Attempting compliance mode recovery\n");
- hcd = xhci->shared_hcd;
-
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ temp |= (1 << 31);
-+ xhci_writel(xhci, temp, xhci->usb3_ports[i]);
-+#endif
-+
- if (hcd->state == HC_STATE_SUSPENDED)
- usb_hcd_resume_root_hub(hcd);
-
-@@ -478,6 +506,9 @@ bool xhci_compliance_mode_recovery_timer
- {
- const char *dmi_product_name, *dmi_sys_vendor;
-
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ return true;
-+#endif
- dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
- dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
- if (!dmi_product_name || !dmi_sys_vendor)
-@@ -521,6 +552,10 @@ int xhci_init(struct usb_hcd *hcd)
- } else {
- xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
- }
-+
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ mtk_xhci_scheduler_init();
-+#endif
- retval = xhci_mem_init(xhci, GFP_KERNEL);
- xhci_dbg(xhci, "Finished xhci_init\n");
-
-@@ -664,7 +699,11 @@ int xhci_run(struct usb_hcd *hcd)
- xhci_dbg(xhci, "// Set the interrupt modulation register\n");
- temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
- temp &= ~ER_IRQ_INTERVAL_MASK;
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ temp |= (u32) 16;
-+#else
- temp |= (u32) 160;
-+#endif
- xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
-
- /* Set the HCD state before we enable the irqs */
-@@ -685,6 +724,9 @@ int xhci_run(struct usb_hcd *hcd)
- xhci_queue_vendor_command(xhci, 0, 0, 0,
- TRB_TYPE(TRB_NEC_GET_FW));
-
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ enableXhciAllPortPower(xhci);
-+#endif
- xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
- return 0;
- }
-@@ -1002,7 +1044,6 @@ int xhci_resume(struct xhci_hcd *xhci, b
-
- /* If restore operation fails, re-initialize the HC during resume */
- if ((temp & STS_SRE) || hibernated) {
--
- if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
- !(xhci_all_ports_seen_u0(xhci))) {
- del_timer_sync(&xhci->comp_mode_recovery_timer);
-@@ -1586,6 +1627,13 @@ int xhci_drop_endpoint(struct usb_hcd *h
- u32 drop_flag;
- u32 new_add_flags, new_drop_flags, new_slot_info;
- int ret;
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+#if MTK_SCH_NEW
-+ struct sch_ep *sch_ep = NULL;
-+ int isTT;
-+ int ep_type;
-+#endif
-+#endif
-
- ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
- if (ret <= 0)
-@@ -1637,6 +1685,40 @@ int xhci_drop_endpoint(struct usb_hcd *h
-
- xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
-
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+#if MTK_SCH_NEW
-+ slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[udev->slot_id]->out_ctx);
-+ if ((slot_ctx->tt_info & 0xff) > 0) {
-+ isTT = 1;
-+ }
-+ else {
-+ isTT = 0;
-+ }
-+ if (usb_endpoint_xfer_int(&ep->desc)) {
-+ ep_type = USB_EP_INT;
-+ }
-+ else if (usb_endpoint_xfer_isoc(&ep->desc)) {
-+ ep_type = USB_EP_ISOC;
-+ }
-+ else if (usb_endpoint_xfer_bulk(&ep->desc)) {
-+ ep_type = USB_EP_BULK;
-+ }
-+ else
-+ ep_type = USB_EP_CONTROL;
-+
-+ sch_ep = mtk_xhci_scheduler_remove_ep(udev->speed, usb_endpoint_dir_in(&ep->desc)
-+ , isTT, ep_type, (mtk_u32 *)ep);
-+ if (sch_ep != NULL) {
-+ kfree(sch_ep);
-+ }
-+ else {
-+ xhci_dbg(xhci, "[MTK]Doesn't find ep_sch instance when removing endpoint\n");
-+ }
-+#else
-+ mtk_xhci_scheduler_remove_ep(xhci, udev, ep);
-+#endif
-+#endif
-+
- xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
- (unsigned int) ep->desc.bEndpointAddress,
- udev->slot_id,
-@@ -1672,6 +1754,18 @@ int xhci_add_endpoint(struct usb_hcd *hc
- u32 new_add_flags, new_drop_flags, new_slot_info;
- struct xhci_virt_device *virt_dev;
- int ret = 0;
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ struct xhci_ep_ctx *in_ep_ctx;
-+#if MTK_SCH_NEW
-+ struct sch_ep *sch_ep;
-+ int isTT;
-+ int ep_type;
-+ int maxp = 0;
-+ int burst = 0;
-+ int mult = 0;
-+ int interval;
-+#endif
-+#endif
-
- ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
- if (ret <= 0) {
-@@ -1734,6 +1828,56 @@ int xhci_add_endpoint(struct usb_hcd *hc
- return -ENOMEM;
- }
-
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
-+#if MTK_SCH_NEW
-+ slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
-+ if ((slot_ctx->tt_info & 0xff) > 0) {
-+ isTT = 1;
-+ }
-+ else {
-+ isTT = 0;
-+ }
-+ if (usb_endpoint_xfer_int(&ep->desc)) {
-+ ep_type = USB_EP_INT;
-+ }
-+ else if (usb_endpoint_xfer_isoc(&ep->desc)) {
-+ ep_type = USB_EP_ISOC;
-+ }
-+ else if (usb_endpoint_xfer_bulk(&ep->desc)) {
-+ ep_type = USB_EP_BULK;
-+ }
-+ else
-+ ep_type = USB_EP_CONTROL;
-+
-+ if (udev->speed == USB_SPEED_FULL || udev->speed == USB_SPEED_HIGH
-+ || udev->speed == USB_SPEED_LOW) {
-+ maxp = ep->desc.wMaxPacketSize & 0x7FF;
-+ burst = ep->desc.wMaxPacketSize >> 11;
-+ mult = 0;
-+ }
-+ else if (udev->speed == USB_SPEED_SUPER) {
-+ maxp = ep->desc.wMaxPacketSize & 0x7FF;
-+ burst = ep->ss_ep_comp.bMaxBurst;
-+ mult = ep->ss_ep_comp.bmAttributes & 0x3;
-+ }
-+ interval = (1 << ((in_ep_ctx->ep_info >> 16) & 0xff));
-+ sch_ep = kmalloc(sizeof(struct sch_ep), GFP_KERNEL);
-+ if (mtk_xhci_scheduler_add_ep(udev->speed, usb_endpoint_dir_in(&ep->desc),
-+ isTT, ep_type, maxp, interval, burst, mult, (mtk_u32 *)ep
-+ , (mtk_u32 *)in_ep_ctx, sch_ep) != SCH_SUCCESS) {
-+ xhci_err(xhci, "[MTK] not enough bandwidth\n");
-+
-+ return -ENOSPC;
-+ }
-+#else
-+ if (mtk_xhci_scheduler_add_ep(xhci, udev, ep, in_ep_ctx) != SCH_SUCCESS) {
-+ xhci_err(xhci, "[MTK] not enough bandwidth\n");
-+
-+ return -ENOSPC;
-+ }
-+#endif
-+#endif
- ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
- new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
-
-@@ -2697,7 +2841,7 @@ int xhci_check_bandwidth(struct usb_hcd
- if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
- ctrl_ctx->drop_flags == 0)
- return 0;
--
-+
- xhci_dbg(xhci, "New Input Control Context:\n");
- slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
- xhci_dbg_ctx(xhci, virt_dev->in_ctx,
-@@ -4233,10 +4377,14 @@ static u16 xhci_call_host_update_timeout
- u16 *timeout)
- {
- if (state == USB3_LPM_U1) {
-+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- if (xhci->quirks & XHCI_INTEL_HOST)
-+#endif
- return xhci_calculate_intel_u1_timeout(udev, desc);
- } else {
-+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- if (xhci->quirks & XHCI_INTEL_HOST)
-+#endif
- return xhci_calculate_intel_u2_timeout(udev, desc);
- }
-
-@@ -4662,7 +4810,9 @@ int xhci_gen_setup(struct usb_hcd *hcd,
- /* Accept arbitrarily long scatter-gather lists */
- hcd->self.sg_tablesize = ~0;
- /* XHCI controllers don't stop the ep queue on short packets :| */
-+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- hcd->self.no_stop_on_short = 1;
-+#endif
-
- if (usb_hcd_is_primary_hcd(hcd)) {
- xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
-@@ -4731,6 +4881,10 @@ int xhci_gen_setup(struct usb_hcd *hcd,
- goto error;
- xhci_dbg(xhci, "Reset complete\n");
-
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ setInitialReg();
-+#endif
-+
- temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
- if (HCC_64BIT_ADDR(temp)) {
- xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
-@@ -4755,8 +4909,21 @@ MODULE_DESCRIPTION(DRIVER_DESC);
- MODULE_AUTHOR(DRIVER_AUTHOR);
- MODULE_LICENSE("GPL");
-
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+static struct platform_device xhci_platform_dev = {
-+ .name = "xhci-hcd",
-+ .id = -1,
-+ .dev = {
-+ .coherent_dma_mask = 0xffffffff,
-+ },
-+};
-+#endif
-+
- static int __init xhci_hcd_init(void)
- {
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ struct platform_device *pPlatformDev;
-+#endif
- int retval;
-
- retval = xhci_register_pci();
-@@ -4769,6 +4936,33 @@ static int __init xhci_hcd_init(void)
- printk(KERN_DEBUG "Problem registering platform driver.");
- goto unreg_pci;
- }
-+
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ retval = register_chrdev(XHCI_MTK_TEST_MAJOR, DEVICE_NAME, &xhci_mtk_test_fops);
-+
-+ u3phy_init();
-+ if (u3phy_ops->u2_slew_rate_calibration) {
-+ u3phy_ops->u2_slew_rate_calibration(u3phy);
-+ u3phy_ops->u2_slew_rate_calibration(u3phy_p1);
-+ }
-+ else{
-+ printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
-+ }
-+ u3phy_ops->init(u3phy);
-+ reinitIP();
-+
-+ pPlatformDev = &xhci_platform_dev;
-+ memset(pPlatformDev, 0, sizeof(struct platform_device));
-+ pPlatformDev->name = "xhci-hcd";
-+ pPlatformDev->id = -1;
-+ pPlatformDev->dev.coherent_dma_mask = 0xffffffff;
-+ pPlatformDev->dev.dma_mask = &pPlatformDev->dev.coherent_dma_mask;
-+
-+ retval = platform_device_register(&xhci_platform_dev);
-+ if (retval < 0)
-+ xhci_unregister_plat();
-+#endif
-+
- /*
- * Check the compiler generated sizes of structures that must be laid
- * out in specific ways for hardware access.
-@@ -4786,6 +4980,7 @@ static int __init xhci_hcd_init(void)
- BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
- /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
- BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
-+
- return 0;
- unreg_pci:
- xhci_unregister_pci();
---- a/drivers/usb/host/xhci-dbg.c
-+++ b/drivers/usb/host/xhci-dbg.c
-@@ -21,6 +21,9 @@
- */
-
- #include "xhci.h"
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+#include "xhci-mtk.h"
-+#endif
-
- #define XHCI_INIT_VALUE 0x0
-
---- a/drivers/usb/host/xhci.h
-+++ b/drivers/usb/host/xhci.h
-@@ -29,9 +29,24 @@
- #include <linux/usb/hcd.h>
-
- /* Code sharing between pci-quirks and xhci hcd */
--#include "xhci-ext-caps.h"
-+#include "xhci-ext-caps.h"
- #include "pci-quirks.h"
-
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+#define XHC_IRQ (22 + 8)
-+#define XHC_IO_START 0x1E1C0000
-+#define XHC_IO_LENGTH 0x10000
-+/* mtk scheduler bitmasks */
-+#define BPKTS(p) ((p) & 0x3f)
-+#define BCSCOUNT(p) (((p) & 0x7) << 8)
-+#define BBM(p) ((p) << 11)
-+#define BOFFSET(p) ((p) & 0x3fff)
-+#define BREPEAT(p) (((p) & 0x7fff) << 16)
-+#endif
-+
-+
-+
-+
- /* xHCI PCI Configuration Registers */
- #define XHCI_SBRN_OFFSET (0x60)
-
-@@ -1536,8 +1551,12 @@ struct xhci_hcd {
- /* Compliance Mode Recovery Data */
- struct timer_list comp_mode_recovery_timer;
- u32 port_status_u0;
-+#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
-+#define COMP_MODE_RCVRY_MSECS 5000
-+#else
- /* Compliance Mode Timer Triggered every 2 seconds */
- #define COMP_MODE_RCVRY_MSECS 2000
-+#endif
- };
-
- /* convert between an HCD pointer and the corresponding EHCI_HCD */
-@@ -1703,7 +1722,7 @@ void xhci_urb_free_priv(struct xhci_hcd
- void xhci_free_command(struct xhci_hcd *xhci,
- struct xhci_command *command);
-
--#ifdef CONFIG_PCI
-+#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- /* xHCI PCI glue */
- int xhci_register_pci(void);
- void xhci_unregister_pci(void);
---- a/drivers/usb/host/xhci-mem.c
-+++ b/drivers/usb/host/xhci-mem.c
-@@ -65,6 +65,9 @@ static struct xhci_segment *xhci_segment
-
- static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
- {
-+ if (!seg)
-+ return;
-+
- if (seg->trbs) {
- dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
- seg->trbs = NULL;
-@@ -1446,9 +1449,17 @@ int xhci_endpoint_init(struct xhci_hcd *
- max_burst = (usb_endpoint_maxp(&ep->desc)
- & 0x1800) >> 11;
- }
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
-+ max_packet += 2;
-+#endif
- break;
- case USB_SPEED_FULL:
- case USB_SPEED_LOW:
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
-+ max_packet += 2;
-+#endif
- break;
- default:
- BUG();
---- a/drivers/usb/host/xhci-plat.c
-+++ b/drivers/usb/host/xhci-plat.c
-@@ -25,6 +25,13 @@ static void xhci_plat_quirks(struct devi
- * dev struct in order to setup MSI
- */
- xhci->quirks |= XHCI_PLAT;
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ /* MTK host controller gives a spurious successful event after a
-+ * short transfer. Ignore it.
-+ */
-+ xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
-+ xhci->quirks |= XHCI_LPM_SUPPORT;
-+#endif
- }
-
- /* called during probe() after chip reset completes */
-@@ -96,20 +103,32 @@ static int xhci_plat_probe(struct platfo
-
- driver = &xhci_plat_xhci_driver;
-
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ irq = XHC_IRQ;
-+#else
- irq = platform_get_irq(pdev, 0);
-+#endif
-+
- if (irq < 0)
- return -ENODEV;
-
-+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- return -ENODEV;
-+#endif
-
- hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
- if (!hcd)
- return -ENOMEM;
-
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ hcd->rsrc_start = (uint32_t)XHC_IO_START;
-+ hcd->rsrc_len = XHC_IO_LENGTH;
-+#else
- hcd->rsrc_start = res->start;
- hcd->rsrc_len = resource_size(res);
-+#endif
-
- if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
- driver->description)) {
---- a/drivers/usb/host/xhci-ring.c
-+++ b/drivers/usb/host/xhci-ring.c
-@@ -236,7 +236,6 @@ static void inc_enq(struct xhci_hcd *xhc
- */
- if (!chain && !more_trbs_coming)
- break;
--
- /* If we're not dealing with 0.95 hardware or
- * isoc rings on AMD 0.96 host,
- * carry over the chain bit of the previous TRB
-@@ -273,16 +272,20 @@ static void inc_enq(struct xhci_hcd *xhc
- static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
- unsigned int num_trbs)
- {
-+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- int num_trbs_in_deq_seg;
-+#endif
-
- if (ring->num_trbs_free < num_trbs)
- return 0;
-
-+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
- num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
- if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
- return 0;
- }
-+#endif
-
- return 1;
- }
-@@ -2910,6 +2913,7 @@ static int prepare_ring(struct xhci_hcd
- next = ring->enqueue;
-
- while (last_trb(xhci, ring, ring->enq_seg, next)) {
-+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- /* If we're not dealing with 0.95 hardware or isoc rings
- * on AMD 0.96 host, clear the chain bit.
- */
-@@ -2919,7 +2923,9 @@ static int prepare_ring(struct xhci_hcd
- next->link.control &= cpu_to_le32(~TRB_CHAIN);
- else
- next->link.control |= cpu_to_le32(TRB_CHAIN);
--
-+#else
-+ next->link.control &= cpu_to_le32(~TRB_CHAIN);
-+#endif
- wmb();
- next->link.control ^= cpu_to_le32(TRB_CYCLE);
-
-@@ -3049,6 +3055,9 @@ static void giveback_first_trb(struct xh
- start_trb->field[3] |= cpu_to_le32(start_cycle);
- else
- start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ wmb();
-+#endif
- xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
- }
-
-@@ -3108,6 +3117,29 @@ static u32 xhci_td_remainder(unsigned in
- return (remainder >> 10) << 17;
- }
-
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+static u32 mtk_xhci_td_remainder(unsigned int td_transfer_size, unsigned int td_running_total, unsigned int maxp, unsigned trb_buffer_length)
-+{
-+ u32 max = 31;
-+ int remainder, td_packet_count, packet_transferred;
-+
-+ //0 for the last TRB
-+ //FIXME: need to workaround if there is ZLP in this TD
-+ if (td_running_total + trb_buffer_length == td_transfer_size)
-+ return 0;
-+
-+ //FIXME: need to take care of high-bandwidth (MAX_ESIT)
-+ packet_transferred = (td_running_total /*+ trb_buffer_length*/) / maxp;
-+ td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp);
-+ remainder = td_packet_count - packet_transferred;
-+
-+ if (remainder > max)
-+ return max << 17;
-+ else
-+ return remainder << 17;
-+}
-+#endif
-+
- /*
- * For xHCI 1.0 host controllers, TD size is the number of max packet sized
- * packets remaining in the TD (*not* including this TRB).
-@@ -3245,6 +3277,7 @@ static int queue_bulk_sg_tx(struct xhci_
- }
-
- /* Set the TRB length, TD size, and interrupter fields. */
-+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- if (xhci->hci_version < 0x100) {
- remainder = xhci_td_remainder(
- urb->transfer_buffer_length -
-@@ -3254,6 +3287,13 @@ static int queue_bulk_sg_tx(struct xhci_
- trb_buff_len, total_packet_count, urb,
- num_trbs - 1);
- }
-+#else
-+ if (num_trbs > 1)
-+ remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length,
-+ running_total, urb->ep->desc.wMaxPacketSize, trb_buff_len);
-+#endif
-+
-+
- length_field = TRB_LEN(trb_buff_len) |
- remainder |
- TRB_INTR_TARGET(0);
-@@ -3316,6 +3356,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
- int running_total, trb_buff_len, ret;
- unsigned int total_packet_count;
- u64 addr;
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ int max_packet;
-+#endif
-
- if (urb->num_sgs)
- return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
-@@ -3341,6 +3384,25 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
- running_total += TRB_MAX_BUFF_SIZE;
- }
- /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ switch(urb->dev->speed){
-+ case USB_SPEED_SUPER:
-+ max_packet = urb->ep->desc.wMaxPacketSize;
-+ break;
-+ case USB_SPEED_HIGH:
-+ case USB_SPEED_FULL:
-+ case USB_SPEED_LOW:
-+ case USB_SPEED_WIRELESS:
-+ case USB_SPEED_UNKNOWN:
-+ default:
-+ max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
-+ break;
-+ }
-+ if((urb->transfer_flags & URB_ZERO_PACKET)
-+ && ((urb->transfer_buffer_length % max_packet) == 0)){
-+ num_trbs++;
-+ }
-+#endif
-
- ret = prepare_transfer(xhci, xhci->devs[slot_id],
- ep_index, urb->stream_id,
-@@ -3400,6 +3462,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
- field |= TRB_ISP;
-
- /* Set the TRB length, TD size, and interrupter fields. */
-+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- if (xhci->hci_version < 0x100) {
- remainder = xhci_td_remainder(
- urb->transfer_buffer_length -
-@@ -3409,6 +3472,10 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
- trb_buff_len, total_packet_count, urb,
- num_trbs - 1);
- }
-+#else
-+ remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
-+#endif
-+
- length_field = TRB_LEN(trb_buff_len) |
- remainder |
- TRB_INTR_TARGET(0);
-@@ -3498,7 +3565,11 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
- field |= 0x1;
-
- /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ if (1) {
-+#else
- if (xhci->hci_version == 0x100) {
-+#endif
- if (urb->transfer_buffer_length > 0) {
- if (setup->bRequestType & USB_DIR_IN)
- field |= TRB_TX_TYPE(TRB_DATA_IN);
-@@ -3522,7 +3593,12 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
- field = TRB_TYPE(TRB_DATA);
-
- length_field = TRB_LEN(urb->transfer_buffer_length) |
-+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- xhci_td_remainder(urb->transfer_buffer_length) |
-+#else
-+ //CC: MTK style, no scatter-gather for control transfer
-+ 0 |
-+#endif
- TRB_INTR_TARGET(0);
- if (urb->transfer_buffer_length > 0) {
- if (setup->bRequestType & USB_DIR_IN)
-@@ -3533,7 +3609,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
- length_field,
- field | ep_ring->cycle_state);
- }
--
-+
- /* Save the DMA address of the last TRB in the TD */
- td->last_trb = ep_ring->enqueue;
-
-@@ -3645,6 +3721,9 @@ static int xhci_queue_isoc_tx(struct xhc
- u64 start_addr, addr;
- int i, j;
- bool more_trbs_coming;
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ int max_packet;
-+#endif
-
- ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
-
-@@ -3658,6 +3737,21 @@ static int xhci_queue_isoc_tx(struct xhc
- start_trb = &ep_ring->enqueue->generic;
- start_cycle = ep_ring->cycle_state;
-
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ switch(urb->dev->speed){
-+ case USB_SPEED_SUPER:
-+ max_packet = urb->ep->desc.wMaxPacketSize;
-+ break;
-+ case USB_SPEED_HIGH:
-+ case USB_SPEED_FULL:
-+ case USB_SPEED_LOW:
-+ case USB_SPEED_WIRELESS:
-+ case USB_SPEED_UNKNOWN:
-+ max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
-+ break;
-+ }
-+#endif
-+
- urb_priv = urb->hcpriv;
- /* Queue the first TRB, even if it's zero-length */
- for (i = 0; i < num_tds; i++) {
-@@ -3729,9 +3823,13 @@ static int xhci_queue_isoc_tx(struct xhc
- } else {
- td->last_trb = ep_ring->enqueue;
- field |= TRB_IOC;
-+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
-+ if (!(xhci->quirks & XHCI_AVOID_BEI)) {
-+#else
- if (xhci->hci_version == 0x100 &&
- !(xhci->quirks &
- XHCI_AVOID_BEI)) {
-+#endif
- /* Set BEI bit except for the last td */
- if (i < num_tds - 1)
- field |= TRB_BEI;
-@@ -3746,6 +3844,7 @@ static int xhci_queue_isoc_tx(struct xhc
- trb_buff_len = td_remain_len;
-
- /* Set the TRB length, TD size, & interrupter fields. */
-+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
- if (xhci->hci_version < 0x100) {
- remainder = xhci_td_remainder(
- td_len - running_total);
-@@ -3755,6 +3854,10 @@ static int xhci_queue_isoc_tx(struct xhc
- total_packet_count, urb,
- (trbs_per_td - j - 1));
- }
-+#else
-+ remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
-+#endif
-+
- length_field = TRB_LEN(trb_buff_len) |
- remainder |
- TRB_INTR_TARGET(0);
diff --git a/target/linux/ramips/patches-3.10/800-eco.patch b/target/linux/ramips/patches-3.10/800-eco.patch
deleted file mode 100644
index 08b2bb0ad9..0000000000
--- a/target/linux/ramips/patches-3.10/800-eco.patch
+++ /dev/null
@@ -1,12 +0,0 @@
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -101,4 +101,9 @@
- #define MT7620_GPIO_MODE_EPHY 15
- #define MT7620_GPIO_MODE_PA 20
-
-+static inline int mt7620_get_eco(void)
-+{
-+ return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
-+}
-+
- #endif
diff --git a/target/linux/ramips/patches-3.10/999-clk.patch b/target/linux/ramips/patches-3.10/999-clk.patch
deleted file mode 100644
index 22ac33aa54..0000000000
--- a/target/linux/ramips/patches-3.10/999-clk.patch
+++ /dev/null
@@ -1,17 +0,0 @@
-Index: linux-3.10.32/arch/mips/ralink/clk.c
-===================================================================
---- linux-3.10.32.orig/arch/mips/ralink/clk.c 2014-03-12 03:04:05.468396764 +0000
-+++ linux-3.10.32/arch/mips/ralink/clk.c 2014-03-12 03:29:00.220416177 +0000
-@@ -56,6 +56,12 @@
- }
- EXPORT_SYMBOL_GPL(clk_get_rate);
-
-+int clk_set_rate(struct clk *clk, unsigned long rate)
-+{
-+ return -1;
-+}
-+EXPORT_SYMBOL_GPL(clk_set_rate);
-+
- void __init plat_time_init(void)
- {
- struct clk *clk;
diff --git a/target/linux/ramips/patches-3.10/999-memory-detect.patch b/target/linux/ramips/patches-3.10/999-memory-detect.patch
deleted file mode 100644
index 165a1f0ded..0000000000
--- a/target/linux/ramips/patches-3.10/999-memory-detect.patch
+++ /dev/null
@@ -1,32 +0,0 @@
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -80,6 +80,16 @@ void __init device_tree_init(void)
- }
-
- extern struct boot_param_header __image_dtb;
-+static int memory_dtb;
-+
-+static int __init early_init_dt_find_memory(unsigned long node, const char *uname,
-+ int depth, void *data)
-+{
-+ if (depth == 1 && !strcmp(uname, "memory@0"))
-+ memory_dtb = 1;
-+
-+ return 0;
-+}
-
- void __init plat_mem_setup(void)
- {
-@@ -90,8 +100,10 @@ void __init plat_mem_setup(void)
- * parsed resulting in our memory appearing
- */
- __dt_setup_arch(&__image_dtb);
--
-- if (soc_info.mem_size)
-+ of_scan_flat_dt(early_init_dt_find_memory, NULL);
-+ if (memory_dtb)
-+ of_scan_flat_dt(early_init_dt_scan_memory, NULL);
-+ else if (soc_info.mem_size)
- add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
- BOOT_MEM_RAM);
- else
diff --git a/target/linux/ramips/patches-3.10/999-pinctrl_fixes.patch b/target/linux/ramips/patches-3.10/999-pinctrl_fixes.patch
deleted file mode 100644
index d7ad676f09..0000000000
--- a/target/linux/ramips/patches-3.10/999-pinctrl_fixes.patch
+++ /dev/null
@@ -1,33 +0,0 @@
---- a/drivers/pinctrl/pinctrl-rt2880.c
-+++ b/drivers/pinctrl/pinctrl-rt2880.c
-@@ -204,6 +204,7 @@ static int rt2880_pmx_group_enable(struc
- {
- struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
- u32 mode = 0;
-+ int i;
-
- /* dont allow double use */
- if (p->groups[group].enabled) {
-@@ -217,16 +218,16 @@ static int rt2880_pmx_group_enable(struc
- mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
- mode &= ~(p->groups[group].mask << p->groups[group].shift);
-
-+ /* mark the pins as gpio */
-+ for (i = 0; i < p->groups[group].func[0].pin_count; i++)
-+ p->gpio[p->groups[group].func[0].pins[i]] = 1;
-+
- /* function 0 is gpio and needs special handling */
- if (func == 0) {
-- int i;
--
--
- mode |= p->groups[group].gpio << p->groups[group].shift;
-- /* mark the pins as gpio */
-- for (i = 0; i < p->groups[group].func[0].pin_count; i++)
-- p->gpio[p->groups[group].func[0].pins[i]] = 1;
- } else {
-+ for (i = 0; i < p->func[func]->pin_count; i++)
-+ p->gpio[p->func[func]->pins[i]] = 0;
- mode |= p->func[func]->value << p->groups[group].shift;
- }
- rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
diff --git a/target/linux/ramips/patches-3.10/999-raeth_fixes.patch b/target/linux/ramips/patches-3.10/999-raeth_fixes.patch
deleted file mode 100644
index 5e1bb4d2ec..0000000000
--- a/target/linux/ramips/patches-3.10/999-raeth_fixes.patch
+++ /dev/null
@@ -1,21 +0,0 @@
---- a/drivers/net/ethernet/ralink/ralink_soc_eth.c
-+++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c
-@@ -335,7 +335,7 @@ static int fe_start_xmit(struct sk_buff
- if (priv->soc->tso)
- fe_start_tso(skb, dev, nr_frags, tx);
-
-- if (skb_shinfo(skb)->gso_segs > 1) {
-+ if (priv->soc->tso && (skb_shinfo(skb)->gso_segs > 1)) {
- struct iphdr *iph = NULL;
- struct tcphdr *th = NULL;
- struct ipv6hdr *ip6h = NULL;
-@@ -741,8 +741,7 @@ static int fe_probe(struct platform_devi
- dev_info(&pdev->dev, "Enabling TSO\n");
- netdev->features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
- }
--
-- netdev->hw_features = netdev->vlan_features = netdev->features;
-+ netdev->hw_features = netdev->features;
-
- netdev->irq = platform_get_irq(pdev, 0);
- if (netdev->irq < 0) {
diff --git a/target/linux/ramips/rt288x/config-3.10 b/target/linux/ramips/rt288x/config-3.10
index a3a12a9e7f..f1ae652ec6 100644
--- a/target/linux/ramips/rt288x/config-3.10
+++ b/target/linux/ramips/rt288x/config-3.10
@@ -1,6 +1,7 @@
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
@@ -82,6 +83,7 @@ CONFIG_IRQCHIP=y
CONFIG_IRQ_CPU=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
CONFIG_IRQ_WORK=y
CONFIG_M25PXX_USE_FAST_READ=y
CONFIG_MDIO_BOARDINFO=y
@@ -127,6 +129,7 @@ CONFIG_PINMUX=y
# CONFIG_PREEMPT_RCU is not set
CONFIG_RALINK=y
CONFIG_RALINK_WDT=y
+CONFIG_RA_NAT_NONE=y
# CONFIG_RCU_STALL_COMMON is not set
CONFIG_RESET_CONTROLLER=y
# CONFIG_SCSI_DMA is not set
@@ -136,6 +139,7 @@ CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SOC_MT7620 is not set
+# CONFIG_SOC_MT7621 is not set
CONFIG_SOC_RT288X=y
# CONFIG_SOC_RT305X is not set
# CONFIG_SOC_RT3883 is not set
--
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